\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
control register 1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CEN : Counter enable
bits : 0 - 0 (1 bit)
UDIS : Update disable
bits : 1 - 1 (1 bit)
URS : Update request source
bits : 2 - 2 (1 bit)
OPM : One-pulse mode
bits : 3 - 3 (1 bit)
DIR : Direction
bits : 4 - 4 (1 bit)
CMS : Center-aligned mode selection
bits : 5 - 6 (2 bit)
ARPE : Auto-reload preload enable
bits : 7 - 7 (1 bit)
CKD : Clock division
bits : 8 - 9 (2 bit)
UIFREMAP : UIF status bit remapping
bits : 11 - 11 (1 bit)
DITHEN : Dithering Enable
bits : 12 - 12 (1 bit)
status register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UIF : Update interrupt flag
bits : 0 - 0 (1 bit)
CC1IF : Capture/compare 1 interrupt flag
bits : 1 - 1 (1 bit)
CC2IF : Capture/Compare 2 interrupt flag
bits : 2 - 2 (1 bit)
CC3IF : Capture/Compare 3 interrupt flag
bits : 3 - 3 (1 bit)
CC4IF : Capture/Compare 4 interrupt flag
bits : 4 - 4 (1 bit)
COMIF : COM interrupt flag
bits : 5 - 5 (1 bit)
TIF : Trigger interrupt flag
bits : 6 - 6 (1 bit)
BIF : Break interrupt flag
bits : 7 - 7 (1 bit)
B2IF : Break 2 interrupt flag
bits : 8 - 8 (1 bit)
CC1OF : Capture/Compare 1 overcapture flag
bits : 9 - 9 (1 bit)
CC2OF : Capture/compare 2 overcapture flag
bits : 10 - 10 (1 bit)
CC3OF : Capture/Compare 3 overcapture flag
bits : 11 - 11 (1 bit)
CC4OF : Capture/Compare 4 overcapture flag
bits : 12 - 12 (1 bit)
SBIF : System Break interrupt flag
bits : 13 - 13 (1 bit)
CC5IF : Compare 5 interrupt flag
bits : 16 - 16 (1 bit)
CC6IF : Compare 6 interrupt flag
bits : 17 - 17 (1 bit)
IDXF : Index interrupt flag
bits : 20 - 20 (1 bit)
DIRF : Direction Change interrupt flag
bits : 21 - 21 (1 bit)
IERRF : Index Error interrupt flag
bits : 22 - 22 (1 bit)
TERRF : Transition Error interrupt flag
bits : 23 - 23 (1 bit)
event generation register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
UG : Update generation
bits : 0 - 0 (1 bit)
CC1G : Capture/compare 1 generation
bits : 1 - 1 (1 bit)
CC2G : Capture/compare 2 generation
bits : 2 - 2 (1 bit)
CC3G : Capture/compare 3 generation
bits : 3 - 3 (1 bit)
CC4G : Capture/compare 4 generation
bits : 4 - 4 (1 bit)
COMG : Capture/Compare control update generation
bits : 5 - 5 (1 bit)
TG : Trigger generation
bits : 6 - 6 (1 bit)
BG : Break generation
bits : 7 - 7 (1 bit)
B2G : Break 2 generation
bits : 8 - 8 (1 bit)
capture/compare mode register 1 (output mode)
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC1S : Capture/Compare 1 selection
bits : 0 - 1 (2 bit)
OC1FE : Output Compare 1 fast enable
bits : 2 - 2 (1 bit)
OC1PE : Output Compare 1 preload enable
bits : 3 - 3 (1 bit)
OC1M : Output Compare 1 mode
bits : 4 - 6 (3 bit)
OC1CE : Output Compare 1 clear enable
bits : 7 - 7 (1 bit)
CC2S : Capture/Compare 2 selection
bits : 8 - 9 (2 bit)
OC2FE : Output Compare 2 fast enable
bits : 10 - 10 (1 bit)
OC2PE : Output Compare 2 preload enable
bits : 11 - 11 (1 bit)
OC2M : Output Compare 2 mode
bits : 12 - 14 (3 bit)
OC2CE : Output Compare 2 clear enable
bits : 15 - 15 (1 bit)
OC1M_3 : Output Compare 1 mode - bit 3
bits : 16 - 16 (1 bit)
OC2M_3 : Output Compare 2 mode - bit 3
bits : 24 - 24 (1 bit)
capture/compare mode register 1 (input mode)
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CCMR1_Output
reset_Mask : 0x0
CC1S : Capture/Compare 1 selection
bits : 0 - 1 (2 bit)
ICPCS : Input capture 1 prescaler
bits : 2 - 3 (2 bit)
IC1F : Input capture 1 filter
bits : 4 - 7 (4 bit)
CC2S : Capture/Compare 2 selection
bits : 8 - 9 (2 bit)
IC2PSC : Input capture 2 prescaler
bits : 10 - 11 (2 bit)
IC2F : Input capture 2 filter
bits : 12 - 15 (4 bit)
capture/compare mode register 2 (output mode)
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC3S : Capture/Compare 3 selection
bits : 0 - 1 (2 bit)
OC3FE : Output compare 3 fast enable
bits : 2 - 2 (1 bit)
OC3PE : Output compare 3 preload enable
bits : 3 - 3 (1 bit)
OC3M : Output compare 3 mode
bits : 4 - 6 (3 bit)
OC3CE : Output compare 3 clear enable
bits : 7 - 7 (1 bit)
CC4S : Capture/Compare 4 selection
bits : 8 - 9 (2 bit)
OC4FE : Output compare 4 fast enable
bits : 10 - 10 (1 bit)
OC4PE : Output compare 4 preload enable
bits : 11 - 11 (1 bit)
OC4M : Output compare 4 mode
bits : 12 - 14 (3 bit)
OC4CE : Output compare 4 clear enable
bits : 15 - 15 (1 bit)
OC3M_3 : Output Compare 3 mode - bit 3
bits : 16 - 16 (1 bit)
OC4M_3 : Output Compare 4 mode - bit 3
bits : 24 - 24 (1 bit)
capture/compare mode register 2 (input mode)
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CCMR2_Output
reset_Mask : 0x0
CC3S : Capture/compare 3 selection
bits : 0 - 1 (2 bit)
IC3PSC : Input capture 3 prescaler
bits : 2 - 3 (2 bit)
IC3F : Input capture 3 filter
bits : 4 - 7 (4 bit)
CC4S : Capture/Compare 4 selection
bits : 8 - 9 (2 bit)
IC4PSC : Input capture 4 prescaler
bits : 10 - 11 (2 bit)
IC4F : Input capture 4 filter
bits : 12 - 15 (4 bit)
capture/compare enable register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC1E : Capture/Compare 1 output enable
bits : 0 - 0 (1 bit)
CC1P : Capture/Compare 1 output Polarity
bits : 1 - 1 (1 bit)
CC1NE : Capture/Compare 1 complementary output enable
bits : 2 - 2 (1 bit)
CC1NP : Capture/Compare 1 output Polarity
bits : 3 - 3 (1 bit)
CC2E : Capture/Compare 2 output enable
bits : 4 - 4 (1 bit)
CC2P : Capture/Compare 2 output Polarity
bits : 5 - 5 (1 bit)
CC2NE : Capture/Compare 2 complementary output enable
bits : 6 - 6 (1 bit)
CC2NP : Capture/Compare 2 output Polarity
bits : 7 - 7 (1 bit)
CC3E : Capture/Compare 3 output enable
bits : 8 - 8 (1 bit)
CC3P : Capture/Compare 3 output Polarity
bits : 9 - 9 (1 bit)
CC3NE : Capture/Compare 3 complementary output enable
bits : 10 - 10 (1 bit)
CC3NP : Capture/Compare 3 output Polarity
bits : 11 - 11 (1 bit)
CC4E : Capture/Compare 4 output enable
bits : 12 - 12 (1 bit)
CC4P : Capture/Compare 3 output Polarity
bits : 13 - 13 (1 bit)
CC4NE : Capture/Compare 4 complementary output enable
bits : 14 - 14 (1 bit)
CC4NP : Capture/Compare 4 complementary output polarity
bits : 15 - 15 (1 bit)
CC5E : Capture/Compare 5 output enable
bits : 16 - 16 (1 bit)
CC5P : Capture/Compare 5 output polarity
bits : 17 - 17 (1 bit)
CC6E : Capture/Compare 6 output enable
bits : 20 - 20 (1 bit)
CC6P : Capture/Compare 6 output polarity
bits : 21 - 21 (1 bit)
counter
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : counter value
bits : 0 - 15 (16 bit)
access : read-write
UIFCPY : UIFCPY
bits : 31 - 31 (1 bit)
access : read-only
prescaler
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSC : Prescaler value
bits : 0 - 15 (16 bit)
auto-reload register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARR : Auto-reload value
bits : 0 - 15 (16 bit)
repetition counter register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REP : Repetition counter value
bits : 0 - 15 (16 bit)
capture/compare register 1
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCR1 : Capture/Compare 1 value
bits : 0 - 15 (16 bit)
capture/compare register 2
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCR2 : Capture/Compare 2 value
bits : 0 - 15 (16 bit)
capture/compare register 3
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCR3 : Capture/Compare value
bits : 0 - 15 (16 bit)
control register
address_offset : 0x3DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBA : DMA base address
bits : 0 - 4 (5 bit)
DBL : DMA burst length
bits : 8 - 12 (5 bit)
DMA address for full transfer
address_offset : 0x3E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAB : DMA register for burst accesses
bits : 0 - 31 (32 bit)
control register 2
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCPC : Capture/compare preloaded control
bits : 0 - 0 (1 bit)
CCUS : Capture/compare control update selection
bits : 2 - 2 (1 bit)
CCDS : Capture/compare DMA selection
bits : 3 - 3 (1 bit)
MMS : Master mode selection
bits : 4 - 6 (3 bit)
TI1S : TI1 selection
bits : 7 - 7 (1 bit)
OIS1 : Output Idle state 1
bits : 8 - 8 (1 bit)
OIS1N : Output Idle state 1
bits : 9 - 9 (1 bit)
OIS2 : Output Idle state 2
bits : 10 - 10 (1 bit)
OIS2N : Output Idle state 2
bits : 11 - 11 (1 bit)
OIS3 : Output Idle state 3
bits : 12 - 12 (1 bit)
OIS3N : Output Idle state 3
bits : 13 - 13 (1 bit)
OIS4 : Output Idle state 4
bits : 14 - 14 (1 bit)
OIS4N : Output Idle state 4 (OC4N output)
bits : 15 - 15 (1 bit)
OIS5 : Output Idle state 5 (OC5 output)
bits : 16 - 16 (1 bit)
OIS6 : Output Idle state 6 (OC6 output)
bits : 18 - 18 (1 bit)
MMS2 : Master mode selection 2
bits : 20 - 23 (4 bit)
MMS_3 : Master mode selection - bit 3
bits : 25 - 25 (1 bit)
capture/compare register 4
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCR4 : Capture/Compare value
bits : 0 - 15 (16 bit)
break and dead-time register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTG : Dead-time generator setup
bits : 0 - 7 (8 bit)
LOCK : Lock configuration
bits : 8 - 9 (2 bit)
OSSI : Off-state selection for Idle mode
bits : 10 - 10 (1 bit)
OSSR : Off-state selection for Run mode
bits : 11 - 11 (1 bit)
BKE : Break enable
bits : 12 - 12 (1 bit)
BKP : Break polarity
bits : 13 - 13 (1 bit)
AOE : Automatic output enable
bits : 14 - 14 (1 bit)
MOE : Main output enable
bits : 15 - 15 (1 bit)
BKF : Break filter
bits : 16 - 19 (4 bit)
BK2F : Break 2 filter
bits : 20 - 23 (4 bit)
BK2E : Break 2 Enable
bits : 24 - 24 (1 bit)
BK2P : Break 2 polarity
bits : 25 - 25 (1 bit)
BKDSRM : BKDSRM
bits : 26 - 26 (1 bit)
BK2DSRM : BK2DSRM
bits : 27 - 27 (1 bit)
BKBID : BKBID
bits : 28 - 28 (1 bit)
BK2ID : BK2ID
bits : 29 - 29 (1 bit)
capture/compare register 4
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCR5 : Capture/Compare value
bits : 0 - 15 (16 bit)
GC5C1 : Group Channel 5 and Channel 1
bits : 29 - 29 (1 bit)
GC5C2 : Group Channel 5 and Channel 2
bits : 30 - 30 (1 bit)
GC5C3 : Group Channel 5 and Channel 3
bits : 31 - 31 (1 bit)
capture/compare register 4
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCR6 : Capture/Compare value
bits : 0 - 15 (16 bit)
capture/compare mode register 2 (output mode)
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OC5FE : Output compare 5 fast enable
bits : 2 - 2 (1 bit)
OC5PE : Output compare 5 preload enable
bits : 3 - 3 (1 bit)
OC5M : Output compare 5 mode
bits : 4 - 6 (3 bit)
OC5CE : Output compare 5 clear enable
bits : 7 - 7 (1 bit)
OC6FE : Output compare 6 fast enable
bits : 10 - 10 (1 bit)
OC6PE : Output compare 6 preload enable
bits : 11 - 11 (1 bit)
OC6M : Output compare 6 mode
bits : 12 - 14 (3 bit)
OC6CE : Output compare 6 clear enable
bits : 15 - 15 (1 bit)
OC5M_bit3 : Output Compare 5 mode bit 3
bits : 16 - 18 (3 bit)
OC6M_bit3 : Output Compare 6 mode bit 3
bits : 24 - 24 (1 bit)
timer Deadtime Register 2
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTGF : Dead-time falling edge generator setup
bits : 0 - 7 (8 bit)
DTAE : Deadtime Asymmetric Enable
bits : 16 - 16 (1 bit)
DTPE : Deadtime Preload Enable
bits : 17 - 17 (1 bit)
DMA control register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IE : Index Enable
bits : 0 - 0 (1 bit)
IDIR : Index Direction
bits : 1 - 2 (2 bit)
IBLK : Index Blanking
bits : 3 - 4 (2 bit)
FIDX : First Index
bits : 5 - 5 (1 bit)
IPOS : Index Positioning
bits : 6 - 7 (2 bit)
PW : Pulse width
bits : 16 - 23 (8 bit)
PWPRSC : Pulse Width prescaler
bits : 24 - 26 (3 bit)
TIM timer input selection register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TI1SEL : TI1[0] to TI1[15] input selection
bits : 0 - 3 (4 bit)
TI2SEL : TI2[0] to TI2[15] input selection
bits : 8 - 11 (4 bit)
TI3SEL : TI3[0] to TI3[15] input selection
bits : 16 - 19 (4 bit)
TI4SEL : TI4[0] to TI4[15] input selection
bits : 24 - 27 (4 bit)
TIM alternate function option register 1
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKINE : BRK BKIN input enable
bits : 0 - 0 (1 bit)
BKCMP1E : BRK COMP1 enable
bits : 1 - 1 (1 bit)
BKCMP2E : BRK COMP2 enable
bits : 2 - 2 (1 bit)
BKCMP3E : BRK COMP3 enable
bits : 3 - 3 (1 bit)
BKCMP4E : BRK COMP4 enable
bits : 4 - 4 (1 bit)
BKCMP5E : BRK COMP5 enable
bits : 5 - 5 (1 bit)
BKCMP6E : BRK COMP6 enable
bits : 6 - 6 (1 bit)
BKCMP7E : BRK COMP7 enable
bits : 7 - 7 (1 bit)
BKINP : BRK BKIN input polarity
bits : 9 - 9 (1 bit)
BKCMP1P : BRK COMP1 input polarity
bits : 10 - 10 (1 bit)
BKCMP2P : BRK COMP2 input polarity
bits : 11 - 11 (1 bit)
BKCMP3P : BRK COMP3 input polarity
bits : 12 - 12 (1 bit)
BKCMP4P : BRK COMP4 input polarity
bits : 13 - 13 (1 bit)
ETRSEL : ETR source selection
bits : 14 - 17 (4 bit)
TIM alternate function option register 2
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKINE : BRK BKIN input enable
bits : 0 - 0 (1 bit)
BK2CMP1E : BRK2 COMP1 enable
bits : 1 - 1 (1 bit)
BK2CMP2E : BRK2 COMP2 enable
bits : 2 - 2 (1 bit)
BK2CMP3E : BRK2 COMP3 enable
bits : 3 - 3 (1 bit)
BK2CMP4E : BRK2 COMP4 enable
bits : 4 - 4 (1 bit)
BK2CMP5E : BRK2 COMP5 enable
bits : 5 - 5 (1 bit)
BK2CMP6E : BRK2 COMP6 enable
bits : 6 - 6 (1 bit)
BK2CMP7E : BRK2 COMP7 enable
bits : 7 - 7 (1 bit)
BK2INP : BRK2 BKIN input polarity
bits : 9 - 9 (1 bit)
BK2CMP1P : BRK2 COMP1 input polarity
bits : 10 - 10 (1 bit)
BK2CMP2P : BRK2 COMP2 input polarity
bits : 11 - 11 (1 bit)
BK2CMP3P : BRK2 COMP3 input polarity
bits : 12 - 12 (1 bit)
BK2CMP4P : BRK2 COMP4 input polarity
bits : 13 - 13 (1 bit)
OCRSEL : OCREF_CLR source selection
bits : 16 - 18 (3 bit)
slave mode control register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SMS : Slave mode selection
bits : 0 - 2 (3 bit)
OCCS : OCREF clear selection
bits : 3 - 3 (1 bit)
TS : Trigger selection
bits : 4 - 6 (3 bit)
MSM : Master/Slave mode
bits : 7 - 7 (1 bit)
ETF : External trigger filter
bits : 8 - 11 (4 bit)
ETPS : External trigger prescaler
bits : 12 - 13 (2 bit)
ECE : External clock enable
bits : 14 - 14 (1 bit)
ETP : External trigger polarity
bits : 15 - 15 (1 bit)
SMS_3 : Slave mode selection - bit 3
bits : 16 - 16 (1 bit)
TS_4_3 : Trigger selection - bit 4:3
bits : 20 - 21 (2 bit)
SMSPE : SMS Preload Enable
bits : 24 - 24 (1 bit)
SMSPS : SMS Preload Source
bits : 25 - 25 (1 bit)
DMA/Interrupt enable register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UIE : Update interrupt enable
bits : 0 - 0 (1 bit)
CC1IE : Capture/Compare 1 interrupt enable
bits : 1 - 1 (1 bit)
CC2IE : Capture/Compare 2 interrupt enable
bits : 2 - 2 (1 bit)
CC3IE : Capture/Compare 3 interrupt enable
bits : 3 - 3 (1 bit)
CC4IE : Capture/Compare 4 interrupt enable
bits : 4 - 4 (1 bit)
COMIE : COM interrupt enable
bits : 5 - 5 (1 bit)
TIE : Trigger interrupt enable
bits : 6 - 6 (1 bit)
BIE : Break interrupt enable
bits : 7 - 7 (1 bit)
UDE : Update DMA request enable
bits : 8 - 8 (1 bit)
CC1DE : Capture/Compare 1 DMA request enable
bits : 9 - 9 (1 bit)
CC2DE : Capture/Compare 2 DMA request enable
bits : 10 - 10 (1 bit)
CC3DE : Capture/Compare 3 DMA request enable
bits : 11 - 11 (1 bit)
CC4DE : Capture/Compare 4 DMA request enable
bits : 12 - 12 (1 bit)
COMDE : COM DMA request enable
bits : 13 - 13 (1 bit)
TDE : Trigger DMA request enable
bits : 14 - 14 (1 bit)
IDXIE : Index interrupt enable
bits : 20 - 20 (1 bit)
DIRIE : Direction Change interrupt enable
bits : 21 - 21 (1 bit)
IERRIE : Index Error interrupt enable
bits : 22 - 22 (1 bit)
TERRIE : Transition Error interrupt enable
bits : 23 - 23 (1 bit)
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