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address_offset : 0x0 Bytes (0x0)
size : 0x2A byte (0x0)
mem_usage : registers
protection : not protected
Remap Memory register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MEM_MODE : Memory mapping selection
bits : 0 - 2 (3 bit)
FB_mode : User Flash Bank mode
bits : 8 - 8 (1 bit)
external interrupt configuration register 3
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXTI8 : EXTI x configuration (x = 8 to 11)
bits : 0 - 3 (4 bit)
EXTI9 : EXTI x configuration (x = 8 to 11)
bits : 4 - 7 (4 bit)
EXTI10 : EXTI10
bits : 8 - 11 (4 bit)
EXTI11 : EXTI x configuration (x = 8 to 11)
bits : 12 - 15 (4 bit)
external interrupt configuration register 4
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXTI12 : EXTI x configuration (x = 12 to 15)
bits : 0 - 3 (4 bit)
EXTI13 : EXTI x configuration (x = 12 to 15)
bits : 4 - 7 (4 bit)
EXTI14 : EXTI x configuration (x = 12 to 15)
bits : 8 - 11 (4 bit)
EXTI15 : EXTI x configuration (x = 12 to 15)
bits : 12 - 15 (4 bit)
CCM SRAM control and status register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCMER : CCM SRAM Erase
bits : 0 - 0 (1 bit)
access : read-write
CCMBSY : CCM SRAM busy by erase operation
bits : 1 - 1 (1 bit)
access : read-only
configuration register 2
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLL : Core Lockup Lock
bits : 0 - 0 (1 bit)
SPL : SRAM Parity Lock
bits : 1 - 1 (1 bit)
PVDL : PVD Lock
bits : 2 - 2 (1 bit)
ECCL : ECC Lock
bits : 3 - 3 (1 bit)
SPF : SRAM Parity Flag
bits : 8 - 8 (1 bit)
SRAM Write protection register 1
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Page0_WP : Write protection
bits : 0 - 0 (1 bit)
Page1_WP : Write protection
bits : 1 - 1 (1 bit)
Page2_WP : Write protection
bits : 2 - 2 (1 bit)
Page3_WP : Write protection
bits : 3 - 3 (1 bit)
Page4_WP : Write protection
bits : 4 - 4 (1 bit)
Page5_WP : Write protection
bits : 5 - 5 (1 bit)
Page6_WP : Write protection
bits : 6 - 6 (1 bit)
Page7_WP : Write protection
bits : 7 - 7 (1 bit)
Page8_WP : Write protection
bits : 8 - 8 (1 bit)
Page9_WP : Write protection
bits : 9 - 9 (1 bit)
Page10_WP : Write protection
bits : 10 - 10 (1 bit)
Page11_WP : Write protection
bits : 11 - 11 (1 bit)
Page12_WP : Write protection
bits : 12 - 12 (1 bit)
Page13_WP : Write protection
bits : 13 - 13 (1 bit)
Page14_WP : Write protection
bits : 14 - 14 (1 bit)
Page15_WP : Write protection
bits : 15 - 15 (1 bit)
Page16_WP : Write protection
bits : 16 - 16 (1 bit)
Page17_WP : Write protection
bits : 17 - 17 (1 bit)
Page18_WP : Write protection
bits : 18 - 18 (1 bit)
Page19_WP : Write protection
bits : 19 - 19 (1 bit)
Page20_WP : Write protection
bits : 20 - 20 (1 bit)
Page21_WP : Write protection
bits : 21 - 21 (1 bit)
Page22_WP : Write protection
bits : 22 - 22 (1 bit)
Page23_WP : Write protection
bits : 23 - 23 (1 bit)
Page24_WP : Write protection
bits : 24 - 24 (1 bit)
Page25_WP : Write protection
bits : 25 - 25 (1 bit)
Page26_WP : Write protection
bits : 26 - 26 (1 bit)
Page27_WP : Write protection
bits : 27 - 27 (1 bit)
Page28_WP : Write protection
bits : 28 - 28 (1 bit)
Page29_WP : Write protection
bits : 29 - 29 (1 bit)
Page30_WP : Write protection
bits : 30 - 30 (1 bit)
Page31_WP : Write protection
bits : 31 - 31 (1 bit)
SRAM2 Key Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
KEY : SRAM2 Key for software erase
bits : 0 - 7 (8 bit)
peripheral mode configuration register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOOSTEN : BOOSTEN
bits : 8 - 8 (1 bit)
ANASWVDD : GPIO analog switch control voltage selection
bits : 9 - 9 (1 bit)
I2C_PB6_FMP : FM+ drive capability on PB6
bits : 16 - 16 (1 bit)
I2C_PB7_FMP : FM+ drive capability on PB6
bits : 17 - 17 (1 bit)
I2C_PB8_FMP : FM+ drive capability on PB6
bits : 18 - 18 (1 bit)
I2C_PB9_FMP : FM+ drive capability on PB6
bits : 19 - 19 (1 bit)
I2C1_FMP : I2C1 FM+ drive capability enable
bits : 20 - 20 (1 bit)
I2C2_FMP : I2C1 FM+ drive capability enable
bits : 21 - 21 (1 bit)
I2C3_FMP : I2C1 FM+ drive capability enable
bits : 22 - 22 (1 bit)
I2C4_FMP : I2C1 FM+ drive capability enable
bits : 23 - 23 (1 bit)
FPU_IE : FPU Interrupts Enable
bits : 26 - 31 (6 bit)
external interrupt configuration register 1
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXTI0 : EXTI x configuration (x = 0 to 3)
bits : 0 - 3 (4 bit)
EXTI1 : EXTI x configuration (x = 0 to 3)
bits : 4 - 7 (4 bit)
EXTI2 : EXTI x configuration (x = 0 to 3)
bits : 8 - 11 (4 bit)
EXTI3 : EXTI x configuration (x = 0 to 3)
bits : 12 - 15 (4 bit)
external interrupt configuration register 2
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXTI4 : EXTI x configuration (x = 4 to 7)
bits : 0 - 3 (4 bit)
EXTI5 : EXTI x configuration (x = 4 to 7)
bits : 4 - 7 (4 bit)
EXTI6 : EXTI x configuration (x = 4 to 7)
bits : 8 - 11 (4 bit)
EXTI7 : EXTI x configuration (x = 4 to 7)
bits : 12 - 15 (4 bit)
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