\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Enable
bits : 0 - 0 (1 bit)
ABORT : Abort request
bits : 1 - 1 (1 bit)
DMAEN : DMA enable
bits : 2 - 2 (1 bit)
TCEN : Timeout counter enable
bits : 3 - 3 (1 bit)
SSHIFT : Sample shift
bits : 4 - 4 (1 bit)
DFM : DFM
bits : 6 - 6 (1 bit)
FSEL : FSEL
bits : 7 - 7 (1 bit)
FTHRES : IFO threshold level
bits : 8 - 12 (5 bit)
TEIE : Transfer error interrupt enable
bits : 16 - 16 (1 bit)
TCIE : Transfer complete interrupt enable
bits : 17 - 17 (1 bit)
FTIE : FIFO threshold interrupt enable
bits : 18 - 18 (1 bit)
SMIE : Status match interrupt enable
bits : 19 - 19 (1 bit)
TOIE : TimeOut interrupt enable
bits : 20 - 20 (1 bit)
APMS : Automatic poll mode stop
bits : 22 - 22 (1 bit)
PMM : Polling match mode
bits : 23 - 23 (1 bit)
PRESCALER : Clock prescaler
bits : 24 - 31 (8 bit)
data length register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DL : Data length
bits : 0 - 31 (32 bit)
communication configuration register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INSTRUCTION : Instruction
bits : 0 - 7 (8 bit)
IMODE : Instruction mode
bits : 8 - 9 (2 bit)
ADMODE : Address mode
bits : 10 - 11 (2 bit)
ADSIZE : Address size
bits : 12 - 13 (2 bit)
ABMODE : Alternate bytes mode
bits : 14 - 15 (2 bit)
ABSIZE : Alternate bytes size
bits : 16 - 17 (2 bit)
DCYC : Number of dummy cycles
bits : 18 - 22 (5 bit)
DMODE : Data mode
bits : 24 - 25 (2 bit)
FMODE : Functional mode
bits : 26 - 27 (2 bit)
SIOO : Send instruction only once mode
bits : 28 - 28 (1 bit)
DDRM : Double data rate mode
bits : 31 - 31 (1 bit)
address register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDRESS : Address
bits : 0 - 31 (32 bit)
ABR
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ALTERNATE : ALTERNATE
bits : 0 - 31 (32 bit)
data register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data
bits : 0 - 31 (32 bit)
polling status mask register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MASK : Status mask
bits : 0 - 31 (32 bit)
polling status match register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCH : Status match
bits : 0 - 31 (32 bit)
polling interval register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTERVAL : Polling interval
bits : 0 - 15 (16 bit)
low-power timeout register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIMEOUT : Timeout period
bits : 0 - 15 (16 bit)
device configuration register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMODE : Mode 0 / mode 3
bits : 0 - 0 (1 bit)
CSHT : Chip select high time
bits : 8 - 10 (3 bit)
FSIZE : FLASH memory size
bits : 16 - 20 (5 bit)
status register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEF : Transfer error flag
bits : 0 - 0 (1 bit)
TCF : Transfer complete flag
bits : 1 - 1 (1 bit)
FTF : FIFO threshold flag
bits : 2 - 2 (1 bit)
SMF : Status match flag
bits : 3 - 3 (1 bit)
TOF : Timeout flag
bits : 4 - 4 (1 bit)
BUSY : Busy
bits : 5 - 5 (1 bit)
FLEVEL : FIFO level
bits : 8 - 12 (5 bit)
flag clear register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTEF : Clear transfer error flag
bits : 0 - 0 (1 bit)
CTCF : Clear transfer complete flag
bits : 1 - 1 (1 bit)
CSMF : Clear status match flag
bits : 3 - 3 (1 bit)
CTOF : Clear timeout flag
bits : 4 - 4 (1 bit)
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