\n
address_offset : 0x0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xC Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xB Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x10 Bytes (0x0)
size : 0xC4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x210 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
DMA Request Selection Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USBEP1 : The EP1 DRQ interrupt signal of the USB ch.0 is output as a transfer request to the DMAC.
bits : 0 - -1 (0 bit)
access : read-write
USBEP2 : The EP2 DRQ interrupt signal of the USB ch.0 is output as a transfer request to the DMAC.
bits : 1 - 0 (0 bit)
access : read-write
USBEP3 : The EP3 DRQ interrupt signal of the USB ch.0 is output as a transfer request to the DMAC.
bits : 2 - 1 (0 bit)
access : read-write
USBEP4 : The EP4 DRQ interrupt signal of the USB ch.0 is output as a transfer request to the DMAC.
bits : 3 - 2 (0 bit)
access : read-write
USBEP5 : The EP5 DRQ interrupt signal of the USB ch.0 is output as a transfer request to the DMAC.
bits : 4 - 3 (0 bit)
access : read-write
ADCSCAN0 : The scan conversion interrupt signal of the A/D converter unit 0 is output as a transfer request to the DMAC.
bits : 5 - 4 (0 bit)
access : read-write
ADCSCAN1 : The scan conversion interrupt signal of the A/D converter unit 1 is output as a transfer request to the DMAC.
bits : 6 - 5 (0 bit)
access : read-write
ADCSCAN2 : The scan conversion interrupt signal of the A/D converter unit 2 is output as a transfer request to the DMAC.
bits : 7 - 6 (0 bit)
access : read-write
IRQ0BT0 : The IRQ0 interrupt signal of the base timer ch.0 is output as a transfer request to the DMAC.
bits : 8 - 7 (0 bit)
access : read-write
IRQ0BT2 : The IRQ0 interrupt signal of the base timer ch.3 is output as a transfer request to the DMAC.
bits : 9 - 8 (0 bit)
access : read-write
IRQ0BT3 : The IRQ0 interrupt signal of the base timer ch.3 is output as a transfer request to the DMAC.
bits : 9 - 8 (0 bit)
access : read-write
IRQ0BT4 : The IRQ0 interrupt signal of the base timer ch.4 is output as a transfer request to the DMAC.
bits : 10 - 9 (0 bit)
access : read-write
IRQ0BT6 : The IRQ0 interrupt signal of the base timer ch.6 is output as a transfer request to the DMAC.
bits : 11 - 10 (0 bit)
access : read-write
MFS0RX : The reception interrupt signal of the MFS ch.0 is output as a transfer request to the DMAC (including extension).
bits : 12 - 11 (0 bit)
access : read-write
MFS0TX : The transmission interrupt signal of the MFS ch.0 is output as a transfer request to the DMAC (including extension).
bits : 13 - 12 (0 bit)
access : read-write
MFS1RX : The reception interrupt signal of the MFS ch.1 is output as a transfer request to the DMAC (including extension).
bits : 14 - 13 (0 bit)
access : read-write
MFS1TX : The transmission interrupt signal of the MFS ch.1 is output as a transfer request to the DMAC (including extension).
bits : 15 - 14 (0 bit)
access : read-write
MFS2RX : The reception interrupt signal of the MFS ch.2 is output as a transfer request to the DMAC (including extension).
bits : 16 - 15 (0 bit)
access : read-write
MFS2TX : The transmission interrupt signal of the MFS ch.2 is output as a transfer request to the DMAC (including extension).
bits : 17 - 16 (0 bit)
access : read-write
MFS3RX : The reception interrupt signal of the MFS ch.3 is output as a transfer request to the DMAC (including extension).
bits : 18 - 17 (0 bit)
access : read-write
MFS3TX : The transmission interrupt signal of the MFS ch.3 is output as a transfer request to the DMAC (including extension).
bits : 19 - 18 (0 bit)
access : read-write
MFS4RX : The reception interrupt signal of the MFS ch.4 is output as a transfer request to the DMAC (including extension).
bits : 20 - 19 (0 bit)
access : read-write
MFS4TX : The transmission interrupt signal of the MFS ch.4 is output as a transfer request to the DMAC (including extension).
bits : 21 - 20 (0 bit)
access : read-write
MFS5RX : The reception interrupt signal of the MFS ch.5 is output as a transfer request to the DMAC (including extension).
bits : 22 - 21 (0 bit)
access : read-write
MFS5TX : The transmission interrupt signal of the MFS ch.5 is output as a transfer request to the DMAC (including extension).
bits : 23 - 22 (0 bit)
access : read-write
MFS6RX : The reception interrupt signal of the MFS ch.6 is output as a transfer request to the DMAC (including extension).
bits : 24 - 23 (0 bit)
access : read-write
MFS6TX : The transmission interrupt signal of the MFS ch.6 is output as a transfer request to the DMAC (including extension).
bits : 25 - 24 (0 bit)
access : read-write
MFS7RX : The reception interrupt signal of the MFS ch.7 is output as a transfer request to the DMAC (including extension).
bits : 26 - 25 (0 bit)
access : read-write
MFS7TX : The transmission interrupt signal of the MFS ch.7 is output as a transfer request to the DMAC (including extension).
bits : 27 - 26 (0 bit)
access : read-write
EXINT0 : The interrupt signal of the external interrupt ch.0 is output as a transfer request to the DMAC (including extension).
bits : 28 - 27 (0 bit)
access : read-write
EXINT1 : The interrupt signal of the external interrupt ch.1 is output as a transfer request to the DMAC (including extension).
bits : 29 - 28 (0 bit)
access : read-write
EXINT2 : The interrupt signal of the external interrupt ch.2 is output as a transfer request to the DMAC (including extension).
bits : 30 - 29 (0 bit)
access : read-write
EXINT3 : The interrupt signal of the external interrupt ch.3 is output as a transfer request to the DMAC (including extension).
bits : 31 - 30 (0 bit)
access : read-write
EXC02 batch read register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NMI : External NMIX pin interrupt request
bits : 0 - -1 (0 bit)
access : read-only
HWINT : Hardware watchdog timer interrupt request
bits : 1 - 0 (0 bit)
access : read-only
IRQ00 Batch Read Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FCSINT : Anomalous frequency detection by CSV interrupt request
bits : 0 - -1 (0 bit)
access : read-only
IRQ01 Batch Read Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SWWDTINT : Software watchdog timer interrupt request
bits : 0 - -1 (0 bit)
access : read-only
IRQ02 Batch Read Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LVDINT : Low voltage detection (LVD) interrupt request
bits : 0 - -1 (0 bit)
access : read-only
IRQ03 Batch Read Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WAVE0INT0 : DTIF (motor emergency stop) interrupt request in MFT unit 0
bits : 0 - -1 (0 bit)
access : read-only
WAVE0INT1 : WFG timer 10 interrupt request in MFT unit 0
bits : 1 - 0 (0 bit)
access : read-only
WAVE0INT2 : WFG timer 32 interrupt request in MFT unit 0
bits : 2 - 1 (0 bit)
access : read-only
WAVE0INT3 : WFG timer 54 interrupt request in MFT unit 0
bits : 3 - 2 (0 bit)
access : read-only
WAVE1INT0 : DTIF (motor emergency stop) interrupt request in MFT unit 1
bits : 4 - 3 (0 bit)
access : read-only
WAVE1INT1 : WFG timer 10 interrupt request in MFT unit 1
bits : 5 - 4 (0 bit)
access : read-only
WAVE1INT2 : WFG timer 32 interrupt request in MFT unit 1
bits : 6 - 5 (0 bit)
access : read-only
WAVE1INT3 : WFG timer 54 interrupt request in MFT unit 1
bits : 7 - 6 (0 bit)
access : read-only
WAVE2INT0 : DTIF (motor emergency stop) interrupt request in MFT unit 2
bits : 8 - 7 (0 bit)
access : read-only
WAVE2INT1 : WFG timer 10 interrupt request in MFT unit 2
bits : 9 - 8 (0 bit)
access : read-only
WAVE2INT2 : WFG timer 32 interrupt request in MFT unit 2
bits : 10 - 9 (0 bit)
access : read-only
WAVE2INT3 : WFG timer 54 interrupt request in MFT unit 2
bits : 11 - 10 (0 bit)
access : read-only
Interrupt Factor Selection Register 0
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTSEL0 : select the interrupt factor of the interrupt vector No.19.
bits : 0 - 6 (7 bit)
access : read-write
INTSEL1 : select the interrupt factor of the interrupt vector No.20.
bits : 8 - 14 (7 bit)
access : read-write
INTSEL2 : select the interrupt factor of the interrupt vector No.21.
bits : 16 - 22 (7 bit)
access : read-write
INTSEL3 : select the interrupt factor of the interrupt vector No.22.
bits : 24 - 30 (7 bit)
access : read-write
Interrupt Factor Selection Register 1
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTSEL4 : select the interrupt factor of the interrupt vector No.23.
bits : 0 - 6 (7 bit)
access : read-write
INTSEL5 : select the interrupt factor of the interrupt vector No.24.
bits : 8 - 14 (7 bit)
access : read-write
INTSEL6 : select the interrupt factor of the interrupt vector No.25.
bits : 16 - 22 (7 bit)
access : read-write
INTSEL7 : select the interrupt factor of the interrupt vector No.26.
bits : 24 - 30 (7 bit)
access : read-write
IRQ04 Batch Read Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EXTINT0 : Interrupt request on external interrupt ch.0
bits : 0 - -1 (0 bit)
access : read-only
EXTINT1 : Interrupt request on external interrupt ch.1
bits : 1 - 0 (0 bit)
access : read-only
EXTINT2 : Interrupt request on external interrupt ch.2
bits : 2 - 1 (0 bit)
access : read-only
EXTINT3 : Interrupt request on external interrupt ch.3
bits : 3 - 2 (0 bit)
access : read-only
EXTINT4 : Interrupt request on external interrupt ch.4
bits : 4 - 3 (0 bit)
access : read-only
EXTINT5 : Interrupt request on external interrupt ch.5
bits : 5 - 4 (0 bit)
access : read-only
EXTINT6 : Interrupt request on external interrupt ch.6
bits : 6 - 5 (0 bit)
access : read-only
EXTINT7 : Interrupt request on external interrupt ch.7
bits : 7 - 6 (0 bit)
access : read-only
IRQ05 Batch Read Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EXTINT0 : Interrupt request on external interrupt ch.8
bits : 0 - -1 (0 bit)
access : read-only
EXTINT1 : Interrupt request on external interrupt ch.9
bits : 1 - 0 (0 bit)
access : read-only
EXTINT2 : Interrupt request on external interrupt ch.10
bits : 2 - 1 (0 bit)
access : read-only
EXTINT3 : Interrupt request on external interrupt ch.11
bits : 3 - 2 (0 bit)
access : read-only
EXTINT4 : Interrupt request on external interrupt ch.12
bits : 4 - 3 (0 bit)
access : read-only
EXTINT5 : Interrupt request on external interrupt ch.13
bits : 5 - 4 (0 bit)
access : read-only
EXTINT6 : Interrupt request on external interrupt ch.14
bits : 6 - 5 (0 bit)
access : read-only
EXTINT7 : Interrupt request on external interrupt ch.15
bits : 7 - 6 (0 bit)
access : read-only
IRQ06 Batch Read Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TIMINT1 : Dual timer 1 interrupt request
bits : 0 - -1 (0 bit)
access : read-only
TIMINT2 : Dual timer 2 interrupt request
bits : 1 - 0 (0 bit)
access : read-only
QUD0INT0 : PC match interrupt request on QPRC ch.0
bits : 2 - 1 (0 bit)
access : read-only
QUD0INT1 : PC and RC match interrupt request on QPRC ch.0
bits : 3 - 2 (0 bit)
access : read-only
QUD0INT2 : Overflow/underflow/zero index interrupt request on QPRC ch.0
bits : 4 - 3 (0 bit)
access : read-only
QUD0INT3 : PC count invert interrupt request on QPRC ch.0
bits : 5 - 4 (0 bit)
access : read-only
QUD0INT4 : Interrupt request detected RC out of range on QPRC ch.0
bits : 6 - 5 (0 bit)
access : read-only
QUD0INT5 : PC match and RC match interrupt request on QPRC ch.0
bits : 7 - 6 (0 bit)
access : read-only
QUD1INT0 : PC match interrupt request on QPRC ch.1
bits : 8 - 7 (0 bit)
access : read-only
QUD1INT1 : PC and RC match interrupt request on QPRC ch.1
bits : 9 - 8 (0 bit)
access : read-only
QUD1INT2 : Overflow/underflow/zero index interrupt request on QPRC ch.1
bits : 10 - 9 (0 bit)
access : read-only
QUD1INT3 : PC count invert interrupt request on QPRC ch.1
bits : 11 - 10 (0 bit)
access : read-only
QUD1INT4 : Interrupt request detected RC out of range on QPRC ch.1
bits : 12 - 11 (0 bit)
access : read-only
QUD1INT5 : PC match and RC match interrupt request on QPRC ch.1
bits : 13 - 12 (0 bit)
access : read-only
QUD2INT0 : PC match interrupt request on QPRC ch.2
bits : 14 - 13 (0 bit)
access : read-only
QUD2INT1 : PC and RC match interrupt request on QPRC ch.2
bits : 15 - 14 (0 bit)
access : read-only
QUD2INT2 : Overflow/underflow/zero index interrupt request on QPRC ch.2
bits : 16 - 15 (0 bit)
access : read-only
QUD2INT3 : PC count invert interrupt request on QPRC ch.2
bits : 17 - 16 (0 bit)
access : read-only
QUD2INT4 : Interrupt request detected RC out of range on QPRC ch.2
bits : 18 - 17 (0 bit)
access : read-only
QUD2INT5 : PC match and RC match interrupt request on QPRC ch.2
bits : 19 - 18 (0 bit)
access : read-only
IRQ07 Batch Read Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MFSINT : Reception interrupt request on MFS ch.0
bits : 0 - -1 (0 bit)
access : read-only
IRQ08 Batch Read Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MFSINT0 : Transmission interrupt request on MFS ch.0
bits : 0 - -1 (0 bit)
access : read-only
MFSINT1 : Status interrupt request on MFS ch.0
bits : 1 - 0 (0 bit)
access : read-only
IRQ09 Batch Read Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MFSINT : Reception interrupt request on MFS ch.1
bits : 0 - -1 (0 bit)
access : read-only
IRQ10 Batch Read Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MFSINT0 : Transmission interrupt request on MFS ch.1
bits : 0 - -1 (0 bit)
access : read-only
MFSINT1 : Status interrupt request on MFS ch.1
bits : 1 - 0 (0 bit)
access : read-only
IRQ11 Batch Read Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MFSINT : Reception interrupt request on MFS ch.2
bits : 0 - -1 (0 bit)
access : read-only
IRQ12 Batch Read Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MFSINT0 : Transmission interrupt request on MFS ch.2
bits : 0 - -1 (0 bit)
access : read-only
MFSINT1 : Status interrupt request on MFS ch.2
bits : 1 - 0 (0 bit)
access : read-only
IRQ13 Batch Read Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MFSINT : Reception interrupt request on MFS ch.3
bits : 0 - -1 (0 bit)
access : read-only
IRQ14 Batch Read Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MFSINT0 : Transmission interrupt request on MFS ch.3
bits : 0 - -1 (0 bit)
access : read-only
MFSINT1 : Status interrupt request on MFS ch.3
bits : 1 - 0 (0 bit)
access : read-only
IRQ15 Batch Read Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MFSINT : Reception interrupt request on MFS ch.4
bits : 0 - -1 (0 bit)
access : read-only
IRQ16 Batch Read Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MFSINT0 : Transmission interrupt request on MFS ch.4
bits : 0 - -1 (0 bit)
access : read-only
MFSINT1 : Status interrupt request on MFS ch.4
bits : 1 - 0 (0 bit)
access : read-only
IRQ17 Batch Read Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MFSINT : Reception interrupt request on MFS ch.5
bits : 0 - -1 (0 bit)
access : read-only
IRQ18 Batch Read Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MFSINT0 : Transmission interrupt request on MFS ch.5
bits : 0 - -1 (0 bit)
access : read-only
MFSINT1 : Status interrupt request on MFS ch.5
bits : 1 - 0 (0 bit)
access : read-only
IRQ19 Batch Read Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MFSINT : Reception interrupt request on MFS ch.6
bits : 0 - -1 (0 bit)
access : read-only
IRQ20 Batch Read Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MFSINT0 : Transmission interrupt request on MFS ch.6
bits : 0 - -1 (0 bit)
access : read-only
MFSINT1 : Status interrupt request on MFS ch.6
bits : 1 - 0 (0 bit)
access : read-only
IRQ21 Batch Read Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MFSINT : Reception interrupt request on MFS ch.7
bits : 0 - -1 (0 bit)
access : read-only
IRQ22 Batch Read Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MFSINT0 : Transmission interrupt request on MFS ch.7
bits : 0 - -1 (0 bit)
access : read-only
MFSINT1 : Status interrupt request on MFS ch.7
bits : 1 - 0 (0 bit)
access : read-only
IRQ23 Batch Read Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PPGINT0 : Interrupt request on PPG ch.0
bits : 0 - -1 (0 bit)
access : read-only
PPGINT1 : Interrupt request on PPG ch.2
bits : 1 - 0 (0 bit)
access : read-only
PPGINT2 : Interrupt request on PPG ch.4
bits : 2 - 1 (0 bit)
access : read-only
PPGINT3 : Interrupt request on PPG ch.8
bits : 3 - 2 (0 bit)
access : read-only
PPGINT4 : Interrupt request on PPG ch.10
bits : 4 - 3 (0 bit)
access : read-only
PPGINT5 : Interrupt request on PPG ch.12
bits : 5 - 4 (0 bit)
access : read-only
PPGINT6 : Interrupt request on PPG ch.16
bits : 6 - 5 (0 bit)
access : read-only
PPGINT7 : Interrupt request on PPG ch.18
bits : 7 - 6 (0 bit)
access : read-only
PPGINT8 : Interrupt request on PPG ch.20
bits : 8 - 7 (0 bit)
access : read-only
IRQ24 Batch Read Register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MOSCINT : Stabilization wait completion interrupt request for main clock oscillation
bits : 0 - -1 (0 bit)
access : read-only
SOSCINT : Stabilization wait completion interrupt request for sub-clock oscillation
bits : 1 - 0 (0 bit)
access : read-only
MPLLINT : Stabilization wait completion interrupt request for main PLL oscillation
bits : 2 - 1 (0 bit)
access : read-only
UPLLINT : Stabilization wait completion interrupt request for USB or USB/Ethernet PLL oscillation.
bits : 3 - 2 (0 bit)
access : read-only
WCINT : Watch counter interrupt request
bits : 4 - 3 (0 bit)
access : read-only
RTCINT : RTC interrupt request
bits : 5 - 4 (0 bit)
access : read-only
IRQ25 Batch Read Register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADCINT0 : Priority conversion interrupt request in the corresponding A/D unit 0.
bits : 0 - -1 (0 bit)
access : read-only
ADCINT1 : Scan conversion interrupt request in the corresponding A/D unit 0.
bits : 1 - 0 (0 bit)
access : read-only
ADCINT2 : FIFO overrun interrupt request in the corresponding A/D unit 0.
bits : 2 - 1 (0 bit)
access : read-only
ADCINT3 : Conversion result comparison interrupt request in the corresponding A/D unit 0.
bits : 3 - 2 (0 bit)
access : read-only
IRQ26 Batch Read Register
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADCINT0 : Priority conversion interrupt request in the corresponding A/D unit 1
bits : 0 - -1 (0 bit)
access : read-only
ADCINT1 : Scan conversion interrupt request in the corresponding A/D unit 1
bits : 1 - 0 (0 bit)
access : read-only
ADCINT2 : FIFO overrun interrupt request in the corresponding A/D unit 1
bits : 2 - 1 (0 bit)
access : read-only
ADCINT3 : Conversion result comparison interrupt request in the corresponding A/D unit 1
bits : 3 - 2 (0 bit)
access : read-only
IRQ27 Batch Read Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADCINT0 : Priority conversion interrupt request in the corresponding A/D unit 2
bits : 0 - -1 (0 bit)
access : read-only
ADCINT1 : Scan conversion interrupt request in the corresponding A/D unit 2
bits : 1 - 0 (0 bit)
access : read-only
ADCINT2 : FIFO overrun interrupt request in the corresponding A/D unit 2
bits : 2 - 1 (0 bit)
access : read-only
ADCINT3 : Conversion result comparison interrupt request in the corresponding A/D unit 2
bits : 3 - 2 (0 bit)
access : read-only
IRQ28 Batch Read Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FRT0INT0 : Peak value detection interrupt request on the free run timer ch.0 in the MFT unit 0
bits : 0 - -1 (0 bit)
access : read-only
FRT0INT1 : Peak value detection interrupt request on the free run timer ch.1 in the MFT unit 0
bits : 1 - 0 (0 bit)
access : read-only
FRT0INT2 : Peak value detection interrupt request on the free run timer ch.2 in the MFT unit 0
bits : 2 - 1 (0 bit)
access : read-only
FRT0INT3 : Zero detection interrupt request on the free run timer ch.0 in the MFT unit 0
bits : 3 - 2 (0 bit)
access : read-only
FRT0INT4 : Zero detection interrupt request on the free run timer ch.1 in the MFT unit 0
bits : 4 - 3 (0 bit)
access : read-only
FRT0INT5 : Zero detection interrupt request on the free run timer ch.2 in the MFT unit 0
bits : 5 - 4 (0 bit)
access : read-only
FRT1INT0 : Peak value detection interrupt request on the free run timer ch.0 in the MFT unit 1
bits : 6 - 5 (0 bit)
access : read-only
FRT1INT1 : Peak value detection interrupt request on the free run timer ch.1 in the MFT unit 1
bits : 7 - 6 (0 bit)
access : read-only
FRT1INT2 : Peak value detection interrupt request on the free run timer ch.2 in the MFT unit 1
bits : 8 - 7 (0 bit)
access : read-only
FRT1INT3 : Zero detection interrupt request on the free run timer ch.0 in the MFT unit 1
bits : 9 - 8 (0 bit)
access : read-only
FRT1INT4 : Zero detection interrupt request on the free run timer ch.1 in the MFT unit 1
bits : 10 - 9 (0 bit)
access : read-only
FRT1INT5 : Zero detection interrupt request on the free run timer ch.2 in the MFT unit 1
bits : 11 - 10 (0 bit)
access : read-only
FRT2INT0 : Peak value detection interrupt request on the free run timer ch.0 in the MFT unit 2
bits : 12 - 11 (0 bit)
access : read-only
FRT2INT1 : Peak value detection interrupt request on the free run timer ch.1 in the MFT unit 2
bits : 13 - 12 (0 bit)
access : read-only
FRT2INT2 : Peak value detection interrupt request on the free run timer ch.2 in the MFT unit 2
bits : 14 - 13 (0 bit)
access : read-only
FRT2INT3 : Zero detection interrupt request on the free run timer ch.0 in the MFT unit 2
bits : 15 - 14 (0 bit)
access : read-only
FRT2INT4 : Zero detection interrupt request on the free run timer ch.1 in the MFT unit 2
bits : 16 - 15 (0 bit)
access : read-only
FRT2INT5 : Zero detection interrupt request on the free run timer ch.2 in the MFT unit 2
bits : 17 - 16 (0 bit)
access : read-only
IRQ29 Batch Read Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ICU0INT0 : Interrupt request on the input capture ch.0 in the MFT unit 0
bits : 0 - -1 (0 bit)
access : read-only
ICU0INT1 : Interrupt request on the input capture ch.1 in the MFT unit 0
bits : 1 - 0 (0 bit)
access : read-only
ICU0INT2 : Interrupt request on the input capture ch.2 in the MFT unit 0
bits : 2 - 1 (0 bit)
access : read-only
ICU0INT3 : Interrupt request on the input capture ch.3 in the MFT unit 0
bits : 3 - 2 (0 bit)
access : read-only
ICU1INT0 : Interrupt request on the input capture ch.0 in the MFT unit 1
bits : 4 - 3 (0 bit)
access : read-only
ICU1INT1 : Interrupt request on the input capture ch.1 in the MFT unit 1
bits : 5 - 4 (0 bit)
access : read-only
ICU1INT2 : Interrupt request on the input capture ch.2 in the MFT unit 1
bits : 6 - 5 (0 bit)
access : read-only
ICU1INT3 : Interrupt request on the input capture ch.3 in the MFT unit 1
bits : 7 - 6 (0 bit)
access : read-only
ICU2INT0 : Interrupt request on the input capture ch.0 in the MFT unit 2
bits : 8 - 7 (0 bit)
access : read-only
ICU2INT1 : Interrupt request on the input capture ch.1 in the MFT unit 2
bits : 9 - 8 (0 bit)
access : read-only
ICU2INT2 : Interrupt request on the input capture ch.2 in the MFT unit 2
bits : 10 - 9 (0 bit)
access : read-only
ICU2INT3 : Interrupt request on the input capture ch.3 in the MFT unit 2
bits : 11 - 10 (0 bit)
access : read-only
IRQ30 Batch Read Register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
OCU0INT0 : Interrupt request on the output compare ch.0 in the MFT unit 0
bits : 0 - -1 (0 bit)
access : read-only
OCU0INT1 : Interrupt request on the output compare ch.1 in the MFT unit 0
bits : 1 - 0 (0 bit)
access : read-only
OCU0INT2 : Interrupt request on the output compare ch.2 in the MFT unit 0
bits : 2 - 1 (0 bit)
access : read-only
OCU0INT3 : Interrupt request on the output compare ch.3 in the MFT unit 0
bits : 3 - 2 (0 bit)
access : read-only
OCU0INT4 : Interrupt request on the output compare ch.4 in the MFT unit 0
bits : 4 - 3 (0 bit)
access : read-only
OCU0INT5 : Interrupt request on the output compare ch.5 in the MFT unit 0
bits : 5 - 4 (0 bit)
access : read-only
OCU1INT0 : Interrupt request on the output compare ch.0 in the MFT unit 1
bits : 6 - 5 (0 bit)
access : read-only
OCU1INT1 : Interrupt request on the output compare ch.1 in the MFT unit 1
bits : 7 - 6 (0 bit)
access : read-only
OCU1INT2 : Interrupt request on the output compare ch.2 in the MFT unit 1
bits : 8 - 7 (0 bit)
access : read-only
OCU1INT3 : Interrupt request on the output compare ch.3 in the MFT unit 1
bits : 9 - 8 (0 bit)
access : read-only
OCU1INT4 : Interrupt request on the output compare ch.4 in the MFT unit 1
bits : 10 - 9 (0 bit)
access : read-only
OCU1INT5 : Interrupt request on the output compare ch.5 in the MFT unit 1
bits : 11 - 10 (0 bit)
access : read-only
OCU2INT0 : Interrupt request on the output compare ch.0 in the MFT unit 2
bits : 12 - 11 (0 bit)
access : read-only
OCU2INT1 : Interrupt request on the output compare ch.1 in the MFT unit 2
bits : 13 - 12 (0 bit)
access : read-only
OCU2INT2 : Interrupt request on the output compare ch.2 in the MFT unit 2
bits : 14 - 13 (0 bit)
access : read-only
OCU2INT3 : Interrupt request on the output compare ch.3 in the MFT unit 2
bits : 15 - 14 (0 bit)
access : read-only
OCU2INT4 : Interrupt request on the output compare ch.4 in the MFT unit 2
bits : 16 - 15 (0 bit)
access : read-only
OCU2INT5 : Interrupt request on the output compare ch.5 in the MFT unit 2
bits : 17 - 16 (0 bit)
access : read-only
IRQ31 Batch Read Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BTINT0 : IRQ0 interrupt request on the base timer ch.0
bits : 0 - -1 (0 bit)
access : read-only
BTINT1 : IRQ1 interrupt request on the base timer ch.0
bits : 1 - 0 (0 bit)
access : read-only
BTINT2 : IRQ0 interrupt request on the base timer ch.1
bits : 2 - 1 (0 bit)
access : read-only
BTINT3 : IRQ1 interrupt request on the base timer ch.1
bits : 3 - 2 (0 bit)
access : read-only
BTINT4 : IRQ0 interrupt request on the base timer ch.2
bits : 4 - 3 (0 bit)
access : read-only
BTINT5 : IRQ1 interrupt request on the base timer ch.2
bits : 5 - 4 (0 bit)
access : read-only
BTINT6 : IRQ0 interrupt request on the base timer ch.3
bits : 6 - 5 (0 bit)
access : read-only
BTINT7 : IRQ1 interrupt request on the base timer ch.3
bits : 7 - 6 (0 bit)
access : read-only
BTINT8 : IRQ0 interrupt request on the base timer ch.4
bits : 8 - 7 (0 bit)
access : read-only
BTINT9 : IRQ1 interrupt request on the base timer ch.4
bits : 9 - 8 (0 bit)
access : read-only
BTINT10 : IRQ0 interrupt request on the base timer ch.5
bits : 10 - 9 (0 bit)
access : read-only
BTINT11 : IRQ1 interrupt request on the base timer ch.5
bits : 11 - 10 (0 bit)
access : read-only
BTINT12 : IRQ0 interrupt request on the base timer ch.6
bits : 12 - 11 (0 bit)
access : read-only
BTINT13 : IRQ1 interrupt request on the base timer ch.6
bits : 13 - 12 (0 bit)
access : read-only
BTINT14 : IRQ0 interrupt request on the base timer ch.7
bits : 14 - 13 (0 bit)
access : read-only
BTINT15 : IRQ1 interrupt request on the base timer ch.7
bits : 15 - 14 (0 bit)
access : read-only
IRQ32 Batch Read Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CAN0INT : Interrupt request of CAN ch.0
bits : 0 - -1 (0 bit)
access : read-only
IRQ33 Batch Read Register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CAN1INT : Interrupt request of CAN ch.1
bits : 0 - -1 (0 bit)
access : read-only
IRQ34 Batch Read Register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
USB0INT0 : Endpoint 1 DRQ interrupt request on the USB ch.0
bits : 0 - -1 (0 bit)
access : read-only
USB0INT1 : Endpoint 2 DRQ interrupt request on the USB ch.0
bits : 1 - 0 (0 bit)
access : read-only
USB0INT2 : Endpoint 3 DRQ interrupt request on the USB ch.0
bits : 2 - 1 (0 bit)
access : read-only
USB0INT3 : Endpoint 4 DRQ interrupt request on the USB ch.0
bits : 3 - 2 (0 bit)
access : read-only
USB0INT4 : Endpoint 5 DRQ interrupt request on the USB ch.0
bits : 4 - 3 (0 bit)
access : read-only
IRQ35 Batch Read Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
USB0INT0 : Endpoint 0 DRQI interrupt request on the USB ch.0
bits : 0 - -1 (0 bit)
access : read-only
USB0INT1 : Endpoint 0 DRQO interrupt request on the USB ch.0
bits : 1 - 0 (0 bit)
access : read-only
USB0INT2 : Status (SUSP, SOF, BRST, CONF, WKUP) interrupt request on the USB ch.0
bits : 2 - 1 (0 bit)
access : read-only
USB0INT3 : Status (SPK) interrupt request on the USB ch.0
bits : 3 - 2 (0 bit)
access : read-only
USB0INT4 : Status (DIRQ, URIRQ, RWKIRQ, CNNIRQ) interrupt request on the USB ch.0
bits : 4 - 3 (0 bit)
access : read-only
USB0INT5 : Status (SOFIRQ, CMPIRO) interrupt request on the USB ch.0
bits : 5 - 4 (0 bit)
access : read-only
IRQ38 Batch Read Register
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DMAINT : Interrupt request on DMA ch.0.
bits : 0 - -1 (0 bit)
access : read-only
USB ch.0 Odd Packet Size DMA Enable Register
address_offset : 0xB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ODDPKS0 : When the transfer destination address of DMAC is USB.EP1DT, the bit width of the last transfer data is converted to Byte.
bits : 0 - -1 (0 bit)
access : read-write
ODDPKS1 : When the transfer destination address of DMAC is USB.EP2DT, the bit width of the last transfer data is converted to Byte.
bits : 1 - 0 (0 bit)
access : read-write
ODDPKS2 : When the transfer destination address of DMAC is USB.EP3DT, the bit width of the last transfer data is converted to Byte.
bits : 2 - 1 (0 bit)
access : read-write
ODDPKS3 : When the transfer destination address of DMAC is USB.EP4DT, the bit width of the last transfer data is converted to Byte.
bits : 3 - 2 (0 bit)
access : read-write
ODDPKS4 : When the transfer destination address of DMAC is USB.EP5DT, the bit width of the last transfer data is converted to Byte.
bits : 4 - 3 (0 bit)
access : read-write
IRQ39 Batch Read Register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DMAINT : Interrupt request on DMA ch.1.
bits : 0 - -1 (0 bit)
access : read-only
IRQ40 Batch Read Register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DMAINT : Interrupt request on DMA ch.2.
bits : 0 - -1 (0 bit)
access : read-only
IRQ41 Batch Read Register
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DMAINT : Interrupt request on DMA ch.3.
bits : 0 - -1 (0 bit)
access : read-only
IRQ42 Batch Read Register
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DMAINT : Interrupt request on DMA ch.4.
bits : 0 - -1 (0 bit)
access : read-only
Interrupt Factor Vector Relocate Setting Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQCMODE : Interrupt Factor Vector Relocate Setting
bits : 0 - -1 (0 bit)
access : read-write
IRQ43 Batch Read Register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DMAINT : Interrupt request on DMA ch.5.
bits : 0 - -1 (0 bit)
access : read-only
IRQ44 Batch Read Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DMAINT : Interrupt request on DMA ch.6.
bits : 0 - -1 (0 bit)
access : read-only
IRQ45 Batch Read Register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DMAINT : Interrupt request on DMA ch.7.
bits : 0 - -1 (0 bit)
access : read-only
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