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EXTI

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x10 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x14 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x18 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xC Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x4 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x8 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

Registers

ENIR

ELVR1

NMIRR

NMICL

EIRR

EICL

ELVR


ENIR

Enable Interrupt Request Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ENIR ENIR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN0 EN1 EN2 EN3 EN6 EN7 EN14 EN15 EN16 EN17 EN18 EN19 EN20 EN21

EN0 : Bit0 of ENIR
bits : 0 - -1 (0 bit)
access : read-write

EN1 : Bit1 of ENIR
bits : 1 - 0 (0 bit)
access : read-write

EN2 : Bit2 of ENIR
bits : 2 - 1 (0 bit)
access : read-write

EN3 : Bit3 of ENIR
bits : 3 - 2 (0 bit)
access : read-write

EN6 : Bit6 of ENIR
bits : 6 - 5 (0 bit)
access : read-write

EN7 : Bit7 of ENIR
bits : 7 - 6 (0 bit)
access : read-write

EN14 : Bit14 of ENIR
bits : 14 - 13 (0 bit)
access : read-write

EN15 : Bit15 of ENIR
bits : 15 - 14 (0 bit)
access : read-write

EN16 : Bit16 of ENIR
bits : 16 - 15 (0 bit)
access : read-write

EN17 : Bit17 of ENIR
bits : 17 - 16 (0 bit)
access : read-write

EN18 : Bit18 of ENIR
bits : 18 - 17 (0 bit)
access : read-write

EN19 : Bit19 of ENIR
bits : 19 - 18 (0 bit)
access : read-write

EN20 : Bit20 of ENIR
bits : 20 - 19 (0 bit)
access : read-write

EN21 : Bit21 of ENIR
bits : 21 - 20 (0 bit)
access : read-write


ELVR1

External Interrupt Level Register 1
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ELVR1 ELVR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LA16 LB16 LA17 LB17 LA18 LB18 LA19 LB19 LA20 LB20 LA21 LB21

LA16 : Bit0 of ELVR1
bits : 0 - -1 (0 bit)
access : read-write

LB16 : Bit1 of ELVR1
bits : 1 - 0 (0 bit)
access : read-write

LA17 : Bit2 of ELVR1
bits : 2 - 1 (0 bit)
access : read-write

LB17 : Bit3 of ELVR1
bits : 3 - 2 (0 bit)
access : read-write

LA18 : Bit4 of ELVR1
bits : 4 - 3 (0 bit)
access : read-write

LB18 : Bit5 of ELVR1
bits : 5 - 4 (0 bit)
access : read-write

LA19 : Bit6 of ELVR1
bits : 6 - 5 (0 bit)
access : read-write

LB19 : Bit7 of ELVR1
bits : 7 - 6 (0 bit)
access : read-write

LA20 : Bit8 of ELVR1
bits : 8 - 7 (0 bit)
access : read-write

LB20 : Bit9 of ELVR1
bits : 9 - 8 (0 bit)
access : read-write

LA21 : Bit10 of ELVR1
bits : 10 - 9 (0 bit)
access : read-write

LB21 : Bit11 of ELVR1
bits : 11 - 10 (0 bit)
access : read-write


NMIRR

Non Maskable Interrupt Request Register
address_offset : 0x14 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

NMIRR NMIRR read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 NR

NR : NMI interrupt request detection bit
bits : 0 - -1 (0 bit)
access : read-only


NMICL

Non Maskable Interrupt Clear Register
address_offset : 0x18 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NMICL NMICL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 NCL

NCL : NMI interrupt cause clear bit
bits : 0 - -1 (0 bit)
access : read-write


EIRR

External Interrupt Request Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EIRR EIRR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ER0 ER1 ER2 ER3 ER6 ER7 ER14 ER15 ER16 ER17 ER18 ER19 ER20 ER21

ER0 : Bit0 of EIRR
bits : 0 - -1 (0 bit)
access : read-only

ER1 : Bit1 of EIRR
bits : 1 - 0 (0 bit)
access : read-only

ER2 : Bit2 of EIRR
bits : 2 - 1 (0 bit)
access : read-only

ER3 : Bit3 of EIRR
bits : 3 - 2 (0 bit)
access : read-only

ER6 : Bit6 of EIRR
bits : 6 - 5 (0 bit)
access : read-only

ER7 : Bit7 of EIRR
bits : 7 - 6 (0 bit)
access : read-only

ER14 : Bit14 of EIRR
bits : 14 - 13 (0 bit)
access : read-only

ER15 : Bit15 of EIRR
bits : 15 - 14 (0 bit)
access : read-only

ER16 : Bit16 of EIRR
bits : 16 - 15 (0 bit)
access : read-write

ER17 : Bit17 of EIRR
bits : 17 - 16 (0 bit)
access : read-write

ER18 : Bit18 of EIRR
bits : 18 - 17 (0 bit)
access : read-write

ER19 : Bit19 of EIRR
bits : 19 - 18 (0 bit)
access : read-write

ER20 : Bit20 of EIRR
bits : 20 - 19 (0 bit)
access : read-write

ER21 : Bit21 of EIRR
bits : 21 - 20 (0 bit)
access : read-write


EICL

External Interrupt Clear Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EICL EICL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ECL0 ECL1 ECL2 ECL3 ECL6 ECL7 ECL14 ECL15 ECL16 ECL17 ECL18 ECL19 ECL20 ECL21

ECL0 : Bit0 of EICL
bits : 0 - -1 (0 bit)
access : read-write

ECL1 : Bit1 of EICL
bits : 1 - 0 (0 bit)
access : read-write

ECL2 : Bit2 of EICL
bits : 2 - 1 (0 bit)
access : read-write

ECL3 : Bit3 of EICL
bits : 3 - 2 (0 bit)
access : read-write

ECL6 : Bit6 of EICL
bits : 6 - 5 (0 bit)
access : read-write

ECL7 : Bit7 of EICL
bits : 7 - 6 (0 bit)
access : read-write

ECL14 : Bit14 of EICL
bits : 14 - 13 (0 bit)
access : read-write

ECL15 : Bit15 of EICL
bits : 15 - 14 (0 bit)
access : read-write

ECL16 : Bit16 of EICL
bits : 16 - 15 (0 bit)
access : read-write

ECL17 : Bit17 of EICL
bits : 17 - 16 (0 bit)
access : read-write

ECL18 : Bit18 of EICL
bits : 18 - 17 (0 bit)
access : read-write

ECL19 : Bit19 of EICL
bits : 19 - 18 (0 bit)
access : read-write

ECL20 : Bit20 of EICL
bits : 20 - 19 (0 bit)
access : read-write

ECL21 : Bit21 of EICL
bits : 21 - 20 (0 bit)
access : read-write


ELVR

External Interrupt Level Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ELVR ELVR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LA0 LB0 LA1 LB1 LA2 LB2 LA3 LB3 LA6 LB6 LA7 LB7 LA14 LB14 LA15 LB15

LA0 : Bit0 of ELVR
bits : 0 - -1 (0 bit)
access : read-write

LB0 : Bit1 of ELVR
bits : 1 - 0 (0 bit)
access : read-write

LA1 : Bit2 of ELVR
bits : 2 - 1 (0 bit)
access : read-write

LB1 : Bit3 of ELVR
bits : 3 - 2 (0 bit)
access : read-write

LA2 : Bit4 of ELVR
bits : 4 - 3 (0 bit)
access : read-write

LB2 : Bit5 of ELVR
bits : 5 - 4 (0 bit)
access : read-write

LA3 : Bit6 of ELVR
bits : 6 - 5 (0 bit)
access : read-write

LB3 : Bit7 of ELVR
bits : 7 - 6 (0 bit)
access : read-write

LA6 : Bit12 of ELVR
bits : 12 - 11 (0 bit)
access : read-write

LB6 : Bit13 of ELVR
bits : 13 - 12 (0 bit)
access : read-write

LA7 : Bit14 of ELVR
bits : 14 - 13 (0 bit)
access : read-write

LB7 : Bit15 of ELVR
bits : 15 - 14 (0 bit)
access : read-write

LA14 : Bit28 of ELVR
bits : 28 - 27 (0 bit)
access : read-write

LB14 : Bit29 of ELVR
bits : 29 - 28 (0 bit)
access : read-write

LA15 : Bit30 of ELVR
bits : 30 - 29 (0 bit)
access : read-write

LB15 : Bit31 of ELVR
bits : 31 - 30 (0 bit)
access : read-write



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