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FLASH_IF

Peripheral Memory Blocks

address_offset : 0x100 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x4 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x10 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x20 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x28 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x8 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x24 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

Registers

FSYNDN

CRTRMM

FICR

FISR

FICLR

FRWTR

FSTR


FSYNDN

Flash Sync Down Register
address_offset : 0x10 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FSYNDN FSYNDN read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SD

SD : Sync Down
bits : 0 - 2 (3 bit)
access : read-write


CRTRMM

CR Trimming Data Mirror Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CRTRMM CRTRMM read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRMM TTRMM

TRMM : CR Trimming Data Mirror Bit
bits : 0 - 8 (9 bit)
access : read-only

TTRMM : CR Temperature Trimming Data Mirror Bit
bits : 16 - 19 (4 bit)
access : read-only


FICR

Flash Interrupt Control Register
address_offset : 0x20 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FICR FICR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RDYIE HANGIE

RDYIE : RDY Interrupt Enable
bits : 0 - -1 (0 bit)
access : read-write

HANGIE : HANG Interrupt Enable
bits : 1 - 0 (0 bit)
access : read-write


FISR

Flash Interrupt Status Register
address_offset : 0x24 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FISR FISR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RDYIF HANGIF

RDYIF : RDY Interrupt Flag
bits : 0 - -1 (0 bit)
access : read-write

HANGIF : HANG Interrupt Flag
bits : 1 - 0 (0 bit)
access : read-write


FICLR

Flash Interrupt Clear Register
address_offset : 0x28 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

FICLR FICLR write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RDYIC HANGIC

RDYIC : RDY Interrupt Clear
bits : 0 - -1 (0 bit)
access : write-only

HANGIC : HANG Interrupt Clear
bits : 1 - 0 (0 bit)
access : write-only


FRWTR

Flash Read Wait Register
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FRWTR FRWTR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RWT

RWT : Read Wait Cycle
bits : 0 - 0 (1 bit)
access : read-write


FSTR

Flash Status Register
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FSTR FSTR read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RDY HNG CERS ESPS SERS PGMS

RDY : Flash Ready Status
bits : 0 - -1 (0 bit)
access : read-only

HNG : Flash Hang Status
bits : 1 - 0 (0 bit)
access : read-only

CERS : Flash Chip Erase Status
bits : 2 - 1 (0 bit)
access : read-only

ESPS : Flash Erase Suspend Status
bits : 3 - 2 (0 bit)
access : read-only

SERS : Flash Sector Erase Status
bits : 4 - 3 (0 bit)
access : read-only

PGMS : Flash Program Status
bits : 5 - 4 (0 bit)
access : read-only



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