\n
address_offset : 0x0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x10 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x4 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x8 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xC00 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xC Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
Hardware Watchdog Timer Load Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Hardware Watchdog Timer Interrupt Status Register
address_offset : 0x10 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RIS : Hardware watchdog interrupt status bit
bits : 0 - -1 (0 bit)
access : read-only
Hardware Watchdog Timer Value Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Hardware Watchdog Timer Control Register
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTEN : Hardware watchdog interrupt and counter enable bit
bits : 0 - -1 (0 bit)
access : read-write
RESEN : Hardware watchdog reset enable bit
bits : 1 - 0 (0 bit)
access : read-write
Hardware Watchdog Timer Clear Register
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Hardware Watchdog Timer Lock Register
address_offset : 0xC00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
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