\n
address_offset : 0x102 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x106 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x10A Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x10E Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x112 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x116 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x118 Bytes (0x0)
size : 0x3 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x11C Bytes (0x0)
size : 0x3 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x120 Bytes (0x0)
size : 0x3 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x125 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x128 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x12C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x130 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x134 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x138 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x13C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x142 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x146 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x148 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x14E Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x152 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x154 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x15A Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x15E Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x160 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x164 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x168 Bytes (0x0)
size : 0x3 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x16C Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x170 Bytes (0x0)
size : 0x3 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x176 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x17A Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x17E Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x182 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x184 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x188 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x18E Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x190 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x196 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x198 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x19E Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x1A0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x1A4 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x1A8 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x1AC Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x1B0 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x1B4 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x1BA Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x1BE Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x1C2 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x1C6 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x1CA Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x1CE Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x1D0 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x1D4 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x1D8 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x1DC Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x1E0 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x1E4 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x1E8 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
OCU ch.0 Compare Value Store Register
address_offset : 0x102 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OCU ch.1 Compare Value Store Register
address_offset : 0x106 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OCU ch.2 Compare Value Store Register
address_offset : 0x10A Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OCU ch.3 Compare Value Store Register
address_offset : 0x10E Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OCU ch.4 Compare Value Store Register
address_offset : 0x112 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OCU ch.5 Compare Value Store Register
address_offset : 0x116 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OCU ch.1@0 Control Register A
address_offset : 0x118 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CST0 : Enables the operation of OCU ch.(0)
bits : 0 - -1 (0 bit)
access : read-write
CST1 : Enables the operation of OCU ch.(1)
bits : 1 - 0 (0 bit)
access : read-write
IOE0 : Generates interrupt@ when 1 is set to OCSA.IOP0
bits : 4 - 3 (0 bit)
access : read-write
IOE1 : Generates interrupt@ when 1 is set to OCSA.IOP1
bits : 5 - 4 (0 bit)
access : read-write
IOP0 : Indicates that a match has already been detected between FRT's count value and OCCP(0) value at OCU ch.(0).
bits : 6 - 5 (0 bit)
access : read-write
IOP1 : Indicates that a match has already been detected between FRT's count value and OCCP(1) value at OCU ch.(1).
bits : 7 - 6 (0 bit)
access : read-write
OCU ch.1@0 Control Register B
address_offset : 0x119 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OTD0 : Indicates that the RT(0) output pin is in the High-level output state.
bits : 0 - -1 (0 bit)
access : read-write
OTD1 : Indicates that the RT(1) output pin is in the High-level output state.
bits : 1 - 0 (0 bit)
access : read-write
CMOD : Selects OCU's operation mode in combination with OCSC.MOD0 to MOD5
bits : 4 - 3 (0 bit)
access : read-write
FM4 : Selects the OCU's operating mode
bits : 7 - 6 (0 bit)
access : read-write
OCU ch.1@0 Control Register D
address_offset : 0x11A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OCCP0BUFE : Enable or disable the buffer register function of OCCP(0)
bits : 0 - 0 (1 bit)
access : read-write
OCCP1BUFE : Enable or disable the buffer register function of OCCP(1)
bits : 2 - 2 (1 bit)
access : read-write
OCSE0BUFE : Enable or disable the buffer register function of OCSE(0)
bits : 4 - 4 (1 bit)
access : read-write
OCSE1BUFE : Enable or disable the buffer register function of OCSE(1)
bits : 6 - 6 (1 bit)
access : read-write
OCU ch.3@2 Control Register A
address_offset : 0x11C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OCU ch.3@2 Control Register B
address_offset : 0x11D Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OCU ch.1@0 Control Register D
address_offset : 0x11E Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OCU ch.5@4 Control Register A
address_offset : 0x120 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OCU ch.5@4 Control Register B
address_offset : 0x121 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OCU ch.5@4 Control Register D
address_offset : 0x122 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OCU Control Register C
address_offset : 0x125 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MOD0 : OCSC.MOD0 and OCSC.MOD1 determine the operation mode of OCU ch.0,h.1 in combination with OCSB10.CMOD
bits : 0 - -1 (0 bit)
access : read-write
MOD1 : OCSC.MOD0 and OCSC.MOD1 determine the operation mode of OCU ch.0,h.1 in combination with OCSB10.CMOD
bits : 1 - 0 (0 bit)
access : read-write
MOD2 : OCSC.MOD2 and OCSC.MOD3 determine the operation mode of OCU ch.2,h.3 in combination with OCSB32.CMOD
bits : 2 - 1 (0 bit)
access : read-write
MOD3 : OCSC.MOD2 and OCSC.MOD3 determine the operation mode of OCU ch.2,h.3 in combination with OCSB32.CMOD
bits : 3 - 2 (0 bit)
access : read-write
MOD4 : OCSC.MOD4 and OCSC.MOD5 determine the operation mode of OCU ch.4,h.5 in combination with OCSB54.CMOD
bits : 4 - 3 (0 bit)
access : read-write
MOD5 : OCSC.MOD4 and OCSC.MOD5 determine the operation mode of OCU ch.4,h.5 in combination with OCSB54.CMOD
bits : 5 - 4 (0 bit)
access : read-write
OCU ch.0 Control Register E
address_offset : 0x128 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OCSE : Specify the setting conditions of the OCU's matching detection register and the change conditions for output signals
bits : 0 - 14 (15 bit)
access : read-write
OCU ch.1 Control Register E
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OCSE : Specify the setting conditions of the OCU's matching detection register and the change conditions for output signals
bits : 0 - 30 (31 bit)
access : read-write
OCU ch.2 Control Register E
address_offset : 0x130 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OCU ch.3 Control Register E
address_offset : 0x134 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OCU ch.4 Control Register E
address_offset : 0x138 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OCU ch.5 Control Register E
address_offset : 0x13C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRT-ch.0 Cycle Setting Register
address_offset : 0x142 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRT-ch.0 Count Value Register
address_offset : 0x146 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRT-ch.0 Control Register A
address_offset : 0x148 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLK : FRT clock cycle
bits : 0 - 2 (3 bit)
access : read-write
SCLR : FRT operation state initialization request
bits : 4 - 3 (0 bit)
access : write-only
MODE : FRT's count mode
bits : 5 - 4 (0 bit)
access : read-write
STOP : Puts FRT in stopping state
bits : 6 - 5 (0 bit)
access : read-write
BFE : Enables TCCP's buffer function
bits : 7 - 6 (0 bit)
access : read-write
ICRE : Generates interrupt when 1 is set to TCSA.ICLR
bits : 8 - 7 (0 bit)
access : read-write
ICLR : Interrupt flag
bits : 9 - 8 (0 bit)
access : read-write
IRQZE : Generates interrupt@ when 1 is set to TCSA.IRQZF
bits : 13 - 12 (0 bit)
access : read-write
IRQZF : Zero interrupt flag
bits : 14 - 13 (0 bit)
access : read-write
ECKE : Uses an external input clock (FRCK) as FRT's count clock
bits : 15 - 14 (0 bit)
access : read-write
FRT-ch.0 Control Register C
address_offset : 0x14A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MSZI : Reads the current counter value from a Peak value detection mask counter
bits : 0 - 2 (3 bit)
access : read-write
MSPI : Reads the current counter value from a Zero value detection mask counter
bits : 4 - 6 (3 bit)
access : read-write
MSZC : Sets the number of masked Peak value detections
bits : 8 - 10 (3 bit)
access : read-only
MSPC : Sets the number of masked Zero value detections
bits : 12 - 14 (3 bit)
access : read-only
FRT-ch.1 Cycle Setting Register
address_offset : 0x14E Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRT-ch.1 Count Value Register
address_offset : 0x152 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRT-ch.1 Control Register A
address_offset : 0x154 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRT-ch.1 Control Register C
address_offset : 0x156 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRT-ch.2 Cycle Setting Register
address_offset : 0x15A Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRT-ch.2 Count Value Register
address_offset : 0x15E Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRT-ch.2 Control Register A
address_offset : 0x160 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRT-ch.2 Control Register C
address_offset : 0x162 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRT Simultaneous Start Control Register
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STOP00 : Processes simultaneous writes/reads to relevant TCSA.STOP bit 00
bits : 0 - -1 (0 bit)
access : read-write
STOP01 : Processes simultaneous writes/reads to relevant TCSA.STOP bit 01
bits : 1 - 0 (0 bit)
access : read-write
STOP02 : Processes simultaneous writes/reads to relevant TCSA.STOP bit 02
bits : 2 - 1 (0 bit)
access : read-write
STOP10 : Processes simultaneous writes/reads to relevant TCSA.STOP bit 10
bits : 3 - 2 (0 bit)
access : read-write
STOP11 : Processes simultaneous writes/reads to relevant TCSA.STOP bit 11
bits : 4 - 3 (0 bit)
access : read-write
STOP12 : Processes simultaneous writes/reads to relevant TCSA.STOP bit 12
bits : 5 - 4 (0 bit)
access : read-write
STOP20 : Processes simultaneous writes/reads to relevant TCSA.STOP bit 20
bits : 6 - 5 (0 bit)
access : read-write
STOP21 : Processes simultaneous writes/reads to relevant TCSA.STOP bit 21
bits : 7 - 6 (0 bit)
access : read-write
STOP22 : Processes simultaneous writes/reads to relevant TCSA.STOP bit 22
bits : 8 - 7 (0 bit)
access : read-write
SCLR00 : Processes simultaneous writes to relevant TCSA.SCLR register 00
bits : 16 - 15 (0 bit)
access : write-only
SCLR01 : Processes simultaneous writes to relevant TCSA.SCLR register 01
bits : 17 - 16 (0 bit)
access : write-only
SCLR02 : Processes simultaneous writes to relevant TCSA.SCLR register 02
bits : 18 - 17 (0 bit)
access : write-only
SCLR10 : Processes simultaneous writes to relevant TCSA.SCLR register 10
bits : 19 - 18 (0 bit)
access : write-only
SCLR11 : Processes simultaneous writes to relevant TCSA.SCLR register 11
bits : 20 - 19 (0 bit)
access : write-only
SCLR12 : Processes simultaneous writes to relevant TCSA.SCLR register 12
bits : 21 - 20 (0 bit)
access : write-only
SCLR20 : Processes simultaneous writes to relevant TCSA.SCLR register 20
bits : 22 - 21 (0 bit)
access : write-only
SCLR21 : Processes simultaneous writes to relevant TCSA.SCLR register 21
bits : 23 - 22 (0 bit)
access : write-only
SCLR22 : Processes simultaneous writes to relevant TCSA.SCLR register 22
bits : 24 - 23 (0 bit)
access : write-only
OCU ch.1@0 Connecting FRT Select Register
address_offset : 0x168 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FSO0 : Connects FRT ch.x to OCU ch.0
bits : 0 - 2 (3 bit)
access : read-write
FSO1 : Connects FRT ch.x to OCU ch.1
bits : 4 - 6 (3 bit)
access : read-write
OCU ch.3@2 Connecting FRT Select Register
address_offset : 0x169 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OCU ch.5@4 Connecting FRT Select Register
address_offset : 0x16A Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU ch.1@0 Connecting FRT Select Register
address_offset : 0x16C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FSI0 : Connects FRT ch.x to ICU ch.(0)
bits : 0 - 2 (3 bit)
access : read-write
FSI1 : Connects FRT ch.x to ICU ch.(1)
bits : 4 - 6 (3 bit)
access : read-write
ICU ch.3@2 Connecting FRT Select Register
address_offset : 0x16D Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCMP Ch1@0 Connecting FRT Select Register
address_offset : 0x170 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FSA0 : Specify the FRT ch.x to be connected to ADCMP ch.(0)
bits : 0 - 2 (3 bit)
access : read-write
FSA1 : Specify the FRT ch.x to be connected to ADCMP ch.(1)
bits : 4 - 6 (3 bit)
access : read-write
ADCMP Ch3@2 Connecting FRT Select Register
address_offset : 0x171 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCMP Ch5@4 Connecting FRT Select Register
address_offset : 0x172 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU ch.0 Capture value store register
address_offset : 0x176 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ICU ch.1 Capture value store register
address_offset : 0x17A Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU ch.2 Capture value store register
address_offset : 0x17E Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU ch.3 Capture value store register
address_offset : 0x182 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU ch.1@0 Control Register A
address_offset : 0x184 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EG0 : Enables/disables the operation of ICU-ch.(0) and selects a valid edge(s)
bits : 0 - 0 (1 bit)
access : read-write
EG1 : Enables/disables the operation of ICU-ch.(1) and selects a valid edge(s)
bits : 2 - 2 (1 bit)
access : read-write
ICE0 : Generates interrupt@ when 1 is set to ICSA.ICP0.
bits : 4 - 3 (0 bit)
access : read-write
ICE1 : Generates interrupt@ when 1 is set to ICSA.ICP1.
bits : 5 - 4 (0 bit)
access : read-write
ICP0 : Indicates that a valid edge has been detected at ICU ch.(0) and the capture operation has been performed
bits : 6 - 5 (0 bit)
access : read-write
ICP1 : Indicates that a valid edge has been detected at ICU ch.(1) and the capture operation has been performed
bits : 7 - 6 (0 bit)
access : read-write
ICU ch.1@0 Control Register B
address_offset : 0x185 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IEI0 : Indicates the latest valid edge of ICU-ch.(0)
bits : 0 - -1 (0 bit)
access : read-only
IEI1 : Indicates the latest valid edge of ICU-ch.(1)
bits : 1 - 0 (0 bit)
access : read-only
ICU ch.3@2 Control Register A
address_offset : 0x188 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU ch.3@2 Control Register B
address_offset : 0x189 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WFG ch1@0 Pulse Counter Value Register
address_offset : 0x18E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WFG ch.1@0 Timer Value Register A
address_offset : 0x190 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WFG ch.1@0 Timer Value Register B
address_offset : 0x192 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WFG ch3@2 Pulse Counter Value Register
address_offset : 0x196 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WFG ch.3@2 Timer Value Register A
address_offset : 0x198 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WFG ch.3@2 Timer Value Register B
address_offset : 0x19A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WFG ch.5@4 Timer Value Register A
address_offset : 0x19E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WFG ch.5@4 Timer Value Register A
address_offset : 0x1A0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WFG ch.5@4 Timer Value Register B
address_offset : 0x1A2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WFG ch.10 Control Register A
address_offset : 0x1A4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCK : Clock cycle of the WFG timer
bits : 0 - 1 (2 bit)
access : read-write
TMD : WFG's operation mode
bits : 3 - 4 (2 bit)
access : read-write
GTEN : The CH_GATE signal for each channel of WFG
bits : 6 - 6 (1 bit)
access : read-write
PSEL : The PPG timer unit to be used at each channel of WFG
bits : 8 - 8 (1 bit)
access : read-write
PGEN : Specifies how to reflect the CH_PPG signal that is input to each channel of WFG on WFG output
bits : 10 - 10 (1 bit)
access : read-write
DMOD : Specifies which polarity will be used to output the non-overlap signal
bits : 12 - 12 (1 bit)
access : read-write
WFG ch.32 Control Register A
address_offset : 0x1A8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WFG ch.54 Control Register A
address_offset : 0x1AC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WFG Interrupt Control Register
address_offset : 0x1B0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTIFA : Detects the event of DTTIX signal input via digital noise-canceller
bits : 0 - -1 (0 bit)
access : read-only
DTICA : Clears the DTIFA interrupt flag
bits : 1 - 0 (0 bit)
access : write-only
DTIFB : Detects DTTIX signal input via analog noise filter
bits : 2 - 1 (0 bit)
access : read-only
DTICB : Clears DTIFB bit
bits : 3 - 2 (0 bit)
access : write-only
TMIF10 : Indicates that WFG10 timer interrupt has been generated.
bits : 4 - 3 (0 bit)
access : read-only
TMIC10 : Clears WFIR.TMIF10 and deasserts the WFG10 timer interrupt signal.
bits : 5 - 4 (0 bit)
access : write-only
TMIE10 : Starts the WFG10 timer
bits : 6 - 5 (0 bit)
access : read-write
TMIS10 : Stops the WFG10 timer
bits : 7 - 6 (0 bit)
access : write-only
TMIF32 : Indicates that WFG32 timer interrupt has been generated.
bits : 8 - 7 (0 bit)
access : read-only
TMIC32 : Clears WFIR.TMIF32 and deasserts the WFG32 timer interrupt signal.
bits : 9 - 8 (0 bit)
access : write-only
TMIE32 : Starts the WFG32 timer
bits : 10 - 9 (0 bit)
access : read-write
TMIS32 : Stops the WFG32 timer
bits : 11 - 10 (0 bit)
access : write-only
TMIF54 : Indicates that WFG54 timer interrupt has been generated.
bits : 12 - 11 (0 bit)
access : read-only
TMIC54 : Clears WFIR.TMIF54 and deasserts the WFG54 timer interrupt signal.
bits : 13 - 12 (0 bit)
access : write-only
TMIE54 : Starts the WFG54 timer
bits : 14 - 13 (0 bit)
access : read-write
TMIS54 : Stops the WFG54 timer
bits : 15 - 14 (0 bit)
access : write-only
NZCL Control Register
address_offset : 0x1B4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTIEA : Selects whether the WFIR.DTIFA register is set for the path via digital noise filter from the DTTIX input pin
bits : 0 - -1 (0 bit)
access : read-write
NWS : Noise-canceling width of the noise-canceller for the DTTIX pin
bits : 1 - 2 (2 bit)
access : read-write
SDTI : Forcibly generates DTIF interrupt
bits : 4 - 3 (0 bit)
access : write-only
DTIEB : Selects whether to set the WFIR.DTIFB flag for the path from the DTTIX pin for input signal to an analog noise filter
bits : 5 - 4 (0 bit)
access : read-write
DIMA : Selects whether a DTIF interrupt is masked when the WFIR.DTIFA flag is set
bits : 8 - 7 (0 bit)
access : read-write
DIMB : Selects whether a DTIF interrupt is masked when the WFIR.TIFDTIFB flag is set
bits : 9 - 8 (0 bit)
access : read-write
WIM10 : Selects whether a WFG10 reload timer interrupt is masked when the WFIR.TMIF10 flag is set
bits : 12 - 11 (0 bit)
access : read-write
WIM32 : Selects whether a WFG32 reload timer interrupt is masked when the WFIR.TMIF32 flag is set
bits : 13 - 12 (0 bit)
access : read-write
WIM54 : Selects whether a WFG54 reload timer interrupt is masked when the WFIR.TMIF54 flag is set
bits : 14 - 13 (0 bit)
access : read-write
ADCMP Ch.0 Compare Value Store Register
address_offset : 0x1BA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACMP : Specify an AD conversion start time
bits : 0 - 14 (15 bit)
access : read-write
ADCMP Ch.1 Compare Value Store Register
address_offset : 0x1BE Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCMP Ch.2 Compare Value Store Register
address_offset : 0x1C2 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCMP Ch.3 Compare Value Store Register
address_offset : 0x1C6 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCMP Ch.4 Compare Value Store Register
address_offset : 0x1CA Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCMP Ch.5 Compare Value Store Register
address_offset : 0x1CE Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCMP Control Register A
address_offset : 0x1D0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CE10 : Enables/disables compatibility of ADCMP ch.1 and ch.0 with FM3 Family products
bits : 0 - 0 (1 bit)
access : read-write
CE32 : Enables/disables compatibility of ADCMP ch.3 and ch.2 with FM3 Family products
bits : 2 - 2 (1 bit)
access : read-write
CE54 : Enables/disables compatibility of ADCMP ch.5 and ch.4 with FM3 Family products
bits : 4 - 4 (1 bit)
access : read-write
SEL10 : Selects compatible operation of ADCMP ch.1 and ch.0 with FM3 Family products
bits : 8 - 8 (1 bit)
access : read-write
SEL32 : Selects compatible operation of ADCMP ch.3 and ch.2 with FM3 Family products
bits : 10 - 10 (1 bit)
access : read-write
SEL54 : Selects compatible operation of ADCMP ch.5 and ch.4 with FM3 Family products
bits : 12 - 12 (1 bit)
access : read-write
ADCMP Ch.0 Control Register C
address_offset : 0x1D4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUFE : Select enable/disable and transfer timing for buffer function of the ACMP register
bits : 0 - 0 (1 bit)
access : read-write
ADSEL : Specify the destinations of ADC start signals that are output by ADCMP
bits : 2 - 3 (2 bit)
access : read-write
ADCMP Ch.0 Control Register D
address_offset : 0x1D5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AMOD : Selects operation mode for ADCMP
bits : 0 - -1 (0 bit)
access : read-write
OCUS : Selects the OCU OCCP register that will become the start for offset start
bits : 1 - 0 (0 bit)
access : read-write
DE : Enables/disables the operation of the ADCMP that is counting down for the connected FRT
bits : 4 - 3 (0 bit)
access : read-write
PE : Enables/disables the operation of the ADCMP that is counting down at the Peak value of the connected FRT
bits : 5 - 4 (0 bit)
access : read-write
UE : Nables/disables the operation of the ADCMP that is counting up for the connected FRT
bits : 6 - 5 (0 bit)
access : read-write
ZE : Enables/disables the operation of the ADCMP when the FRT is 0x0000
bits : 7 - 6 (0 bit)
access : read-write
ADCMP Ch.1 Control Register C
address_offset : 0x1D8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCMP Ch.1 Control Register D
address_offset : 0x1D9 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCMP Ch.2 Control Register C
address_offset : 0x1DC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCMP Ch.2 Control Register D
address_offset : 0x1DD Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCMP Ch.3 Control Register C
address_offset : 0x1E0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCMP Ch.3 Control Register D
address_offset : 0x1E1 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCMP Ch.4 Control Register C
address_offset : 0x1E4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCMP Ch.4 Control Register D
address_offset : 0x1E5 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCMP Ch.5 Control Register C
address_offset : 0x1E8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCMP Ch.5 Control Register D
address_offset : 0x1E9 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
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