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ADC0

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x20 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x34 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x4C Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xC Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x8 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x10 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x14 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x18 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x28 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x2C Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x30 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x38 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x3C Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x1C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x24 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x26 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x50 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x44 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x48 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

Registers

ADSR

ADCR

SCIS2

SCIS3

SCIS0

SCIS1

PFNS

PCCR

PCFD

PCIS

CMPCR

CMPD

ADSS2

ADSS3

ADSS0

ADSS1

ADST1

ADST0

ADCT

PRTSL

SCTSL

ADCEN

WCMRCIF

WCMRCOT

WCMPCR

WCMPSR

WCMPDL

WCMPDH

SFNS

SCCR

SCFD


ADSR

A/D Status Register
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADSR ADSR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SCS PCS PCNS FDAS ADSTP

SCS : Scan conversion status flag
bits : 0 - -1 (0 bit)
access : read-only

PCS : Priority conversion status flag
bits : 1 - 0 (0 bit)
access : read-only

PCNS : Priority conversion pending flag
bits : 2 - 1 (0 bit)
access : read-only

FDAS : FIFO data placement selection bit
bits : 6 - 5 (0 bit)
access : read-write

ADSTP : A/D conversion forced stop bit
bits : 7 - 6 (0 bit)
access : read-write


ADCR

A/D Control Register
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADCR ADCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVRIE CMPIE PCIE SCIE CMPIF PCIF SCIF

OVRIE : FIFO overrun interrupt enable bit
bits : 0 - -1 (0 bit)
access : read-write

CMPIE : Conversion result comparison interrupt enable bit
bits : 1 - 0 (0 bit)
access : read-write

PCIE : Priority conversion interrupt enable bit
bits : 2 - 1 (0 bit)
access : read-write

SCIE : Scan conversion interrupt enable bit
bits : 3 - 2 (0 bit)
access : read-write

CMPIF : Conversion result comparison interrupt request bit
bits : 5 - 4 (0 bit)
access : read-write

PCIF : Priority conversion interrupt request bit
bits : 6 - 5 (0 bit)
access : read-write

SCIF : Scan conversion interrupt request bit
bits : 7 - 6 (0 bit)
access : read-write


SCIS2

Scan Conversion Input Selection Register 2
address_offset : 0x10 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCIS2 SCIS2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 AN16 AN17 AN18 AN19 AN20 AN21 AN22 AN23

AN16 : AN16 analog input selection bit
bits : 0 - -1 (0 bit)
access : read-write

AN17 : AN17 analog input selection bit
bits : 1 - 0 (0 bit)
access : read-write

AN18 : AN18 analog input selection bit
bits : 2 - 1 (0 bit)
access : read-write

AN19 : AN19 analog input selection bit
bits : 3 - 2 (0 bit)
access : read-write

AN20 : AN20 analog input selection bit
bits : 4 - 3 (0 bit)
access : read-write

AN21 : AN21 analog input selection bit
bits : 5 - 4 (0 bit)
access : read-write

AN22 : AN22 analog input selection bit
bits : 6 - 5 (0 bit)
access : read-write

AN23 : AN23 analog input selection bit
bits : 7 - 6 (0 bit)
access : read-write


SCIS3

Scan Conversion Input Selection Register 3
address_offset : 0x11 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCIS3 SCIS3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 AN24 AN25 AN26 AN27 AN28 AN29 AN30 AN31

AN24 : AN24 analog input selection bit
bits : 0 - -1 (0 bit)
access : read-write

AN25 : AN25 analog input selection bit
bits : 1 - 0 (0 bit)
access : read-write

AN26 : AN26 analog input selection bit
bits : 2 - 1 (0 bit)
access : read-write

AN27 : AN27 analog input selection bit
bits : 3 - 2 (0 bit)
access : read-write

AN28 : AN28 analog input selection bit
bits : 4 - 3 (0 bit)
access : read-write

AN29 : AN29 analog input selection bit
bits : 5 - 4 (0 bit)
access : read-write

AN30 : AN30 analog input selection bit
bits : 6 - 5 (0 bit)
access : read-write

AN31 : AN31 analog input selection bit
bits : 7 - 6 (0 bit)
access : read-write


SCIS0

Scan Conversion Input Selection Register 0
address_offset : 0x14 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCIS0 SCIS0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7

AN0 : AN0 analog input selection bit
bits : 0 - -1 (0 bit)
access : read-write

AN1 : AN1 analog input selection bit
bits : 1 - 0 (0 bit)
access : read-write

AN2 : AN2 analog input selection bit
bits : 2 - 1 (0 bit)
access : read-write

AN3 : AN3 analog input selection bit
bits : 3 - 2 (0 bit)
access : read-write

AN4 : AN4 analog input selection bit
bits : 4 - 3 (0 bit)
access : read-write

AN5 : AN5 analog input selection bit
bits : 5 - 4 (0 bit)
access : read-write

AN6 : AN6 analog input selection bit
bits : 6 - 5 (0 bit)
access : read-write

AN7 : AN7 analog input selection bit
bits : 7 - 6 (0 bit)
access : read-write


SCIS1

Scan Conversion Input Selection Register 1
address_offset : 0x15 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCIS1 SCIS1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15

AN8 : AN8 analog input selection bit
bits : 0 - -1 (0 bit)
access : read-write

AN9 : AN9 analog input selection bit
bits : 1 - 0 (0 bit)
access : read-write

AN10 : AN10 analog input selection bit
bits : 2 - 1 (0 bit)
access : read-write

AN11 : AN11 analog input selection bit
bits : 3 - 2 (0 bit)
access : read-write

AN12 : AN12 analog input selection bit
bits : 4 - 3 (0 bit)
access : read-write

AN13 : AN13 analog input selection bit
bits : 5 - 4 (0 bit)
access : read-write

AN14 : AN14 analog input selection bit
bits : 6 - 5 (0 bit)
access : read-write

AN15 : AN15 analog input selection bit
bits : 7 - 6 (0 bit)
access : read-write


PFNS

Priority Conversion FIFO Stage Count Setup Register
address_offset : 0x18 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PFNS PFNS read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PFS TEST

PFS : Priority conversion FIFO stage count setting bits
bits : 0 - 0 (1 bit)
access : read-write

TEST : Test bits
bits : 4 - 4 (1 bit)
access : read-only


PCCR

Priority Conversion Control Register
address_offset : 0x19 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCCR PCCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PSTR PHEN PEEN ESCE PFCLR POVR PFUL PEMP

PSTR : Priority conversion start bit
bits : 0 - -1 (0 bit)
access : read-write

PHEN : Priority conversion timer start enable bit
bits : 1 - 0 (0 bit)
access : read-write

PEEN : Priority conversion external start enable bit
bits : 2 - 1 (0 bit)
access : read-write

ESCE : External trigger analog input selection bit
bits : 3 - 2 (0 bit)
access : read-write

PFCLR : Priority conversion FIFO clear bit
bits : 4 - 3 (0 bit)
access : read-write

POVR : Priority conversion overrun flag
bits : 5 - 4 (0 bit)
access : read-write

PFUL : Priority conversion FIFO full bit
bits : 6 - 5 (0 bit)
access : read-only

PEMP : Priority conversion FIFO empty bit
bits : 7 - 6 (0 bit)
access : read-only


PCFD

Priority Conversion FIFO Data Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PCFD PCFD read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PC RS INVL PD

PC : Conversion input channel bits
bits : 0 - 3 (4 bit)
access : read-only

RS : Scan conversion start factor
bits : 8 - 9 (2 bit)
access : read-only

INVL : A/D conversion result disable bit
bits : 12 - 11 (0 bit)
access : read-only

PD : Priority conversion result
bits : 20 - 30 (11 bit)
access : read-only


PCIS

Priority Conversion Input Selection Register
address_offset : 0x20 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCIS PCIS read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 P1A P2A

P1A : Priority level 1 analog input selection
bits : 0 - 1 (2 bit)
access : read-write

P2A : Priority level 2 analog input selection
bits : 3 - 6 (4 bit)
access : read-write


CMPCR

A/D Comparison Control Register
address_offset : 0x24 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPCR CMPCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CCH CMD0 CMD1 CMPEN

CCH : Comparison target analog input channel
bits : 0 - 3 (4 bit)
access : read-write

CMD0 : Comparison mode 0
bits : 5 - 4 (0 bit)
access : read-write

CMD1 : Comparison mode 1
bits : 6 - 5 (0 bit)
access : read-write

CMPEN : Conversion result comparison function operation enable bit
bits : 7 - 6 (0 bit)
access : read-write


CMPD

A/D Comparison Value Setup Register
address_offset : 0x26 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPD CMPD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMAD

CMAD : A/D conversion compare value setting bits
bits : 6 - 14 (9 bit)
access : read-write


ADSS2

Sampling Time Selection Register 2
address_offset : 0x28 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADSS2 ADSS2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TS16 TS17 TS18 TS19 TS20 TS21 TS22 TS23

TS16 : AN16 sampling time selection bit
bits : 0 - -1 (0 bit)
access : read-write

TS17 : AN17 sampling time selection bit
bits : 1 - 0 (0 bit)
access : read-write

TS18 : AN18 sampling time selection bit
bits : 2 - 1 (0 bit)
access : read-write

TS19 : AN19 sampling time selection bit
bits : 3 - 2 (0 bit)
access : read-write

TS20 : AN20 sampling time selection bit
bits : 4 - 3 (0 bit)
access : read-write

TS21 : AN21 sampling time selection bit
bits : 5 - 4 (0 bit)
access : read-write

TS22 : AN22 sampling time selection bit
bits : 6 - 5 (0 bit)
access : read-write

TS23 : AN23 sampling time selection bit
bits : 7 - 6 (0 bit)
access : read-write


ADSS3

Sampling Time Selection Register 3
address_offset : 0x29 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADSS3 ADSS3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TS24 TS25 TS26 TS27 TS28 TS29 TS30 TS31

TS24 : AN24 sampling time selection bit
bits : 0 - -1 (0 bit)
access : read-write

TS25 : AN25 sampling time selection bit
bits : 1 - 0 (0 bit)
access : read-write

TS26 : AN26 sampling time selection bit
bits : 2 - 1 (0 bit)
access : read-write

TS27 : AN27 sampling time selection bit
bits : 3 - 2 (0 bit)
access : read-write

TS28 : AN28 sampling time selection bit
bits : 4 - 3 (0 bit)
access : read-write

TS29 : AN29 sampling time selection bit
bits : 5 - 4 (0 bit)
access : read-write

TS30 : AN30 sampling time selection bit
bits : 6 - 5 (0 bit)
access : read-write

TS31 : AN31 sampling time selection bit
bits : 7 - 6 (0 bit)
access : read-write


ADSS0

Sampling Time Selection Register 0
address_offset : 0x2C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADSS0 ADSS0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TS0 TS1 TS2 TS3 TS4 TS5 TS6 TS7

TS0 : AN0 sampling time selection bit
bits : 0 - -1 (0 bit)
access : read-write

TS1 : AN1 sampling time selection bit
bits : 1 - 0 (0 bit)
access : read-write

TS2 : AN2 sampling time selection bit
bits : 2 - 1 (0 bit)
access : read-write

TS3 : AN3 sampling time selection bit
bits : 3 - 2 (0 bit)
access : read-write

TS4 : AN4 sampling time selection bit
bits : 4 - 3 (0 bit)
access : read-write

TS5 : AN5 sampling time selection bit
bits : 5 - 4 (0 bit)
access : read-write

TS6 : AN6 sampling time selection bit
bits : 6 - 5 (0 bit)
access : read-write

TS7 : AN7 sampling time selection bit
bits : 7 - 6 (0 bit)
access : read-write


ADSS1

Sampling Time Selection Register 1
address_offset : 0x2D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADSS1 ADSS1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TS8 TS9 TS10 TS11 TS12 TS13 TS14 TS15

TS8 : AN8 sampling time selection bit
bits : 0 - -1 (0 bit)
access : read-write

TS9 : AN9 sampling time selection bit
bits : 1 - 0 (0 bit)
access : read-write

TS10 : AN10 sampling time selection bit
bits : 2 - 1 (0 bit)
access : read-write

TS11 : AN11 sampling time selection bit
bits : 3 - 2 (0 bit)
access : read-write

TS12 : AN12 sampling time selection bit
bits : 4 - 3 (0 bit)
access : read-write

TS13 : AN13 sampling time selection bit
bits : 5 - 4 (0 bit)
access : read-write

TS14 : AN14 sampling time selection bit
bits : 6 - 5 (0 bit)
access : read-write

TS15 : AN15 sampling time selection bit
bits : 7 - 6 (0 bit)
access : read-write


ADST1

Sampling Time Setup Register 1
address_offset : 0x30 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADST1 ADST1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ST1 STX1

ST1 : Sampling time setting bits
bits : 0 - 3 (4 bit)
access : read-write

STX1 : Sampling time N times setting bits
bits : 5 - 6 (2 bit)
access : read-write


ADST0

Sampling Time Setup Register 0
address_offset : 0x31 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADST0 ADST0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ST0 STX0

ST0 : Sampling time setting bits
bits : 0 - 3 (4 bit)
access : read-write

STX0 : Sampling time N times setting bits
bits : 5 - 6 (2 bit)
access : read-write


ADCT

Frequency Division Ratio Setup Register
address_offset : 0x34 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADCT ADCT read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CT

CT : Frequency division ratio setting bits
bits : 0 - 6 (7 bit)
access : read-write


PRTSL

Priority Conversion Timer Trigger Selection Register
address_offset : 0x38 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRTSL PRTSL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRTSL

PRTSL : Priority conversion timer trigger selection bits
bits : 0 - 2 (3 bit)
access : read-write


SCTSL

Scan Conversion Timer Trigger Selection Register
address_offset : 0x39 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCTSL SCTSL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SCTSL

SCTSL : Scan conversion timer trigger selection bits
bits : 0 - 2 (3 bit)
access : read-write


ADCEN

A/D Operation Enable Setup Register
address_offset : 0x3C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADCEN ADCEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENBL READY ENBLTIME

ENBL : A/D operation enable bit
bits : 0 - -1 (0 bit)
access : read-write

READY : A/D operation enable state bit
bits : 1 - 0 (0 bit)
access : read-only

ENBLTIME : Operation enable state transition cycle selection bits
bits : 8 - 14 (7 bit)
access : read-write


WCMRCIF

Range Comparison Flag Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WCMRCIF WCMRCIF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCINT

RCINT : Range comparison interrupt factor flag bit
bits : 0 - -1 (0 bit)
access : read-write


WCMRCOT

Range Comparison Threshold Excess Flag Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WCMRCOT WCMRCOT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCOOF

RCOOF : Threshold excess flag bit
bits : 0 - -1 (0 bit)
access : read-write


WCMPCR

ERROR!!!!!!!!!!!!!!!!!!!!
address_offset : 0x4C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WCMPCR WCMPCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RCOE RCOIE RCOIRS RCOCD RCODC

RCOE : ERROR!!!!!!!!!!!!!!!!!!!!
bits : 2 - 1 (0 bit)
access : read-write

RCOIE : ERROR!!!!!!!!!!!!!!!!!!!!
bits : 3 - 2 (0 bit)
access : read-write

RCOIRS : ERROR!!!!!!!!!!!!!!!!!!!!
bits : 4 - 3 (0 bit)
access : read-write

RCOCD : Continuous detection specification count/state indication bits
bits : 5 - 6 (2 bit)
access : read-write

RCODC : ERROR!!!!!!!!!!!!!!!!!!!!
bits : 5 - 6 (2 bit)
access : read-write


WCMPSR

ERROR!!!!!!!!!!!!!!!!!!!!
address_offset : 0x4D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WCMPSR WCMPSR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 WCCH WCMD

WCCH : ERROR!!!!!!!!!!!!!!!!!!!!
bits : 0 - 3 (4 bit)
access : read-write

WCMD : ERROR!!!!!!!!!!!!!!!!!!!!
bits : 5 - 4 (0 bit)
access : read-write


WCMPDL

ERROR!!!!!!!!!!!!!!!!!!!!
address_offset : 0x50 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WCMPDL WCMPDL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMLD

CMLD : ERROR!!!!!!!!!!!!!!!!!!!!
bits : 6 - 14 (9 bit)
access : read-write


WCMPDH

ERROR!!!!!!!!!!!!!!!!!!!!
address_offset : 0x52 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WCMPDH WCMPDH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMHD

CMHD : ERROR!!!!!!!!!!!!!!!!!!!!
bits : 6 - 14 (9 bit)
access : read-write


SFNS

Scan Conversion FIFO Stage Count Setup Register
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SFNS SFNS read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SFS

SFS : Scan conversion FIFO stage count setting bits
bits : 0 - 2 (3 bit)
access : read-write


SCCR

Scan Conversion Control Register
address_offset : 0x9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCCR SCCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SSTR SHEN RPT SFCLR SOVR SFUL SEMP

SSTR : Scan conversion start bit
bits : 0 - -1 (0 bit)
access : read-write

SHEN : Scan conversion timer start enable bit
bits : 1 - 0 (0 bit)
access : read-write

RPT : Scan conversion repeat bit
bits : 2 - 1 (0 bit)
access : read-write

SFCLR : Scan conversion FIFO clear bit
bits : 4 - 3 (0 bit)
access : read-write

SOVR : Scan conversion overrun flag
bits : 5 - 4 (0 bit)
access : read-write

SFUL : Scan conversion FIFO full bit
bits : 6 - 5 (0 bit)
access : read-only

SEMP : Scan conversion FIFO empty bit
bits : 7 - 6 (0 bit)
access : read-only


SCFD

Scan Conversion FIFO Data Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SCFD SCFD read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SC RS INVL SD

SC : Conversion input channel bits
bits : 0 - 3 (4 bit)
access : read-only

RS : Scan conversion start factor
bits : 8 - 8 (1 bit)
access : read-only

INVL : A/D conversion result disable bit
bits : 12 - 11 (0 bit)
access : read-only

SD : Scan conversion result
bits : 20 - 30 (11 bit)
access : read-only



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