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INTREQ

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x10 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xC Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x1C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x20 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x80 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x90 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x50 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x88 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x3C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x44 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x48 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x14 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x18 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x24 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x28 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x2C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x30 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x34 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x38 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x40 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x4C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x54 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x58 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x5C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x60 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x64 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x68 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x6C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x70 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x74 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x78 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x7C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x84 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x8C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x210 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x214 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

Registers

DRQSEL

EXC02MON

IRQ00MON

IRQ01MON

IRQ02MON

IRQ03MON

RCINTSEL0

RCINTSEL1

IRQ04MON

IRQ05MON

IRQ06MON

IRQ07MON

IRQ08MON

IRQ09MON

IRQ10MON

IRQ11MON

IRQ12MON

IRQ13MON

IRQ14MON

IRQ15MON

IRQ16MON

IRQ17MON

IRQ18MON

IRQ19MON

IRQ20MON

IRQ21MON

IRQ22MON

IRQ23MON

IRQ24MON

IRQ25MON

IRQ26MON

IRQ27MON

IRQ28MON

IRQ29MON

IRQ30MON

IRQ31MON

IRQCMODE


DRQSEL

DMA Request Selection Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DRQSEL DRQSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADCSCAN0 ADCSCAN1 ADCSCAN2 IRQ0BT0 IRQ0BT2 IRQ0BT4 IRQ0BT6 MFS0RX MFS0TX MFS1RX MFS1TX MFS2RX MFS2TX MFS3RX MFS3TX MFS4RX MFS4TX MFS5RX MFS5TX MFS6RX MFS6TX MFS7RX MFS7TX EXINT0 EXINT1 EXINT2 EXINT3

ADCSCAN0 : The scan conversion interrupt signal of the A/D converter unit 0 is output as a transfer request to the DMAC
bits : 5 - 4 (0 bit)
access : read-write

ADCSCAN1 : The scan conversion interrupt signal of the A/D converter unit 1 is output as a transfer request to the DMAC
bits : 6 - 5 (0 bit)
access : read-write

ADCSCAN2 : The scan conversion interrupt signal of the A/D converter unit 2 is output as a transfer request to the DMAC
bits : 7 - 6 (0 bit)
access : read-write

IRQ0BT0 : The IRQ0 interrupt signal of the base timer ch.0 is output as a transfer request to the DMAC
bits : 8 - 7 (0 bit)
access : read-write

IRQ0BT2 : The IRQ0 interrupt signal of the base timer ch.2 is output as a transfer request to the DMAC
bits : 9 - 8 (0 bit)
access : read-write

IRQ0BT4 : The IRQ0 interrupt signal of the base timer ch.4 is output as a transfer request to the DMAC
bits : 10 - 9 (0 bit)
access : read-write

IRQ0BT6 : The IRQ0 interrupt signal of the base timer ch.6 is output as a transfer request to the DMAC
bits : 11 - 10 (0 bit)
access : read-write

MFS0RX : The reception interrupt signal of the MFS ch.0 is output as a transfer request to the DMAC
bits : 12 - 11 (0 bit)
access : read-write

MFS0TX : The transmission interrupt signal of the MFS ch.0 is output as a transfer request to the DMAC
bits : 13 - 12 (0 bit)
access : read-write

MFS1RX : The reception interrupt signal of the MFS ch.1 is output as a transfer request to the DMAC
bits : 14 - 13 (0 bit)
access : read-write

MFS1TX : The transmission interrupt signal of the MFS ch.1 is output as a transfer request to the DMAC
bits : 15 - 14 (0 bit)
access : read-write

MFS2RX : The reception interrupt signal of the MFS ch.2 is output as a transfer request to the DMAC
bits : 16 - 15 (0 bit)
access : read-write

MFS2TX : The transmission interrupt signal of the MFS ch.2 is output as a transfer request to the DMAC
bits : 17 - 16 (0 bit)
access : read-write

MFS3RX : The reception interrupt signal of the MFS ch.3 is output as a transfer request to the DMAC
bits : 18 - 17 (0 bit)
access : read-write

MFS3TX : The transmission interrupt signal of the MFS ch.3 is output as a transfer request to the DMAC
bits : 19 - 18 (0 bit)
access : read-write

MFS4RX : The reception interrupt signal of the MFS ch.4 is output as a transfer request to the DMAC
bits : 20 - 19 (0 bit)
access : read-write

MFS4TX : The transmission interrupt signal of the MFS ch.4 is output as a transfer request to the DMAC
bits : 21 - 20 (0 bit)
access : read-write

MFS5RX : The reception interrupt signal of the MFS ch.5 is output as a transfer request to the DMAC
bits : 22 - 21 (0 bit)
access : read-write

MFS5TX : The transmission interrupt signal of the MFS ch.5 is output as a transfer request to the DMAC
bits : 23 - 22 (0 bit)
access : read-write

MFS6RX : The reception interrupt signal of the MFS ch.6 is output as a transfer request to the DMAC
bits : 24 - 23 (0 bit)
access : read-write

MFS6TX : The transmission interrupt signal of the MFS ch.6 is output as a transfer request to the DMAC
bits : 25 - 24 (0 bit)
access : read-write

MFS7RX : The reception interrupt signal of the MFS ch.7 is output as a transfer request to the DMAC
bits : 26 - 25 (0 bit)
access : read-write

MFS7TX : The transmission interrupt signal of the MFS ch.7 is output as a transfer request to the DMAC
bits : 27 - 26 (0 bit)
access : read-write

EXINT0 : The interrupt signal of the external interrupt ch.0 is output as a transfer request to the DMAC
bits : 28 - 27 (0 bit)
access : read-write

EXINT1 : The interrupt signal of the external interrupt ch.1 is output as a transfer request to the DMAC
bits : 29 - 28 (0 bit)
access : read-write

EXINT2 : The interrupt signal of the external interrupt ch.2 is output as a transfer request to the DMAC
bits : 30 - 29 (0 bit)
access : read-write

EXINT3 : The interrupt signal of the external interrupt ch.3 is output as a transfer request to the DMAC
bits : 31 - 30 (0 bit)
access : read-write


EXC02MON

EXC02 Batch Read Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EXC02MON EXC02MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NMI HWINT

NMI : NMIX external pin interrupt request
bits : 0 - -1 (0 bit)
access : read-only

HWINT : Hardware watchdog timer interrupt request
bits : 1 - 0 (0 bit)
access : read-only


IRQ00MON

IRQ00 Batch Read Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ00MON IRQ00MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FCSINT

FCSINT : Anomalous frequency detection by CSV interrupt request
bits : 0 - -1 (0 bit)
access : read-only


IRQ01MON

IRQ01 Batch Read Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ01MON IRQ01MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWWDTINT

SWWDTINT : Software watchdog timer interrupt request
bits : 0 - -1 (0 bit)
access : read-only


IRQ02MON

IRQ02 Batch Read Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ02MON IRQ02MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LVDINT

LVDINT : Low voltage detection (LVD) interrupt request
bits : 0 - -1 (0 bit)
access : read-only


IRQ03MON

IRQ03 Batch Read Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ03MON IRQ03MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WAVE0INT0 WAVE0INT1 WAVE0INT2 WAVE0INT3 WAVE1INT0 WAVE1INT1 WAVE1INT2 WAVE1INT3 WAVE2INT0 WAVE2INT1 WAVE2INT2 WAVE2INT3

WAVE0INT0 : DTIF (motor emergency stop) interrupt request in MFT unit 0
bits : 0 - -1 (0 bit)
access : read-only

WAVE0INT1 : WFG timer 10 interrupt request in MFT unit 0
bits : 1 - 0 (0 bit)
access : read-only

WAVE0INT2 : WFG timer 32 interrupt request in MFT unit 0
bits : 2 - 1 (0 bit)
access : read-only

WAVE0INT3 : WFG timer 54 interrupt request in MFT unit 0
bits : 3 - 2 (0 bit)
access : read-only

WAVE1INT0 : DTIF (motor emergency stop) interrupt request in MFT unit 1
bits : 4 - 3 (0 bit)
access : read-only

WAVE1INT1 : WFG timer 10 interrupt request in MFT unit 1
bits : 5 - 4 (0 bit)
access : read-only

WAVE1INT2 : WFG timer 32 interrupt request in MFT unit 1
bits : 6 - 5 (0 bit)
access : read-only

WAVE1INT3 : WFG timer 54 interrupt request in MFT unit 1
bits : 7 - 6 (0 bit)
access : read-only

WAVE2INT0 : DTIF (motor emergency stop) interrupt request in MFT unit 2
bits : 8 - 7 (0 bit)
access : read-only

WAVE2INT1 : WFG timer 10 interrupt request in MFT unit 2
bits : 9 - 8 (0 bit)
access : read-only

WAVE2INT2 : WFG timer 32 interrupt request in MFT unit 2
bits : 10 - 9 (0 bit)
access : read-only

WAVE2INT3 : WFG timer 54 interrupt request in MFT unit 2
bits : 11 - 10 (0 bit)
access : read-only


RCINTSEL0

Interrupt Factor Selection Register 0
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RCINTSEL0 RCINTSEL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTSEL0 INTSEL1 INTSEL2 INTSEL3

INTSEL0 : Select the interrupt factor for the interrupt vector No.19
bits : 0 - 6 (7 bit)
access : read-write

INTSEL1 : Select the interrupt factor for the interrupt vector No.20
bits : 8 - 14 (7 bit)
access : read-write

INTSEL2 : Select the interrupt factor for the interrupt vector No.21
bits : 16 - 22 (7 bit)
access : read-write

INTSEL3 : Select the interrupt factor for the interrupt vector No.22
bits : 24 - 30 (7 bit)
access : read-write


RCINTSEL1

Interrupt Factor Selection Register 1
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RCINTSEL1 RCINTSEL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTSEL4 INTSEL5 INTSEL6 INTSEL7

INTSEL4 : Select the interrupt factor for the interrupt vector No.23
bits : 0 - 6 (7 bit)
access : read-write

INTSEL5 : Select the interrupt factor for the interrupt vector No.24
bits : 8 - 14 (7 bit)
access : read-write

INTSEL6 : Select the interrupt factor for the interrupt vector No.25
bits : 16 - 22 (7 bit)
access : read-write

INTSEL7 : Select the interrupt factor for the interrupt vector No.26
bits : 24 - 30 (7 bit)
access : read-write


IRQ04MON

IRQ04 Batch Read Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ04MON IRQ04MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTINT0 EXTINT1 EXTINT2 EXTINT3 EXTINT4 EXTINT5 EXTINT6 EXTINT7

EXTINT0 : Interrupt request of external interrupt ch.0
bits : 0 - -1 (0 bit)
access : read-only

EXTINT1 : Interrupt request of external interrupt ch.1
bits : 1 - 0 (0 bit)
access : read-only

EXTINT2 : Interrupt request of external interrupt ch.2
bits : 2 - 1 (0 bit)
access : read-only

EXTINT3 : Interrupt request of external interrupt ch.3
bits : 3 - 2 (0 bit)
access : read-only

EXTINT4 : Interrupt request of external interrupt ch.4
bits : 4 - 3 (0 bit)
access : read-only

EXTINT5 : Interrupt request of external interrupt ch.5
bits : 5 - 4 (0 bit)
access : read-only

EXTINT6 : Interrupt request of external interrupt ch.6
bits : 6 - 5 (0 bit)
access : read-only

EXTINT7 : Interrupt request of external interrupt ch.7
bits : 7 - 6 (0 bit)
access : read-only


IRQ05MON

IRQ05 Batch Read Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ05MON IRQ05MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTINT8 EXTINT9 EXTINT10 EXTINT11 EXTINT12 EXTINT13 EXTINT14 EXTINT15 EXTINT16 EXTINT17 EXTINT18 EXTINT19 EXTINT20 EXTINT21 EXTINT22 EXTINT23 EXTINT24 EXTINT25 EXTINT26 EXTINT27 EXTINT28 EXTINT29 EXTINT30 EXTINT31

EXTINT8 : Interrupt request of external interrupt ch.8
bits : 0 - -1 (0 bit)
access : read-only

EXTINT9 : Interrupt request of external interrupt ch.9
bits : 1 - 0 (0 bit)
access : read-only

EXTINT10 : Interrupt request of external interrupt ch.10
bits : 2 - 1 (0 bit)
access : read-only

EXTINT11 : Interrupt request of external interrupt ch.11
bits : 3 - 2 (0 bit)
access : read-only

EXTINT12 : Interrupt request of external interrupt ch.12
bits : 4 - 3 (0 bit)
access : read-only

EXTINT13 : Interrupt request of external interrupt ch.13
bits : 5 - 4 (0 bit)
access : read-only

EXTINT14 : Interrupt request of external interrupt ch.14
bits : 6 - 5 (0 bit)
access : read-only

EXTINT15 : Interrupt request of external interrupt ch.15
bits : 7 - 6 (0 bit)
access : read-only

EXTINT16 : Interrupt request of external interrupt ch.16
bits : 8 - 7 (0 bit)
access : read-only

EXTINT17 : Interrupt request of external interrupt ch.17
bits : 9 - 8 (0 bit)
access : read-only

EXTINT18 : Interrupt request of external interrupt ch.18
bits : 10 - 9 (0 bit)
access : read-only

EXTINT19 : Interrupt request of external interrupt ch.19
bits : 11 - 10 (0 bit)
access : read-only

EXTINT20 : Interrupt request of external interrupt ch.20
bits : 12 - 11 (0 bit)
access : read-only

EXTINT21 : Interrupt request of external interrupt ch.21
bits : 13 - 12 (0 bit)
access : read-only

EXTINT22 : Interrupt request of external interrupt ch.22
bits : 14 - 13 (0 bit)
access : read-only

EXTINT23 : Interrupt request of external interrupt ch.23
bits : 15 - 14 (0 bit)
access : read-only

EXTINT24 : Interrupt request of external interrupt ch.24
bits : 16 - 15 (0 bit)
access : read-only

EXTINT25 : Interrupt request of external interrupt ch.25
bits : 17 - 16 (0 bit)
access : read-only

EXTINT26 : Interrupt request of external interrupt ch.26
bits : 18 - 17 (0 bit)
access : read-only

EXTINT27 : Interrupt request of external interrupt ch.27
bits : 19 - 18 (0 bit)
access : read-only

EXTINT28 : Interrupt request of external interrupt ch.28
bits : 20 - 19 (0 bit)
access : read-only

EXTINT29 : Interrupt request of external interrupt ch.29
bits : 21 - 20 (0 bit)
access : read-only

EXTINT30 : Interrupt request of external interrupt ch.30
bits : 22 - 21 (0 bit)
access : read-only

EXTINT31 : Interrupt request of external interrupt ch.31
bits : 23 - 22 (0 bit)
access : read-only


IRQ06MON

IRQ06 Batch Read Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ06MON IRQ06MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMINT1 TIMINT2 QUD0INT0 QUD0INT1 QUD0INT2 QUD0INT3 QUD0INT4 QUD0INT5 QUD1INT0 QUD1INT1 QUD1INT2 QUD1INT3 QUD1INT4 QUD1INT5 QUD2INT0 QUD2INT1 QUD2INT2 QUD2INT3 QUD2INT4 QUD2INT5

TIMINT1 : Dual timer TIMINT1 interrupt request
bits : 0 - -1 (0 bit)
access : read-only

TIMINT2 : Dual timer TIMINT2 interrupt request
bits : 1 - 0 (0 bit)
access : read-only

QUD0INT0 : PC match interrupt request of QPRC ch.0
bits : 2 - 1 (0 bit)
access : read-only

QUD0INT1 : PC and RC match interrupt request of QPRC ch.0
bits : 3 - 2 (0 bit)
access : read-only

QUD0INT2 : Overflow/underflow/zero index interrupt request of QPRC ch.0
bits : 4 - 3 (0 bit)
access : read-only

QUD0INT3 : PC count invert interrupt request of QPRC ch.0
bits : 5 - 4 (0 bit)
access : read-only

QUD0INT4 : Interrupt request detected RC out of range of QPRC ch.0
bits : 6 - 5 (0 bit)
access : read-only

QUD0INT5 : PC match and RC match interrupt request of QPRC ch.0
bits : 7 - 6 (0 bit)
access : read-only

QUD1INT0 : PC match interrupt request of QPRC ch.1
bits : 8 - 7 (0 bit)
access : read-only

QUD1INT1 : PC and RC match interrupt request of QPRC ch.1
bits : 9 - 8 (0 bit)
access : read-only

QUD1INT2 : Overflow/underflow/zero index interrupt request of QPRC ch.1
bits : 10 - 9 (0 bit)
access : read-only

QUD1INT3 : PC count invert interrupt request of QPRC ch.1
bits : 11 - 10 (0 bit)
access : read-only

QUD1INT4 : Interrupt request detected RC out of range of QPRC ch.1
bits : 12 - 11 (0 bit)
access : read-only

QUD1INT5 : PC match and RC match interrupt request of QPRC ch.1
bits : 13 - 12 (0 bit)
access : read-only

QUD2INT0 : PC match interrupt request of QPRC ch.2
bits : 14 - 13 (0 bit)
access : read-only

QUD2INT1 : PC and RC match interrupt request of QPRC ch.2
bits : 15 - 14 (0 bit)
access : read-only

QUD2INT2 : Overflow/underflow/zero index interrupt request of QPRC ch.2
bits : 16 - 15 (0 bit)
access : read-only

QUD2INT3 : PC count invert interrupt request of QPRC ch.2
bits : 17 - 16 (0 bit)
access : read-only

QUD2INT4 : Interrupt request detected RC out of range of QPRC ch.2
bits : 18 - 17 (0 bit)
access : read-only

QUD2INT5 : PC match and RC match interrupt request of QPRC ch.2
bits : 19 - 18 (0 bit)
access : read-only


IRQ07MON

IRQ07 Batch Read Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ07MON IRQ07MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFSINT0 MFSINT1

MFSINT0 : Reception interrupt request of MFS channel 0
bits : 0 - -1 (0 bit)
access : read-only

MFSINT1 : Reception interrupt request of MFS channel 8
bits : 1 - 0 (0 bit)
access : read-only


IRQ08MON

IRQ08 Batch Read Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ08MON IRQ08MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFSINT0 MFSINT1 MFSINT2 MFSINT3

MFSINT0 : Transmission interrupt request of MFS channel 0
bits : 0 - -1 (0 bit)
access : read-only

MFSINT1 : Status interrupt request of MFS channel 0
bits : 1 - 0 (0 bit)
access : read-only

MFSINT2 : Transmission interrupt request of MFS channel 8
bits : 2 - 1 (0 bit)
access : read-only

MFSINT3 : Status interrupt request of MFS channel 8
bits : 3 - 2 (0 bit)
access : read-only


IRQ09MON

IRQ09 Batch Read Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ09MON IRQ09MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFSINT0 MFSINT1

MFSINT0 : Reception interrupt request of MFS channel 1
bits : 0 - -1 (0 bit)
access : read-only

MFSINT1 : Reception interrupt request of MFS channel 9
bits : 1 - 0 (0 bit)
access : read-only


IRQ10MON

IRQ10 Batch Read Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ10MON IRQ10MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFSINT0 MFSINT1 MFSINT2 MFSINT3

MFSINT0 : Transmission interrupt request of MFS channel 1
bits : 0 - -1 (0 bit)
access : read-only

MFSINT1 : Status interrupt request of MFS channel 1
bits : 1 - 0 (0 bit)
access : read-only

MFSINT2 : Transmission interrupt request of MFS channel 9
bits : 2 - 1 (0 bit)
access : read-only

MFSINT3 : Status interrupt request of MFS channel 9
bits : 3 - 2 (0 bit)
access : read-only


IRQ11MON

IRQ11 Batch Read Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ11MON IRQ11MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFSINT0 MFSINT1

MFSINT0 : Reception interrupt request of MFS channel 2
bits : 0 - -1 (0 bit)
access : read-only

MFSINT1 : Reception interrupt request of MFS channel 10
bits : 1 - 0 (0 bit)
access : read-only


IRQ12MON

IRQ12 Batch Read Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ12MON IRQ12MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFSINT0 MFSINT1 MFSINT2 MFSINT3

MFSINT0 : Transmission interrupt request of MFS channel 2
bits : 0 - -1 (0 bit)
access : read-only

MFSINT1 : Status interrupt request of MFS channel 2
bits : 1 - 0 (0 bit)
access : read-only

MFSINT2 : Transmission interrupt request of MFS channel 10
bits : 2 - 1 (0 bit)
access : read-only

MFSINT3 : Status interrupt request of MFS channel 10
bits : 3 - 2 (0 bit)
access : read-only


IRQ13MON

IRQ13 Batch Read Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ13MON IRQ13MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFSINT0 MFSINT1

MFSINT0 : Reception interrupt request of MFS channel 3
bits : 0 - -1 (0 bit)
access : read-only

MFSINT1 : Reception interrupt request of MFS channel 11
bits : 1 - 0 (0 bit)
access : read-only


IRQ14MON

IRQ14 Batch Read Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ14MON IRQ14MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFSINT0 MFSINT1 MFSINT2 MFSINT3

MFSINT0 : Transmission interrupt request of MFS channel 3
bits : 0 - -1 (0 bit)
access : read-only

MFSINT1 : Status interrupt request of MFS channel 3
bits : 1 - 0 (0 bit)
access : read-only

MFSINT2 : Transmission interrupt request of MFS channel 11
bits : 2 - 1 (0 bit)
access : read-only

MFSINT3 : Status interrupt request of MFS channel 11
bits : 3 - 2 (0 bit)
access : read-only


IRQ15MON

IRQ15 Batch Read Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ15MON IRQ15MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFSINT0 MFSINT1

MFSINT0 : Reception interrupt request of MFS channel 4
bits : 0 - -1 (0 bit)
access : read-only

MFSINT1 : Reception interrupt request of MFS channel 12
bits : 1 - 0 (0 bit)
access : read-only


IRQ16MON

IRQ16 Batch Read Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ16MON IRQ16MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFSINT0 MFSINT1 MFSINT2 MFSINT3

MFSINT0 : Transmission interrupt request of MFS channel 4
bits : 0 - -1 (0 bit)
access : read-only

MFSINT1 : Status interrupt request of MFS channel 4
bits : 1 - 0 (0 bit)
access : read-only

MFSINT2 : Transmission interrupt request of MFS channel 12
bits : 2 - 1 (0 bit)
access : read-only

MFSINT3 : Status interrupt request of MFS channel 12
bits : 3 - 2 (0 bit)
access : read-only


IRQ17MON

IRQ17 Batch Read Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ17MON IRQ17MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFSINT0 MFSINT1

MFSINT0 : Reception interrupt request of MFS channel 5
bits : 0 - -1 (0 bit)
access : read-only

MFSINT1 : Reception interrupt request of MFS channel 13
bits : 1 - 0 (0 bit)
access : read-only


IRQ18MON

IRQ18 Batch Read Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ18MON IRQ18MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFSINT0 MFSINT1 MFSINT2 MFSINT3

MFSINT0 : Transmission interrupt request of MFS channel 5
bits : 0 - -1 (0 bit)
access : read-only

MFSINT1 : Status interrupt request of MFS channel 5
bits : 1 - 0 (0 bit)
access : read-only

MFSINT2 : Transmission interrupt request of MFS channel 13
bits : 2 - 1 (0 bit)
access : read-only

MFSINT3 : Status interrupt request of MFS channel 13
bits : 3 - 2 (0 bit)
access : read-only


IRQ19MON

IRQ19 Batch Read Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ19MON IRQ19MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFSINT0 MFSINT1 DMAINT

MFSINT0 : Reception interrupt request of MFS channel 6
bits : 0 - -1 (0 bit)
access : read-only

MFSINT1 : Reception interrupt request of MFS channel 14
bits : 1 - 0 (0 bit)
access : read-only

DMAINT : Interrupt request of DMAC ch.0
bits : 4 - 3 (0 bit)
access : read-only


IRQ20MON

IRQ20 Batch Read Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ20MON IRQ20MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFSINT0 MFSINT1 MFSINT2 MFSINT3 DMAINT

MFSINT0 : Transmission interrupt request of MFS channel 6
bits : 0 - -1 (0 bit)
access : read-only

MFSINT1 : Status interrupt request of MFS channel 6
bits : 1 - 0 (0 bit)
access : read-only

MFSINT2 : Transmission interrupt request of MFS channel 14
bits : 2 - 1 (0 bit)
access : read-only

MFSINT3 : Status interrupt request of MFS channel 14
bits : 3 - 2 (0 bit)
access : read-only

DMAINT : Interrupt request of DMAC ch.1
bits : 4 - 3 (0 bit)
access : read-only


IRQ21MON

IRQ21 Batch Read Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ21MON IRQ21MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFSINT0 MFSINT1 DMAINT

MFSINT0 : Reception interrupt request of MFS channel 7
bits : 0 - -1 (0 bit)
access : read-only

MFSINT1 : Reception interrupt request of MFS channel 15
bits : 1 - 0 (0 bit)
access : read-only

DMAINT : Interrupt request of DMAC ch.2
bits : 4 - 3 (0 bit)
access : read-only


IRQ22MON

IRQ22 Batch Read Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ22MON IRQ22MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFSINT0 MFSINT1 MFSINT2 MFSINT3 DMAINT

MFSINT0 : Transmission interrupt request of MFS channel 7
bits : 0 - -1 (0 bit)
access : read-only

MFSINT1 : Status interrupt request of MFS channel 7
bits : 1 - 0 (0 bit)
access : read-only

MFSINT2 : Transmission interrupt request of MFS channel 15
bits : 2 - 1 (0 bit)
access : read-only

MFSINT3 : Status interrupt request of MFS channel 15
bits : 3 - 2 (0 bit)
access : read-only

DMAINT : Interrupt request of DMAC ch.3
bits : 4 - 3 (0 bit)
access : read-only


IRQ23MON

IRQ23 Batch Read Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ23MON IRQ23MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PPGINT0 PPGINT1 PPGINT2 PPGINT3 PPGINT4 PPGINT5 PPGINT6 PPGINT7 PPGINT8

PPGINT0 : Interrupt request of PPG ch.0
bits : 0 - -1 (0 bit)
access : read-only

PPGINT1 : Interrupt request of PPG ch.2
bits : 1 - 0 (0 bit)
access : read-only

PPGINT2 : Interrupt request of PPG ch.4
bits : 2 - 1 (0 bit)
access : read-only

PPGINT3 : Interrupt request of PPG ch.8
bits : 3 - 2 (0 bit)
access : read-only

PPGINT4 : Interrupt request of PPG ch.10
bits : 4 - 3 (0 bit)
access : read-only

PPGINT5 : Interrupt request of PPG ch.12
bits : 5 - 4 (0 bit)
access : read-only

PPGINT6 : Interrupt request of PPG ch.16
bits : 6 - 5 (0 bit)
access : read-only

PPGINT7 : Interrupt request of PPG ch.18
bits : 7 - 6 (0 bit)
access : read-only

PPGINT8 : Interrupt request of PPG ch.20
bits : 8 - 7 (0 bit)
access : read-only


IRQ24MON

IRQ24 Batch Read Register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ24MON IRQ24MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MOSCINT SOSCINT MPLLINT WCINT RTCINT

MOSCINT : Stabilization wait completion interrupt request for main clock oscillation
bits : 0 - -1 (0 bit)
access : read-only

SOSCINT : Stabilization wait completion interrupt request for sub-clock oscillation
bits : 1 - 0 (0 bit)
access : read-only

MPLLINT : Stabilization wait completion interrupt request for main PLL oscillation
bits : 2 - 1 (0 bit)
access : read-only

WCINT : Watch counter interrupt request
bits : 4 - 3 (0 bit)
access : read-only

RTCINT : RTC interrupt request
bits : 5 - 4 (0 bit)
access : read-only


IRQ25MON

IRQ25 Batch Read Register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ25MON IRQ25MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADCINT0 ADCINT1 ADCINT2 ADCINT3 ADCINT4

ADCINT0 : Priority conversion interrupt request in the A/D converter unit 0
bits : 0 - -1 (0 bit)
access : read-only

ADCINT1 : Scan conversion interrupt request in the A/D converter unit 0
bits : 1 - 0 (0 bit)
access : read-only

ADCINT2 : FIFO overrun interrupt request in the A/D converter unit 0
bits : 2 - 1 (0 bit)
access : read-only

ADCINT3 : Conversion result comparison interrupt request in the A/D converter unit 0
bits : 3 - 2 (0 bit)
access : read-only

ADCINT4 : Range comparison result interrupt request in the A/D converter unit 0
bits : 4 - 3 (0 bit)
access : read-only


IRQ26MON

IRQ26 Batch Read Register
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ26MON IRQ26MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADCINT0 ADCINT1 ADCINT2 ADCINT3 ADCINT4

ADCINT0 : Priority conversion interrupt request in the A/D converter unit 1
bits : 0 - -1 (0 bit)
access : read-only

ADCINT1 : Scan conversion interrupt request in the A/D converter unit 1
bits : 1 - 0 (0 bit)
access : read-only

ADCINT2 : FIFO overrun interrupt request in the A/D converter unit 1
bits : 2 - 1 (0 bit)
access : read-only

ADCINT3 : Conversion result comparison interrupt request in the A/D converter unit 1
bits : 3 - 2 (0 bit)
access : read-only

ADCINT4 : Range comparison result interrupt request in the A/D converter unit 1
bits : 4 - 3 (0 bit)
access : read-only


IRQ27MON

IRQ27 Batch Read Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ27MON IRQ27MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADCINT0 ADCINT1 ADCINT2 ADCINT3 ADCINT4 LCDCINT

ADCINT0 : Priority conversion interrupt request in the A/D converter unit 2
bits : 0 - -1 (0 bit)
access : read-only

ADCINT1 : Scan conversion interrupt request in the A/D converter unit 2
bits : 1 - 0 (0 bit)
access : read-only

ADCINT2 : FIFO overrun interrupt request in the A/D converter unit 2
bits : 2 - 1 (0 bit)
access : read-only

ADCINT3 : Conversion result comparison interrupt request in the A/D converter unit 2
bits : 3 - 2 (0 bit)
access : read-only

ADCINT4 : Range comparison result interrupt request in the A/D converter unit 2
bits : 4 - 3 (0 bit)
access : read-only

LCDCINT : Interrupt request for LCD controller
bits : 5 - 4 (0 bit)
access : read-only


IRQ28MON

IRQ28 Batch Read Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ28MON IRQ28MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRT0INT0 FRT0INT1 FRT0INT2 FRT0INT3 FRT0INT4 FRT0INT5 FRT1INT0 FRT1INT1 FRT1INT2 FRT1INT3 FRT1INT4 FRT1INT5 FRT2INT0 FRT2INT1 FRT2INT2 FRT2INT3 FRT2INT4 FRT2INT5

FRT0INT0 : Peak value detection interrupt request of the free run timer ch.0 in the MFT unit 0
bits : 0 - -1 (0 bit)
access : read-only

FRT0INT1 : Peak value detection interrupt request of the free run timer ch.1 in the MFT unit 0
bits : 1 - 0 (0 bit)
access : read-only

FRT0INT2 : Peak value detection interrupt request of the free run timer ch.2 in the MFT unit 0
bits : 2 - 1 (0 bit)
access : read-only

FRT0INT3 : Zero detection interrupt request of the free run timer ch.0 in the MFT unit 0
bits : 3 - 2 (0 bit)
access : read-only

FRT0INT4 : Zero detection interrupt request of the free run timer ch.1 in the MFT unit 0
bits : 4 - 3 (0 bit)
access : read-only

FRT0INT5 : Zero detection interrupt request of the free run timer ch.2 in the MFT unit 0
bits : 5 - 4 (0 bit)
access : read-only

FRT1INT0 : Peak value detection interrupt request of the free run timer ch.0 in the MFT unit 1
bits : 6 - 5 (0 bit)
access : read-only

FRT1INT1 : Peak value detection interrupt request of the free run timer ch.1 in the MFT unit 1
bits : 7 - 6 (0 bit)
access : read-only

FRT1INT2 : Peak value detection interrupt request of the free run timer ch.2 in the MFT unit 1
bits : 8 - 7 (0 bit)
access : read-only

FRT1INT3 : Zero detection interrupt request of the free run timer ch.0 in the MFT unit 1
bits : 9 - 8 (0 bit)
access : read-only

FRT1INT4 : Zero detection interrupt request of the free run timer ch.1 in the MFT unit 1
bits : 10 - 9 (0 bit)
access : read-only

FRT1INT5 : Zero detection interrupt request of the free run timer ch.2 in the MFT unit 1
bits : 11 - 10 (0 bit)
access : read-only

FRT2INT0 : Peak value detection interrupt request of the free run timer ch.0 in the MFT unit 2
bits : 12 - 11 (0 bit)
access : read-only

FRT2INT1 : Peak value detection interrupt request of the free run timer ch.1 in the MFT unit 2
bits : 13 - 12 (0 bit)
access : read-only

FRT2INT2 : Peak value detection interrupt request of the free run timer ch.2 in the MFT unit 2
bits : 14 - 13 (0 bit)
access : read-only

FRT2INT3 : Zero detection interrupt request of the free run timer ch.0 in the MFT unit 2
bits : 15 - 14 (0 bit)
access : read-only

FRT2INT4 : Zero detection interrupt request of the free run timer ch.1 in the MFT unit 2
bits : 16 - 15 (0 bit)
access : read-only

FRT2INT5 : Zero detection interrupt request of the free run timer ch.2 in the MFT unit 2
bits : 17 - 16 (0 bit)
access : read-only


IRQ29MON

IRQ29 Batch Read Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ29MON IRQ29MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ICU0INT0 ICU0INT1 ICU0INT2 ICU0INT3 ICU1INT0 ICU1INT1 ICU1INT2 ICU1INT3 ICU2INT0 ICU2INT1 ICU2INT2 ICU2INT3

ICU0INT0 : Interrupt request of the input capture ch.0 in the MFT unit 0
bits : 0 - -1 (0 bit)
access : read-only

ICU0INT1 : Interrupt request of the input capture ch.1 in the MFT unit 0
bits : 1 - 0 (0 bit)
access : read-only

ICU0INT2 : Interrupt request of the input capture ch.2 in the MFT unit 0
bits : 2 - 1 (0 bit)
access : read-only

ICU0INT3 : Interrupt request of the input capture ch.3 in the MFT unit 0
bits : 3 - 2 (0 bit)
access : read-only

ICU1INT0 : Interrupt request of the input capture ch.0 in the MFT unit 1
bits : 4 - 3 (0 bit)
access : read-only

ICU1INT1 : Interrupt request of the input capture ch.1 in the MFT unit 1
bits : 5 - 4 (0 bit)
access : read-only

ICU1INT2 : Interrupt request of the input capture ch.2 in the MFT unit 1
bits : 6 - 5 (0 bit)
access : read-only

ICU1INT3 : Interrupt request of the input capture ch.3 in the MFT unit 1
bits : 7 - 6 (0 bit)
access : read-only

ICU2INT0 : Interrupt request of the input capture ch.0 in the MFT unit 2
bits : 8 - 7 (0 bit)
access : read-only

ICU2INT1 : Interrupt request of the input capture ch.1 in the MFT unit 2
bits : 9 - 8 (0 bit)
access : read-only

ICU2INT2 : Interrupt request of the input capture ch.2 in the MFT unit 2
bits : 10 - 9 (0 bit)
access : read-only

ICU2INT3 : Interrupt request of the input capture ch.3 in the MFT unit 2
bits : 11 - 10 (0 bit)
access : read-only


IRQ30MON

IRQ30 Batch Read Register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ30MON IRQ30MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OCU0INT0 OCU0INT1 OCU0INT2 OCU0INT3 OCU0INT4 OCU0INT5 OCU1INT0 OCU1INT1 OCU1INT2 OCU1INT3 OCU1INT4 OCU1INT5 OCU2INT0 OCU2INT1 OCU2INT2 OCU2INT3 OCU2INT4 OCU2INT5

OCU0INT0 : Interrupt request of the output compare ch.0 in the MFT unit 0
bits : 0 - -1 (0 bit)
access : read-only

OCU0INT1 : Interrupt request of the output compare ch.1 in the MFT unit 0
bits : 1 - 0 (0 bit)
access : read-only

OCU0INT2 : Interrupt request of the output compare ch.2 in the MFT unit 0
bits : 2 - 1 (0 bit)
access : read-only

OCU0INT3 : Interrupt request of the output compare ch.3 in the MFT unit 0
bits : 3 - 2 (0 bit)
access : read-only

OCU0INT4 : Interrupt request of the output compare ch.4 in the MFT unit 0
bits : 4 - 3 (0 bit)
access : read-only

OCU0INT5 : Interrupt request of the output compare ch.5 in the MFT unit 0
bits : 5 - 4 (0 bit)
access : read-only

OCU1INT0 : Interrupt request of the output compare ch.0 in the MFT unit 1
bits : 6 - 5 (0 bit)
access : read-only

OCU1INT1 : Interrupt request of the output compare ch.1 in the MFT unit 1
bits : 7 - 6 (0 bit)
access : read-only

OCU1INT2 : Interrupt request of the output compare ch.2 in the MFT unit 1
bits : 8 - 7 (0 bit)
access : read-only

OCU1INT3 : Interrupt request of the output compare ch.3 in the MFT unit 1
bits : 9 - 8 (0 bit)
access : read-only

OCU1INT4 : Interrupt request of the output compare ch.4 in the MFT unit 1
bits : 10 - 9 (0 bit)
access : read-only

OCU1INT5 : Interrupt request of the output compare ch.5 in the MFT unit 1
bits : 11 - 10 (0 bit)
access : read-only

OCU2INT0 : Interrupt request of the output compare ch.0 in the MFT unit 2
bits : 12 - 11 (0 bit)
access : read-only

OCU2INT1 : Interrupt request of the output compare ch.1 in the MFT unit 2
bits : 13 - 12 (0 bit)
access : read-only

OCU2INT2 : Interrupt request of the output compare ch.2 in the MFT unit 2
bits : 14 - 13 (0 bit)
access : read-only

OCU2INT3 : Interrupt request of the output compare ch.3 in the MFT unit 2
bits : 15 - 14 (0 bit)
access : read-only

OCU2INT4 : Interrupt request of the output compare ch.4 in the MFT unit 2
bits : 16 - 15 (0 bit)
access : read-only

OCU2INT5 : Interrupt request of the output compare ch.5 in the MFT unit 2
bits : 17 - 16 (0 bit)
access : read-only


IRQ31MON

IRQ31 Batch Read Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ31MON IRQ31MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BTINT0 BTINT1 BTINT2 BTINT3 BTINT4 BTINT5 BTINT6 BTINT7 BTINT8 BTINT9 BTINT10 BTINT11 BTINT12 BTINT13 BTINT14 BTINT15 FLASHINT

BTINT0 : IRQ0 interrupt request of the base timer ch.0
bits : 0 - -1 (0 bit)
access : read-only

BTINT1 : IRQ1 interrupt request of the base timer ch.0
bits : 1 - 0 (0 bit)
access : read-only

BTINT2 : IRQ0 interrupt request of the base timer ch.1
bits : 2 - 1 (0 bit)
access : read-only

BTINT3 : IRQ1 interrupt request of the base timer ch.1
bits : 3 - 2 (0 bit)
access : read-only

BTINT4 : IRQ0 interrupt request of the base timer ch.2
bits : 4 - 3 (0 bit)
access : read-only

BTINT5 : IRQ1 interrupt request of the base timer ch.2
bits : 5 - 4 (0 bit)
access : read-only

BTINT6 : IRQ0 interrupt request of the base timer ch.3
bits : 6 - 5 (0 bit)
access : read-only

BTINT7 : IRQ1 interrupt request of the base timer ch.3
bits : 7 - 6 (0 bit)
access : read-only

BTINT8 : IRQ0 interrupt request of the base timer ch.4
bits : 8 - 7 (0 bit)
access : read-only

BTINT9 : IRQ1 interrupt request of the base timer ch.4
bits : 9 - 8 (0 bit)
access : read-only

BTINT10 : IRQ0 interrupt request of the base timer ch.5
bits : 10 - 9 (0 bit)
access : read-only

BTINT11 : IRQ1 interrupt request of the base timer ch.5
bits : 11 - 10 (0 bit)
access : read-only

BTINT12 : IRQ0 interrupt request of the base timer ch.6
bits : 12 - 11 (0 bit)
access : read-only

BTINT13 : IRQ1 interrupt request of the base timer ch.6
bits : 13 - 12 (0 bit)
access : read-only

BTINT14 : IRQ0 interrupt request of the base timer ch.7
bits : 14 - 13 (0 bit)
access : read-only

BTINT15 : IRQ1 interrupt request of the base timer ch.7
bits : 15 - 14 (0 bit)
access : read-only

FLASHINT : RDY/HANG interrupt request for f lash memory
bits : 27 - 26 (0 bit)
access : read-only


IRQCMODE

Interrupt Factor Vector Relocate Setting Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQCMODE IRQCMODE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRQCMODE

IRQCMODE : Assigns the interrupt factor vector according to Table 1-1 in chapter "Interrupt B"
bits : 0 - -1 (0 bit)
access : read-write



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