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INTREQ

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x10 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x14 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x110 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x200 Bytes (0x0)
size : 0x204 byte (0x0)
mem_usage : registers
protection : not protected

Registers

DRQSEL

ODDPKS

IRQ003SEL

IRQ004SEL

IRQ005SEL

IRQ006SEL

IRQ007SEL

IRQ008SEL

IRQ009SEL

IRQ010SEL

ODDPKS1

EXC02MON

IRQ000MON

IRQ001MON

IRQ002MON

IRQ003MON

IRQ004MON

IRQ005MON

IRQ006MON

IRQ007MON

IRQ008MON

IRQ009MON

IRQ010MON

IRQ011MON

IRQ012MON

IRQ013MON

IRQ014MON

IRQ015MON

IRQ016MON

IRQ017MON

IRQ018MON

IRQ019MON

IRQ020MON

IRQ021MON

IRQ022MON

IRQ023MON

IRQ024MON

IRQ025MON

IRQ026MON

IRQ027MON

IRQ028MON

IRQ029MON

IRQ030MON

IRQ031MON

IRQ032MON

IRQ033MON

IRQ034MON

IRQ035MON

IRQ036MON

IRQ037MON

IRQ038MON

IRQ039MON

IRQ040MON

IRQ041MON

IRQ042MON

IRQ043MON

IRQ044MON

IRQ045MON

IRQ046MON

IRQ047MON

IRQ048MON

IRQ049MON

IRQ050MON

IRQ051MON

IRQ052MON

IRQ053MON

IRQ054MON

IRQ055MON

IRQ056MON

IRQ057MON

IRQ058MON

IRQ059MON

IRQ060MON

IRQ061MON

IRQ062MON

IRQ063MON

IRQ064MON

IRQ065MON

IRQ066MON

IRQ067MON

IRQ068MON

IRQ069MON

IRQ070MON

IRQ071MON

IRQ072MON

IRQ073MON

IRQ074MON

IRQ075MON

IRQ076MON

IRQ077MON

IRQ078MON

IRQ079MON

IRQ080MON

IRQ081MON

IRQ082MON

IRQ083MON

IRQ084MON

IRQ085MON

IRQ086MON

IRQ087MON

IRQ088MON

IRQ089MON

IRQ090MON

IRQ091MON

IRQ092MON

IRQ093MON

IRQ094MON

IRQ095MON

IRQ096MON

IRQ097MON

IRQ098MON

IRQ099MON

IRQ100MON

IRQ101MON

IRQ102MON

IRQ103MON

IRQ104MON

IRQ105MON

IRQ106MON

IRQ107MON

IRQ108MON

IRQ109MON

IRQ110MON

IRQ111MON

IRQ112MON

IRQ113MON

IRQ114MON

IRQ115MON

IRQ116MON

IRQ117MON

IRQ118MON

IRQ119MON

IRQ120MON

IRQ121MON

IRQ122MON

IRQ123MON

IRQ124MON

IRQ125MON

IRQ126MON

IRQ127MON


DRQSEL

DMA Request Selection Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DRQSEL DRQSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USBEP1 USBEP2 USBEP3 USBEP4 USBEP5 ADCSCAN0 ADCSCAN1 ADCSCAN2 IRQ0BT0 IRQ0BT2 IRQ0BT4 IRQ0BT6 MFS0RX MFS0TX MFS1RX MFS1TX MFS2RX MFS2TX MFS3RX MFS3TX MFS4RX MFS4TX MFS5RX MFS5TX MFS6RX MFS6TX MFS7RX MFS7TX EXINT0 EXINT1 EXINT2 EXINT3

USBEP1 : USB ch.0 function endpoint 1 DRQ interrupt
bits : 0 - -1 (0 bit)
access : read-write

USBEP2 : USB ch.0 function endpoint 2 DRQ interrupt
bits : 1 - 0 (0 bit)
access : read-write

USBEP3 : USB ch.0 function endpoint 3 DRQ interrupt
bits : 2 - 1 (0 bit)
access : read-write

USBEP4 : USB ch.0 function endpoint 4 DRQ interrupt
bits : 3 - 2 (0 bit)
access : read-write

USBEP5 : USB ch.0 function endpoint 5 DRQ interrupt
bits : 4 - 3 (0 bit)
access : read-write

ADCSCAN0 : A/D converter unit 0 scan conversion interrupt
bits : 5 - 4 (0 bit)
access : read-write

ADCSCAN1 : A/D converter unit 1 scan conversion interrupt
bits : 6 - 5 (0 bit)
access : read-write

ADCSCAN2 : A/D converter unit 2 scan conversion interrupt
bits : 7 - 6 (0 bit)
access : read-write

IRQ0BT0 : Base timer ch.6 source 0 (IRQ0) interrupt
bits : 8 - 7 (0 bit)
access : read-write

IRQ0BT2 : Base timer ch.2 source 0 (IRQ0) interrupt
bits : 9 - 8 (0 bit)
access : read-write

IRQ0BT4 : Base timer ch.4 source 0 (IRQ0) interrupt
bits : 10 - 9 (0 bit)
access : read-write

IRQ0BT6 : Base timer ch.6 source 0 (IRQ0) interrupt
bits : 11 - 10 (0 bit)
access : read-write

MFS0RX : MFS ch.0 reception interrupt.
bits : 12 - 11 (0 bit)
access : read-write

MFS0TX : MFS ch.0 transmission interrupt
bits : 13 - 12 (0 bit)
access : read-write

MFS1RX : MFS ch.1 reception interrupt
bits : 14 - 13 (0 bit)
access : read-write

MFS1TX : MFS ch.1 transmission interrupt
bits : 15 - 14 (0 bit)
access : read-write

MFS2RX : MFS ch.2 reception interrupt
bits : 16 - 15 (0 bit)
access : read-write

MFS2TX : MFS ch.2 transmission interrupt
bits : 17 - 16 (0 bit)
access : read-write

MFS3RX : MFS ch.3 reception interrupt
bits : 18 - 17 (0 bit)
access : read-write

MFS3TX : MFS ch.3 transmission interrupt
bits : 19 - 18 (0 bit)
access : read-write

MFS4RX : MFS ch.4 reception interrupt
bits : 20 - 19 (0 bit)
access : read-write

MFS4TX : MFS ch.4 transmission interrupt
bits : 21 - 20 (0 bit)
access : read-write

MFS5RX : MFS ch.5 reception interrupt
bits : 22 - 21 (0 bit)
access : read-write

MFS5TX : MFS ch.5 transmission interrupt
bits : 23 - 22 (0 bit)
access : read-write

MFS6RX : MFS ch.6 reception interrupt
bits : 24 - 23 (0 bit)
access : read-write

MFS6TX : MFS ch.6 transmission interrupt
bits : 25 - 24 (0 bit)
access : read-write

MFS7RX : MFS ch.7 reception interrupt
bits : 26 - 25 (0 bit)
access : read-write

MFS7TX : MFS ch.7 transmission interrupt
bits : 27 - 26 (0 bit)
access : read-write

EXINT0 : External pin interrupt ch.0
bits : 28 - 27 (0 bit)
access : read-write

EXINT1 : External pin interrupt ch.1
bits : 29 - 28 (0 bit)
access : read-write

EXINT2 : External pin interrupt ch.2
bits : 30 - 29 (0 bit)
access : read-write

EXINT3 : External pin interrupt ch.3
bits : 31 - 30 (0 bit)
access : read-write


ODDPKS

USB ch.0 Odd Packet Size DMA Enable Register
address_offset : 0x10 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ODDPKS ODDPKS read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ODDPKS0 ODDPKS1 ODDPKS2 ODDPKS3 ODDPKS4

ODDPKS0 : If the transfer destination address of DMAC is USB.EP1DT, the bit width of the last transfer data is converted to Byte.
bits : 0 - -1 (0 bit)
access : read-write

ODDPKS1 : If the transfer destination address of DMAC is USB.EP2DT, the bit width of the last transfer data is converted to Byte.
bits : 1 - 0 (0 bit)
access : read-write

ODDPKS2 : If the transfer destination address of DMAC is USB.EP3DT, the bit width of the last transfer data is converted to Byte.
bits : 2 - 1 (0 bit)
access : read-write

ODDPKS3 : If the transfer destination address of DMAC is USB.EP4DT, the bit width of the last transfer data is converted to Byte.
bits : 3 - 2 (0 bit)
access : read-write

ODDPKS4 : If the transfer destination address of DMAC is USB.EP5DT, the bit width of the last transfer data is converted to Byte.
bits : 4 - 3 (0 bit)
access : read-write


IRQ003SEL

Relocate Interrupt Selection Register (IRQ003)
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ003SEL IRQ003SEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SELIRQ SELBIT

SELIRQ : specify the IRQ no. of a peripheral interrupt to be relocated
bits : 0 - 6 (7 bit)
access : read-write

SELBIT : Bit7 of the interrupt source is moved to bit7 of the relocate interrupt.
bits : 16 - 22 (7 bit)
access : read-write


IRQ004SEL

Relocate Interrupt Selection Register (IRQ004)
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ004SEL IRQ004SEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SELIRQ SELBIT

SELIRQ : specify the IRQ no. of a peripheral interrupt to be relocated
bits : 0 - 6 (7 bit)
access : read-write

SELBIT : Bit7 of the interrupt source is moved to bit7 of the relocate interrupt.
bits : 16 - 22 (7 bit)
access : read-write


IRQ005SEL

Relocate Interrupt Selection Register (IRQ005)
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ005SEL IRQ005SEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SELIRQ SELBIT

SELIRQ : specify the IRQ no. of a peripheral interrupt to be relocated
bits : 0 - 6 (7 bit)
access : read-write

SELBIT : Bit7 of the interrupt source is moved to bit7 of the relocate interrupt.
bits : 16 - 22 (7 bit)
access : read-write


IRQ006SEL

Relocate Interrupt Selection Register (IRQ006)
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ006SEL IRQ006SEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SELIRQ SELBIT

SELIRQ : specify the IRQ no. of a peripheral interrupt to be relocated
bits : 0 - 6 (7 bit)
access : read-write

SELBIT : Bit7 of the interrupt source is moved to bit7 of the relocate interrupt.
bits : 16 - 22 (7 bit)
access : read-write


IRQ007SEL

Relocate Interrupt Selection Register (IRQ007)
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ007SEL IRQ007SEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SELIRQ SELBIT

SELIRQ : specify the IRQ no. of a peripheral interrupt to be relocated
bits : 0 - 6 (7 bit)
access : read-write

SELBIT : Bit7 of the interrupt source is moved to bit7 of the relocate interrupt.
bits : 16 - 22 (7 bit)
access : read-write


IRQ008SEL

Relocate Interrupt Selection Register (IRQ008)
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ008SEL IRQ008SEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SELIRQ SELBIT

SELIRQ : specify the IRQ no. of a peripheral interrupt to be relocated
bits : 0 - 6 (7 bit)
access : read-write

SELBIT : Bit7 of the interrupt source is moved to bit7 of the relocate interrupt.
bits : 16 - 22 (7 bit)
access : read-write


IRQ009SEL

Relocate Interrupt Selection Register (IRQ009)
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ009SEL IRQ009SEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SELIRQ SELBIT

SELIRQ : specify the IRQ no. of a peripheral interrupt to be relocated
bits : 0 - 6 (7 bit)
access : read-write

SELBIT : Bit7 of the interrupt source is moved to bit7 of the relocate interrupt.
bits : 16 - 22 (7 bit)
access : read-write


IRQ010SEL

Relocate Interrupt Selection Register (IRQ010)
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ010SEL IRQ010SEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SELIRQ SELBIT

SELIRQ : specify the IRQ no. of a peripheral interrupt to be relocated
bits : 0 - 6 (7 bit)
access : read-write

SELBIT : Bit7 of the interrupt source is moved to bit7 of the relocate interrupt.
bits : 16 - 22 (7 bit)
access : read-write


ODDPKS1

USB ch.1 Odd Packet Size DMA Enable Register
address_offset : 0x14 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ODDPKS1 ODDPKS1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ODDPKS10 ODDPKS11 ODDPKS12 ODDPKS13 ODDPKS14

ODDPKS10 : If the transfer destination address of DMAC is USB.EP1DT, the bit width of the last transfer data is converted to Byte.
bits : 0 - -1 (0 bit)
access : read-write

ODDPKS11 : If the transfer destination address of DMAC is USB.EP2DT, the bit width of the last transfer data is converted to Byte.
bits : 1 - 0 (0 bit)
access : read-write

ODDPKS12 : If the transfer destination address of DMAC is USB.EP3DT, the bit width of the last transfer data is converted to Byte.
bits : 2 - 1 (0 bit)
access : read-write

ODDPKS13 : If the transfer destination address of DMAC is USB.EP4DT, the bit width of the last transfer data is converted to Byte.
bits : 3 - 2 (0 bit)
access : read-write

ODDPKS14 : If the transfer destination address of DMAC is USB.EP5DT, the bit width of the last transfer data is converted to Byte.
bits : 4 - 3 (0 bit)
access : read-write


EXC02MON

EXC02 batch read register
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EXC02MON EXC02MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NMI HWINT

NMI : Interrupt request of the NMIX external pin
bits : 0 - -1 (0 bit)
access : read-only

HWINT : Interrupt request of the hardware watchdog timer
bits : 1 - 0 (0 bit)
access : read-only


IRQ000MON

IRQ000 Batch Read Register
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ000MON IRQ000MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FCSINT

FCSINT : Interrupt request of the anomalous frequency detected by the CSV
bits : 0 - -1 (0 bit)
access : read-only


IRQ001MON

IRQ001 Batch Read Register
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ001MON IRQ001MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWWDTINT

SWWDTINT : interrupt request of the software watchdog timer
bits : 0 - -1 (0 bit)
access : read-only


IRQ002MON

IRQ002 Batch Read Register
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ002MON IRQ002MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LVDINT

LVDINT : Low-voltage detection (LVD) interrupt request
bits : 0 - -1 (0 bit)
access : read-only


IRQ003MON

IRQ003 Batch Read Register
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ003MON IRQ003MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRQBIT0 IRQBIT1 IRQBIT2 IRQBIT3 IRQBIT4 IRQBIT5 IRQBIT6 IRQBIT7

IRQBIT0 : interrupt request of the interrupt selected in bit0 of IRQ003SEL Register
bits : 0 - -1 (0 bit)
access : read-only

IRQBIT1 : interrupt request of the interrupt selected in bit1 of IRQ003SEL Register
bits : 1 - 0 (0 bit)
access : read-only

IRQBIT2 : interrupt request of the interrupt selected in bit2 of IRQ003SEL Register
bits : 2 - 1 (0 bit)
access : read-only

IRQBIT3 : interrupt request of the interrupt selected in bit3 of IRQ003SEL Register
bits : 3 - 2 (0 bit)
access : read-only

IRQBIT4 : interrupt request of the interrupt selected in bit4 of IRQ003SEL Register
bits : 4 - 3 (0 bit)
access : read-only

IRQBIT5 : interrupt request of the interrupt selected in bit5 of IRQ003SEL Register
bits : 5 - 4 (0 bit)
access : read-only

IRQBIT6 : interrupt request of the interrupt selected in bit6 of IRQ003SEL Register
bits : 6 - 5 (0 bit)
access : read-only

IRQBIT7 : interrupt request of the interrupt selected in bit7 of IRQ003SEL Register
bits : 7 - 6 (0 bit)
access : read-only


IRQ004MON

IRQ004 Batch Read Register
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ004MON IRQ004MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRQBIT0 IRQBIT1 IRQBIT2 IRQBIT3 IRQBIT4 IRQBIT5 IRQBIT6 IRQBIT7

IRQBIT0 : interrupt request of the interrupt selected in bit0 of IRQ004SEL Register
bits : 0 - -1 (0 bit)
access : read-only

IRQBIT1 : interrupt request of the interrupt selected in bit1 of IRQ004SEL Register
bits : 1 - 0 (0 bit)
access : read-only

IRQBIT2 : interrupt request of the interrupt selected in bit2 of IRQ004SEL Register
bits : 2 - 1 (0 bit)
access : read-only

IRQBIT3 : interrupt request of the interrupt selected in bit3 of IRQ004SEL Register
bits : 3 - 2 (0 bit)
access : read-only

IRQBIT4 : interrupt request of the interrupt selected in bit4 of IRQ004SEL Register
bits : 4 - 3 (0 bit)
access : read-only

IRQBIT5 : interrupt request of the interrupt selected in bit5 of IRQ004SEL Register
bits : 5 - 4 (0 bit)
access : read-only

IRQBIT6 : interrupt request of the interrupt selected in bit6 of IRQ004SEL Register
bits : 6 - 5 (0 bit)
access : read-only

IRQBIT7 : interrupt request of the interrupt selected in bit7 of IRQ004SEL Register
bits : 7 - 6 (0 bit)
access : read-only


IRQ005MON

IRQ005 Batch Read Register
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ005MON IRQ005MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRQBIT0 IRQBIT1 IRQBIT2 IRQBIT3 IRQBIT4 IRQBIT5 IRQBIT6 IRQBIT7

IRQBIT0 : interrupt request of the interrupt selected in bit0 of IRQ005SEL Register
bits : 0 - -1 (0 bit)
access : read-only

IRQBIT1 : interrupt request of the interrupt selected in bit1 of IRQ005SEL Register
bits : 1 - 0 (0 bit)
access : read-only

IRQBIT2 : interrupt request of the interrupt selected in bit2 of IRQ005SEL Register
bits : 2 - 1 (0 bit)
access : read-only

IRQBIT3 : interrupt request of the interrupt selected in bit3 of IRQ005SEL Register
bits : 3 - 2 (0 bit)
access : read-only

IRQBIT4 : interrupt request of the interrupt selected in bit4 of IRQ005SEL Register
bits : 4 - 3 (0 bit)
access : read-only

IRQBIT5 : interrupt request of the interrupt selected in bit5 of IRQ005SEL Register
bits : 5 - 4 (0 bit)
access : read-only

IRQBIT6 : interrupt request of the interrupt selected in bit6 of IRQ005SEL Register
bits : 6 - 5 (0 bit)
access : read-only

IRQBIT7 : interrupt request of the interrupt selected in bit7 of IRQ005SEL Register
bits : 7 - 6 (0 bit)
access : read-only


IRQ006MON

IRQ006 Batch Read Register
address_offset : 0x21C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ006MON IRQ006MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRQBIT0 IRQBIT1 IRQBIT2 IRQBIT3 IRQBIT4 IRQBIT5 IRQBIT6 IRQBIT7

IRQBIT0 : interrupt request of the interrupt selected in bit0 of IRQ006SEL Register
bits : 0 - -1 (0 bit)
access : read-only

IRQBIT1 : interrupt request of the interrupt selected in bit1 of IRQ006SEL Register
bits : 1 - 0 (0 bit)
access : read-only

IRQBIT2 : interrupt request of the interrupt selected in bit2 of IRQ006SEL Register
bits : 2 - 1 (0 bit)
access : read-only

IRQBIT3 : interrupt request of the interrupt selected in bit3 of IRQ006SEL Register
bits : 3 - 2 (0 bit)
access : read-only

IRQBIT4 : interrupt request of the interrupt selected in bit4 of IRQ006SEL Register
bits : 4 - 3 (0 bit)
access : read-only

IRQBIT5 : interrupt request of the interrupt selected in bit5 of IRQ006SEL Register
bits : 5 - 4 (0 bit)
access : read-only

IRQBIT6 : interrupt request of the interrupt selected in bit6 of IRQ006SEL Register
bits : 6 - 5 (0 bit)
access : read-only

IRQBIT7 : interrupt request of the interrupt selected in bit7 of IRQ006SEL Register
bits : 7 - 6 (0 bit)
access : read-only


IRQ007MON

IRQ007 Batch Read Register
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ007MON IRQ007MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRQBIT0 IRQBIT1 IRQBIT2 IRQBIT3 IRQBIT4 IRQBIT5 IRQBIT6 IRQBIT7

IRQBIT0 : interrupt request of the interrupt selected in bit0 of IRQ007SEL Register
bits : 0 - -1 (0 bit)
access : read-only

IRQBIT1 : interrupt request of the interrupt selected in bit1 of IRQ007SEL Register
bits : 1 - 0 (0 bit)
access : read-only

IRQBIT2 : interrupt request of the interrupt selected in bit2 of IRQ007SEL Register
bits : 2 - 1 (0 bit)
access : read-only

IRQBIT3 : interrupt request of the interrupt selected in bit3 of IRQ007SEL Register
bits : 3 - 2 (0 bit)
access : read-only

IRQBIT4 : interrupt request of the interrupt selected in bit4 of IRQ007SEL Register
bits : 4 - 3 (0 bit)
access : read-only

IRQBIT5 : interrupt request of the interrupt selected in bit5 of IRQ007SEL Register
bits : 5 - 4 (0 bit)
access : read-only

IRQBIT6 : interrupt request of the interrupt selected in bit6 of IRQ007SEL Register
bits : 6 - 5 (0 bit)
access : read-only

IRQBIT7 : interrupt request of the interrupt selected in bit7 of IRQ007SEL Register
bits : 7 - 6 (0 bit)
access : read-only


IRQ008MON

IRQ008 Batch Read Register
address_offset : 0x224 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ008MON IRQ008MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRQBIT0 IRQBIT1 IRQBIT2 IRQBIT3 IRQBIT4 IRQBIT5 IRQBIT6 IRQBIT7

IRQBIT0 : interrupt request of the interrupt selected in bit0 of IRQ008SEL Register
bits : 0 - -1 (0 bit)
access : read-only

IRQBIT1 : interrupt request of the interrupt selected in bit1 of IRQ008SEL Register
bits : 1 - 0 (0 bit)
access : read-only

IRQBIT2 : interrupt request of the interrupt selected in bit2 of IRQ008SEL Register
bits : 2 - 1 (0 bit)
access : read-only

IRQBIT3 : interrupt request of the interrupt selected in bit3 of IRQ008SEL Register
bits : 3 - 2 (0 bit)
access : read-only

IRQBIT4 : interrupt request of the interrupt selected in bit4 of IRQ008SEL Register
bits : 4 - 3 (0 bit)
access : read-only

IRQBIT5 : interrupt request of the interrupt selected in bit5 of IRQ008SEL Register
bits : 5 - 4 (0 bit)
access : read-only

IRQBIT6 : interrupt request of the interrupt selected in bit6 of IRQ008SEL Register
bits : 6 - 5 (0 bit)
access : read-only

IRQBIT7 : interrupt request of the interrupt selected in bit7 of IRQ008SEL Register
bits : 7 - 6 (0 bit)
access : read-only


IRQ009MON

IRQ009 Batch Read Register
address_offset : 0x228 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ009MON IRQ009MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRQBIT0 IRQBIT1 IRQBIT2 IRQBIT3 IRQBIT4 IRQBIT5 IRQBIT6 IRQBIT7

IRQBIT0 : interrupt request of the interrupt selected in bit0 of IRQ009SEL Register
bits : 0 - -1 (0 bit)
access : read-only

IRQBIT1 : interrupt request of the interrupt selected in bit1 of IRQ009SEL Register
bits : 1 - 0 (0 bit)
access : read-only

IRQBIT2 : interrupt request of the interrupt selected in bit2 of IRQ009SEL Register
bits : 2 - 1 (0 bit)
access : read-only

IRQBIT3 : interrupt request of the interrupt selected in bit3 of IRQ009SEL Register
bits : 3 - 2 (0 bit)
access : read-only

IRQBIT4 : interrupt request of the interrupt selected in bit4 of IRQ009SEL Register
bits : 4 - 3 (0 bit)
access : read-only

IRQBIT5 : interrupt request of the interrupt selected in bit5 of IRQ009SEL Register
bits : 5 - 4 (0 bit)
access : read-only

IRQBIT6 : interrupt request of the interrupt selected in bit6 of IRQ009SEL Register
bits : 6 - 5 (0 bit)
access : read-only

IRQBIT7 : interrupt request of the interrupt selected in bit7 of IRQ009SEL Register
bits : 7 - 6 (0 bit)
access : read-only


IRQ010MON

IRQ010 Batch Read Register
address_offset : 0x22C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ010MON IRQ010MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRQBIT0 IRQBIT1 IRQBIT2 IRQBIT3 IRQBIT4 IRQBIT5 IRQBIT6 IRQBIT7

IRQBIT0 : interrupt request of the interrupt selected in bit0 of IRQ010SEL Register
bits : 0 - -1 (0 bit)
access : read-only

IRQBIT1 : interrupt request of the interrupt selected in bit1 of IRQ010SEL Register
bits : 1 - 0 (0 bit)
access : read-only

IRQBIT2 : interrupt request of the interrupt selected in bit2 of IRQ010SEL Register
bits : 2 - 1 (0 bit)
access : read-only

IRQBIT3 : interrupt request of the interrupt selected in bit3 of IRQ010SEL Register
bits : 3 - 2 (0 bit)
access : read-only

IRQBIT4 : interrupt request of the interrupt selected in bit4 of IRQ010SEL Register
bits : 4 - 3 (0 bit)
access : read-only

IRQBIT5 : interrupt request of the interrupt selected in bit5 of IRQ010SEL Register
bits : 5 - 4 (0 bit)
access : read-only

IRQBIT6 : interrupt request of the interrupt selected in bit6 of IRQ010SEL Register
bits : 6 - 5 (0 bit)
access : read-only

IRQBIT7 : interrupt request of the interrupt selected in bit7 of IRQ010SEL Register
bits : 7 - 6 (0 bit)
access : read-only


IRQ011MON

IRQ011 Batch Read Register
address_offset : 0x230 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ011MON IRQ011MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTINT

EXTINT : Interrupt request of the external pin interrupt ch.0
bits : 0 - -1 (0 bit)
access : read-only


IRQ012MON

IRQ012 Batch Read Register
address_offset : 0x234 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ012MON IRQ012MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTINT

EXTINT : Interrupt request of the external pin interrupt ch.1
bits : 0 - -1 (0 bit)
access : read-only


IRQ013MON

IRQ013 Batch Read Register
address_offset : 0x238 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ013MON IRQ013MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTINT

EXTINT : Interrupt request of the external pin interrupt ch.2
bits : 0 - -1 (0 bit)
access : read-only


IRQ014MON

IRQ014 Batch Read Register
address_offset : 0x23C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ014MON IRQ014MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTINT

EXTINT : Interrupt request of the external pin interrupt ch.3
bits : 0 - -1 (0 bit)
access : read-only


IRQ015MON

IRQ015 Batch Read Register
address_offset : 0x240 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ015MON IRQ015MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTINT

EXTINT : Interrupt request of the external pin interrupt ch.4
bits : 0 - -1 (0 bit)
access : read-only


IRQ016MON

IRQ016 Batch Read Register
address_offset : 0x244 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ016MON IRQ016MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTINT

EXTINT : Interrupt request of the external pin interrupt ch.5
bits : 0 - -1 (0 bit)
access : read-only


IRQ017MON

IRQ017 Batch Read Register
address_offset : 0x248 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ017MON IRQ017MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTINT

EXTINT : Interrupt request of the external pin interrupt ch.6
bits : 0 - -1 (0 bit)
access : read-only


IRQ018MON

IRQ018 Batch Read Register
address_offset : 0x24C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ018MON IRQ018MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTINT

EXTINT : Interrupt request of the external pin interrupt ch.7
bits : 0 - -1 (0 bit)
access : read-only


IRQ019MON

IRQ019 Batch Read Register
address_offset : 0x250 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ019MON IRQ019MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QUDINT0 QUDINT1 QUDINT2 QUDINT3 QUDINT4 QUDINT5

QUDINT0 : PC match interrupt request of QPRC ch.0
bits : 0 - -1 (0 bit)
access : read-only

QUDINT1 : PC and RC match interrupt request of QPRC ch.0
bits : 1 - 0 (0 bit)
access : read-only

QUDINT2 : Overflow / underflow / zero index interrupt request of QPRC ch.0
bits : 2 - 1 (0 bit)
access : read-only

QUDINT3 : Count inversion interrupt request of QPRC ch.0
bits : 3 - 2 (0 bit)
access : read-only

QUDINT4 : Out-of-range interrupt request of QPRC ch.0QPRC ch.0
bits : 4 - 3 (0 bit)
access : read-only

QUDINT5 : PC match and RC match interrupt request of QPRC ch.0
bits : 5 - 4 (0 bit)
access : read-only


IRQ020MON

IRQ020 Batch Read Register
address_offset : 0x254 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ020MON IRQ020MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QUDINT0 QUDINT1 QUDINT2 QUDINT3 QUDINT4 QUDINT5

QUDINT0 : PC match interrupt request of QPRC ch.1
bits : 0 - -1 (0 bit)
access : read-only

QUDINT1 : PC and RC match interrupt request of QPRC ch.1
bits : 1 - 0 (0 bit)
access : read-only

QUDINT2 : Overflow / underflow / zero index interrupt request of QPRC ch.1
bits : 2 - 1 (0 bit)
access : read-only

QUDINT3 : Count inversion interrupt request of QPRC ch.1
bits : 3 - 2 (0 bit)
access : read-only

QUDINT4 : Out-of-range interrupt request of QPRC ch.1QPRC ch.1
bits : 4 - 3 (0 bit)
access : read-only

QUDINT5 : PC match and RC match interrupt request of QPRC ch.1
bits : 5 - 4 (0 bit)
access : read-only


IRQ021MON

IRQ021 Batch Read Register
address_offset : 0x258 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ021MON IRQ021MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WAVEINT0 WAVEINT1 WAVEINT2 WAVEINT3

WAVEINT0 : Interrupt request of the DTIF (motor emergency stop) of the MFT unit 0
bits : 0 - -1 (0 bit)
access : read-only

WAVEINT1 : Interrupt request of WFG timer 10 of the MFT unit 0
bits : 1 - 0 (0 bit)
access : read-only

WAVEINT2 : Interrupt request of WFG timer 32 of the MFT unit 0
bits : 2 - 1 (0 bit)
access : read-only

WAVEINT3 : Interrupt request of WFG timer 54 of the MFT unit 0
bits : 3 - 2 (0 bit)
access : read-only


IRQ022MON

IRQ022 Batch Read Register
address_offset : 0x25C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ022MON IRQ022MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WAVEINT0 WAVEINT1 WAVEINT2 WAVEINT3

WAVEINT0 : Interrupt request of the DTIF (motor emergency stop) of the MFT unit 1
bits : 0 - -1 (0 bit)
access : read-only

WAVEINT1 : Interrupt request of WFG timer 10 of the MFT unit 1
bits : 1 - 0 (0 bit)
access : read-only

WAVEINT2 : Interrupt request of WFG timer 32 of the MFT unit 1
bits : 2 - 1 (0 bit)
access : read-only

WAVEINT3 : Interrupt request of WFG timer 54 of the MFT unit 1
bits : 3 - 2 (0 bit)
access : read-only


IRQ023MON

IRQ023 Batch Read Register
address_offset : 0x260 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ023MON IRQ023MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WAVEINT0 WAVEINT1 WAVEINT2 WAVEINT3

WAVEINT0 : Interrupt request of the DTIF (motor emergency stop) of the MFT unit 2
bits : 0 - -1 (0 bit)
access : read-only

WAVEINT1 : Interrupt request of WFG timer 10 of the MFT unit 2
bits : 1 - 0 (0 bit)
access : read-only

WAVEINT2 : Interrupt request of WFG timer 32 of the MFT unit 2
bits : 2 - 1 (0 bit)
access : read-only

WAVEINT3 : Interrupt request of WFG timer 54 of the MFT unit 2
bits : 3 - 2 (0 bit)
access : read-only


IRQ024MON

IRQ024 Batch Read Register
address_offset : 0x264 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ024MON IRQ024MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRT_PEAK_INT0 FRT_PEAK_INT1 FRT_PEAK_INT2

FRT_PEAK_INT0 : FRT ch.0 peak value detection interrupt request of the MFT unit 0
bits : 0 - -1 (0 bit)
access : read-only

FRT_PEAK_INT1 : FRT ch.1 peak value detection interrupt request of the MFT unit 0
bits : 1 - 0 (0 bit)
access : read-only

FRT_PEAK_INT2 : FRT ch.2 peak value detection interrupt request of the MFT unit 0
bits : 2 - 1 (0 bit)
access : read-only


IRQ025MON

IRQ025 Batch Read Register
address_offset : 0x268 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ025MON IRQ025MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRT_ZERO_INT0 FRT_ZERO_INT1 FRT_ZERO_INT2

FRT_ZERO_INT0 : FRT ch.0 zero detection interrupt request of the MFT unit 0
bits : 0 - -1 (0 bit)
access : read-only

FRT_ZERO_INT1 : FRT ch.1 zero detection interrupt request of the MFT unit 0
bits : 1 - 0 (0 bit)
access : read-only

FRT_ZERO_INT2 : FRT ch.2 zero detection interrupt request of the MFT unit 0
bits : 2 - 1 (0 bit)
access : read-only


IRQ026MON

IRQ026 Batch Read Register
address_offset : 0x26C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ026MON IRQ026MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ICUINT0 ICUINT1 ICUINT2 ICUINT3

ICUINT0 : ICU ch.0 input edge detection interrupt request of the MFT unit 0
bits : 0 - -1 (0 bit)
access : read-only

ICUINT1 : ICU ch.1 input edge detection interrupt request of the MFT unit 0
bits : 1 - 0 (0 bit)
access : read-only

ICUINT2 : ICU ch.2 input edge detection interrupt request of the MFT unit 0
bits : 2 - 1 (0 bit)
access : read-only

ICUINT3 : ICU ch.3 input edge detection interrupt request of the MFT unit 0
bits : 3 - 2 (0 bit)
access : read-only


IRQ027MON

IRQ027 Batch Read Register
address_offset : 0x270 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ027MON IRQ027MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OCUINT0 OCUINT1 OCUINT2 OCUINT3 OCUINT4 OCUINT5

OCUINT0 : OCU ch.0 match detection interrupt request of the MFT unit 0
bits : 0 - -1 (0 bit)
access : read-only

OCUINT1 : OCU ch.1 match detection interrupt request of the MFT unit 0
bits : 1 - 0 (0 bit)
access : read-only

OCUINT2 : OCU ch.2 match detection interrupt request of the MFT unit 0
bits : 2 - 1 (0 bit)
access : read-only

OCUINT3 : OCU ch.3 match detection interrupt request of the MFT unit 0
bits : 3 - 2 (0 bit)
access : read-only

OCUINT4 : OCU ch.4 match detection interrupt request of the MFT unit 0
bits : 4 - 3 (0 bit)
access : read-only

OCUINT5 : OCU ch.5 match detection interrupt request of the MFT unit 0
bits : 5 - 4 (0 bit)
access : read-only


IRQ028MON

IRQ028 Batch Read Register
address_offset : 0x274 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ028MON IRQ028MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRT_PEAK_INT0 FRT_PEAK_INT1 FRT_PEAK_INT2

FRT_PEAK_INT0 : FRT ch.0 peak value detection interrupt request of the MFT unit 1
bits : 0 - -1 (0 bit)
access : read-only

FRT_PEAK_INT1 : FRT ch.1 peak value detection interrupt request of the MFT unit 1
bits : 1 - 0 (0 bit)
access : read-only

FRT_PEAK_INT2 : FRT ch.2 peak value detection interrupt request of the MFT unit 1
bits : 2 - 1 (0 bit)
access : read-only


IRQ029MON

IRQ029 Batch Read Register
address_offset : 0x278 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ029MON IRQ029MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRT_ZERO_INT0 FRT_ZERO_INT1 FRT_ZERO_INT2

FRT_ZERO_INT0 : FRT ch.0 zero detection interrupt request of the MFT unit 1
bits : 0 - -1 (0 bit)
access : read-only

FRT_ZERO_INT1 : FRT ch.1 zero detection interrupt request of the MFT unit 1
bits : 1 - 0 (0 bit)
access : read-only

FRT_ZERO_INT2 : FRT ch.2 zero detection interrupt request of the MFT unit 1
bits : 2 - 1 (0 bit)
access : read-only


IRQ030MON

IRQ030 Batch Read Register
address_offset : 0x27C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ030MON IRQ030MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ICUINT0 ICUINT1 ICUINT2 ICUINT3

ICUINT0 : ICU ch.0 input edge detection interrupt request of the MFT unit 1
bits : 0 - -1 (0 bit)
access : read-only

ICUINT1 : ICU ch.1 input edge detection interrupt request of the MFT unit 1
bits : 1 - 0 (0 bit)
access : read-only

ICUINT2 : ICU ch.2 input edge detection interrupt request of the MFT unit 1
bits : 2 - 1 (0 bit)
access : read-only

ICUINT3 : ICU ch.3 input edge detection interrupt request of the MFT unit 1
bits : 3 - 2 (0 bit)
access : read-only


IRQ031MON

IRQ031 Batch Read Register
address_offset : 0x280 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ031MON IRQ031MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OCUINT0 OCUINT1 OCUINT2 OCUINT3 OCUINT4 OCUINT5

OCUINT0 : OCU ch.0 match detection interrupt request of the MFT unit 1
bits : 0 - -1 (0 bit)
access : read-only

OCUINT1 : OCU ch.1 match detection interrupt request of the MFT unit 1
bits : 1 - 0 (0 bit)
access : read-only

OCUINT2 : OCU ch.2 match detection interrupt request of the MFT unit 1
bits : 2 - 1 (0 bit)
access : read-only

OCUINT3 : OCU ch.3 match detection interrupt request of the MFT unit 1
bits : 3 - 2 (0 bit)
access : read-only

OCUINT4 : OCU ch.4 match detection interrupt request of the MFT unit 1
bits : 4 - 3 (0 bit)
access : read-only

OCUINT5 : OCU ch.5 match detection interrupt request of the MFT unit 1
bits : 5 - 4 (0 bit)
access : read-only


IRQ032MON

IRQ032 Batch Read Register
address_offset : 0x284 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ032MON IRQ032MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRT_PEAK_INT0 FRT_PEAK_INT1 FRT_PEAK_INT2

FRT_PEAK_INT0 : FRT ch.0 peak value detection interrupt request of the MFT unit 2
bits : 0 - -1 (0 bit)
access : read-only

FRT_PEAK_INT1 : FRT ch.1 peak value detection interrupt request of the MFT unit 2
bits : 1 - 0 (0 bit)
access : read-only

FRT_PEAK_INT2 : FRT ch.2 peak value detection interrupt request of the MFT unit 2
bits : 2 - 1 (0 bit)
access : read-only


IRQ033MON

IRQ033 Batch Read Register
address_offset : 0x288 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ033MON IRQ033MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRT_ZERO_INT0 FRT_ZERO_INT1 FRT_ZERO_INT2

FRT_ZERO_INT0 : FRT ch.0 zero detection interrupt request of the MFT unit 2
bits : 0 - -1 (0 bit)
access : read-only

FRT_ZERO_INT1 : FRT ch.1 zero detection interrupt request of the MFT unit 2
bits : 1 - 0 (0 bit)
access : read-only

FRT_ZERO_INT2 : FRT ch.2 zero detection interrupt request of the MFT unit 2
bits : 2 - 1 (0 bit)
access : read-only


IRQ034MON

IRQ034 Batch Read Register
address_offset : 0x28C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ034MON IRQ034MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ICUINT0 ICUINT1 ICUINT2 ICUINT3

ICUINT0 : ICU ch.0 input edge detection interrupt request of the MFT unit 2
bits : 0 - -1 (0 bit)
access : read-only

ICUINT1 : ICU ch.1 input edge detection interrupt request of the MFT unit 2
bits : 1 - 0 (0 bit)
access : read-only

ICUINT2 : ICU ch.2 input edge detection interrupt request of the MFT unit 2
bits : 2 - 1 (0 bit)
access : read-only

ICUINT3 : ICU ch.3 input edge detection interrupt request of the MFT unit 2
bits : 3 - 2 (0 bit)
access : read-only


IRQ035MON

IRQ035 Batch Read Register
address_offset : 0x290 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ035MON IRQ035MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OCUINT0 OCUINT1 OCUINT2 OCUINT3 OCUINT4 OCUINT5

OCUINT0 : OCU ch.0 match detection interrupt request of the MFT unit 2
bits : 0 - -1 (0 bit)
access : read-only

OCUINT1 : OCU ch.1 match detection interrupt request of the MFT unit 2
bits : 1 - 0 (0 bit)
access : read-only

OCUINT2 : OCU ch.2 match detection interrupt request of the MFT unit 2
bits : 2 - 1 (0 bit)
access : read-only

OCUINT3 : OCU ch.3 match detection interrupt request of the MFT unit 2
bits : 3 - 2 (0 bit)
access : read-only

OCUINT4 : OCU ch.4 match detection interrupt request of the MFT unit 2
bits : 4 - 3 (0 bit)
access : read-only

OCUINT5 : OCU ch.5 match detection interrupt request of the MFT unit 2
bits : 5 - 4 (0 bit)
access : read-only


IRQ036MON

IRQ036 Batch Read Register
address_offset : 0x294 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ036MON IRQ036MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PPGINT0 PPGINT1 PPGINT2

PPGINT0 : Interrupt request of the PPG ch.0
bits : 0 - -1 (0 bit)
access : read-only

PPGINT1 : Interrupt request of the PPG ch.2
bits : 1 - 0 (0 bit)
access : read-only

PPGINT2 : Interrupt request of the PPG ch.4
bits : 2 - 1 (0 bit)
access : read-only


IRQ037MON

IRQ037 Batch Read Register
address_offset : 0x298 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ037MON IRQ037MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PPGINT0 PPGINT1 PPGINT2

PPGINT0 : Interrupt request of the PPG ch.8
bits : 0 - -1 (0 bit)
access : read-only

PPGINT1 : Interrupt request of the PPG ch.10
bits : 1 - 0 (0 bit)
access : read-only

PPGINT2 : Interrupt request of the PPG ch.12
bits : 2 - 1 (0 bit)
access : read-only


IRQ038MON

IRQ038 Batch Read Register
address_offset : 0x29C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ038MON IRQ038MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PPGINT0 PPGINT1 PPGINT2

PPGINT0 : Interrupt request of the PPG ch.16
bits : 0 - -1 (0 bit)
access : read-only

PPGINT1 : Interrupt request of the PPG ch.18
bits : 1 - 0 (0 bit)
access : read-only

PPGINT2 : Interrupt request of the PPG ch.20
bits : 2 - 1 (0 bit)
access : read-only


IRQ039MON

IRQ039 Batch Read Register
address_offset : 0x2A0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ039MON IRQ039MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BTINT0 BTINT1

BTINT0 : Interrupt request of source 0 (IRQ0) of the base timer ch.0
bits : 0 - -1 (0 bit)
access : read-only

BTINT1 : Interrupt request of source 1 (IRQ1) of the base timer ch.0
bits : 1 - 0 (0 bit)
access : read-only


IRQ040MON

IRQ040 Batch Read Register
address_offset : 0x2A4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ040MON IRQ040MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BTINT0 BTINT1

BTINT0 : Interrupt request of source 0 (IRQ0) of the base timer ch.1
bits : 0 - -1 (0 bit)
access : read-only

BTINT1 : Interrupt request of source 1 (IRQ1) of the base timer ch.1
bits : 1 - 0 (0 bit)
access : read-only


IRQ041MON

IRQ041 Batch Read Register
address_offset : 0x2A8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ041MON IRQ041MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BTINT0 BTINT1

BTINT0 : Interrupt request of source 0 (IRQ0) of the base timer ch.2
bits : 0 - -1 (0 bit)
access : read-only

BTINT1 : Interrupt request of source 1 (IRQ1) of the base timer ch.2
bits : 1 - 0 (0 bit)
access : read-only


IRQ042MON

IRQ042 Batch Read Register
address_offset : 0x2AC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ042MON IRQ042MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BTINT0 BTINT1

BTINT0 : Interrupt request of source 0 (IRQ0) of the base timer ch.3
bits : 0 - -1 (0 bit)
access : read-only

BTINT1 : Interrupt request of source 1 (IRQ1) of the base timer ch.3
bits : 1 - 0 (0 bit)
access : read-only


IRQ043MON

IRQ043 Batch Read Register
address_offset : 0x2B0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ043MON IRQ043MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BTINT0 BTINT1

BTINT0 : Interrupt request of source 0 (IRQ0) of the base timer ch.4
bits : 0 - -1 (0 bit)
access : read-only

BTINT1 : Interrupt request of source 1 (IRQ1) of the base timer ch.4
bits : 1 - 0 (0 bit)
access : read-only


IRQ044MON

IRQ044 Batch Read Register
address_offset : 0x2B4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ044MON IRQ044MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BTINT0 BTINT1

BTINT0 : Interrupt request of source 0 (IRQ0) of the base timer ch.5
bits : 0 - -1 (0 bit)
access : read-only

BTINT1 : Interrupt request of source 1 (IRQ1) of the base timer ch.5
bits : 1 - 0 (0 bit)
access : read-only


IRQ045MON

IRQ045 Batch Read Register
address_offset : 0x2B8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ045MON IRQ045MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BTINT0 BTINT1

BTINT0 : Interrupt request of source 0 (IRQ0) of the base timer ch.6
bits : 0 - -1 (0 bit)
access : read-only

BTINT1 : Interrupt request of source 1 (IRQ1) of the base timer ch.6
bits : 1 - 0 (0 bit)
access : read-only


IRQ046MON

IRQ046 Batch Read Register
address_offset : 0x2BC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ046MON IRQ046MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BTINT0 BTINT1

BTINT0 : Interrupt request of source 0 (IRQ0) of the base timer ch.7
bits : 0 - -1 (0 bit)
access : read-only

BTINT1 : Interrupt request of source 1 (IRQ1) of the base timer ch.7
bits : 1 - 0 (0 bit)
access : read-only


IRQ047MON

IRQ047 Batch Read Register
address_offset : 0x2C0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ047MON IRQ047MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMINT1 TIMINT2

TIMINT1 : Dual timer TIMINT1 interrupt request
bits : 0 - -1 (0 bit)
access : read-only

TIMINT2 : Dual timer TIMINT2 interrupt request
bits : 1 - 0 (0 bit)
access : read-only


IRQ048MON

IRQ048 Batch Read Register
address_offset : 0x2C4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ048MON IRQ048MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WCINT

WCINT : Interrupt request of the watch counter
bits : 0 - -1 (0 bit)
access : read-only


IRQ049MON

IRQ049 Batch Read Register
address_offset : 0x2C8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ049MON IRQ049MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BMEMCS

BMEMCS : External bus output error interrupt request
bits : 0 - -1 (0 bit)
access : read-only


IRQ050MON

IRQ050 Batch Read Register
address_offset : 0x2CC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ050MON IRQ050MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RTCINT

RTCINT : Interrupt request of the RTC$
bits : 0 - -1 (0 bit)
access : read-only


IRQ051MON

IRQ051 Batch Read Register
address_offset : 0x2D0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ051MON IRQ051MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTINT

EXTINT : Interrupt request of the external pin interrupt ch.8
bits : 0 - -1 (0 bit)
access : read-only


IRQ052MON

IRQ052 Batch Read Register
address_offset : 0x2D4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ052MON IRQ052MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTINT

EXTINT : Interrupt request of the external pin interrupt ch.9
bits : 0 - -1 (0 bit)
access : read-only


IRQ053MON

IRQ053 Batch Read Register
address_offset : 0x2D8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ053MON IRQ053MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTINT

EXTINT : Interrupt request of the external pin interrupt ch.10
bits : 0 - -1 (0 bit)
access : read-only


IRQ054MON

IRQ054 Batch Read Register
address_offset : 0x2DC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ054MON IRQ054MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTINT

EXTINT : Interrupt request of the external pin interrupt ch.11
bits : 0 - -1 (0 bit)
access : read-only


IRQ055MON

IRQ055 Batch Read Register
address_offset : 0x2E0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ055MON IRQ055MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTINT

EXTINT : Interrupt request of the external pin interrupt ch.12
bits : 0 - -1 (0 bit)
access : read-only


IRQ056MON

IRQ056 Batch Read Register
address_offset : 0x2E4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ056MON IRQ056MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTINT

EXTINT : Interrupt request of the external pin interrupt ch.13
bits : 0 - -1 (0 bit)
access : read-only


IRQ057MON

IRQ057 Batch Read Register
address_offset : 0x2E8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ057MON IRQ057MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTINT

EXTINT : Interrupt request of the external pin interrupt ch.14
bits : 0 - -1 (0 bit)
access : read-only


IRQ058MON

IRQ058 Batch Read Register
address_offset : 0x2EC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ058MON IRQ058MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTINT

EXTINT : Interrupt request of the external pin interrupt ch.15
bits : 0 - -1 (0 bit)
access : read-only


IRQ059MON

IRQ059 Batch Read Register
address_offset : 0x2F0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ059MON IRQ059MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MOSCINT SOSCINT MPLLINT UPLLINT IPLLINT

MOSCINT : Main clock oscillation stabilization wait completion interrupt
bits : 0 - -1 (0 bit)
access : read-only

SOSCINT : Sub clock oscillation stabilization wait completion interrupt
bits : 1 - 0 (0 bit)
access : read-only

MPLLINT : Main PLL oscillation stabilization wait completion interrupt
bits : 2 - 1 (0 bit)
access : read-only

UPLLINT : PLL of USB / Ethernet oscillation stabilization wait completion interrupt
bits : 3 - 2 (0 bit)
access : read-only

IPLLINT : PLL of I2S oscillation stabilization wait completion interrupt
bits : 4 - 3 (0 bit)
access : read-only


IRQ060MON

IRQ060 Batch Read Register
address_offset : 0x2F4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ060MON IRQ060MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFSRINT

MFSRINT : Reception interrupt request of the MFS ch.0
bits : 0 - -1 (0 bit)
access : read-only


IRQ061MON

IRQ061 Batch Read Register
address_offset : 0x2F8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ061MON IRQ061MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFSINT0 MFSINT1

MFSINT0 : Transmission interrupt request of the MFS ch.0
bits : 0 - -1 (0 bit)
access : read-only

MFSINT1 : Status interrupt request of the MFS ch.0
bits : 1 - 0 (0 bit)
access : read-only


IRQ062MON

IRQ062 Batch Read Register
address_offset : 0x2FC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ062MON IRQ062MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFSRINT

MFSRINT : Reception interrupt request of the MFS ch.1
bits : 0 - -1 (0 bit)
access : read-only


IRQ063MON

IRQ063 Batch Read Register
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ063MON IRQ063MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFSINT0 MFSINT1

MFSINT0 : Transmission interrupt request of the MFS ch.1
bits : 0 - -1 (0 bit)
access : read-only

MFSINT1 : Status interrupt request of the MFS ch.1
bits : 1 - 0 (0 bit)
access : read-only


IRQ064MON

IRQ064 Batch Read Register
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ064MON IRQ064MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFSRINT

MFSRINT : Reception interrupt request of the MFS ch.2
bits : 0 - -1 (0 bit)
access : read-only


IRQ065MON

IRQ065 Batch Read Register
address_offset : 0x308 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ065MON IRQ065MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFSINT0 MFSINT1

MFSINT0 : Transmission interrupt request of the MFS ch.2
bits : 0 - -1 (0 bit)
access : read-only

MFSINT1 : Status interrupt request of the MFS ch.2
bits : 1 - 0 (0 bit)
access : read-only


IRQ066MON

IRQ066 Batch Read Register
address_offset : 0x30C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ066MON IRQ066MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFSRINT

MFSRINT : Reception interrupt request of the MFS ch.3
bits : 0 - -1 (0 bit)
access : read-only


IRQ067MON

IRQ067 Batch Read Register
address_offset : 0x310 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ067MON IRQ067MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFSINT0 MFSINT1

MFSINT0 : Transmission interrupt request of the MFS ch.3
bits : 0 - -1 (0 bit)
access : read-only

MFSINT1 : Status interrupt request of the MFS ch.3
bits : 1 - 0 (0 bit)
access : read-only


IRQ068MON

IRQ068 Batch Read Register
address_offset : 0x314 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ068MON IRQ068MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFSRINT

MFSRINT : Reception interrupt request of the MFS ch.4
bits : 0 - -1 (0 bit)
access : read-only


IRQ069MON

IRQ069 Batch Read Register
address_offset : 0x318 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ069MON IRQ069MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFSINT0 MFSINT1

MFSINT0 : Transmission interrupt request of the MFS ch.4
bits : 0 - -1 (0 bit)
access : read-only

MFSINT1 : Status interrupt request of the MFS ch.4
bits : 1 - 0 (0 bit)
access : read-only


IRQ070MON

IRQ070 Batch Read Register
address_offset : 0x31C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ070MON IRQ070MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFSRINT

MFSRINT : Reception interrupt request of the MFS ch.5
bits : 0 - -1 (0 bit)
access : read-only


IRQ071MON

IRQ071 Batch Read Register
address_offset : 0x320 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ071MON IRQ071MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFSINT0 MFSINT1

MFSINT0 : Transmission interrupt request of the MFS ch.5
bits : 0 - -1 (0 bit)
access : read-only

MFSINT1 : Status interrupt request of the MFS ch.5
bits : 1 - 0 (0 bit)
access : read-only


IRQ072MON

IRQ072 Batch Read Register
address_offset : 0x324 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ072MON IRQ072MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFSRINT

MFSRINT : Reception interrupt request of the MFS ch.6
bits : 0 - -1 (0 bit)
access : read-only


IRQ073MON

IRQ073 Batch Read Register
address_offset : 0x328 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ073MON IRQ073MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFSINT0 MFSINT1

MFSINT0 : Transmission interrupt request of the MFS ch.6
bits : 0 - -1 (0 bit)
access : read-only

MFSINT1 : Status interrupt request of the MFS ch.6
bits : 1 - 0 (0 bit)
access : read-only


IRQ074MON

IRQ074 Batch Read Register
address_offset : 0x32C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ074MON IRQ074MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFSRINT

MFSRINT : Reception interrupt request of the MFS ch.7
bits : 0 - -1 (0 bit)
access : read-only


IRQ075MON

IRQ075 Batch Read Register
address_offset : 0x330 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ075MON IRQ075MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFSINT0 MFSINT1

MFSINT0 : Transmission interrupt request of the MFS ch.7
bits : 0 - -1 (0 bit)
access : read-only

MFSINT1 : Status interrupt request of the MFS ch.7
bits : 1 - 0 (0 bit)
access : read-only


IRQ076MON

IRQ076 Batch Read Register
address_offset : 0x334 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ076MON IRQ076MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADCINT0 ADCINT1 ADCINT2 ADCINT3 ADCINT4

ADCINT0 : Priority conversion interrupt request of the A/D converter unit 0
bits : 0 - -1 (0 bit)
access : read-only

ADCINT1 : Scan conversion interrupt request of the A/D converter unit 0
bits : 1 - 0 (0 bit)
access : read-only

ADCINT2 : FIFO overrun interrupt request of the A/D converter unit 0
bits : 2 - 1 (0 bit)
access : read-only

ADCINT3 : Conversion result comparison interrupt request of the A/D converter unit 0
bits : 3 - 2 (0 bit)
access : read-only

ADCINT4 : Range comparison result interrupt request of the A/D converter unit 0
bits : 4 - 3 (0 bit)
access : read-only


IRQ077MON

IRQ077 Batch Read Register
address_offset : 0x338 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ077MON IRQ077MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADCINT0 ADCINT1 ADCINT2 ADCINT3 ADCINT4

ADCINT0 : Priority conversion interrupt request of the A/D converter unit 1
bits : 0 - -1 (0 bit)
access : read-only

ADCINT1 : Scan conversion interrupt request of the A/D converter unit 1
bits : 1 - 0 (0 bit)
access : read-only

ADCINT2 : FIFO overrun interrupt request of the A/D converter unit 1
bits : 2 - 1 (0 bit)
access : read-only

ADCINT3 : Conversion result comparison interrupt request of the A/D converter unit 1
bits : 3 - 2 (0 bit)
access : read-only

ADCINT4 : Range comparison result interrupt request of the A/D converter unit 1
bits : 4 - 3 (0 bit)
access : read-only


IRQ078MON

IRQ078 Batch Read Register
address_offset : 0x33C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ078MON IRQ078MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_DRQ_INT0 USB_DRQ_INT1 USB_DRQ_INT2 USB_DRQ_INT3 USB_DRQ_INT4

USB_DRQ_INT0 : Endpoint 1 DRQ interrupt request of the USB ch.0
bits : 0 - -1 (0 bit)
access : read-only

USB_DRQ_INT1 : Endpoint 2 DRQ interrupt request of the USB ch.0
bits : 1 - 0 (0 bit)
access : read-only

USB_DRQ_INT2 : Endpoint 3 DRQ interrupt request of the USB ch.0
bits : 2 - 1 (0 bit)
access : read-only

USB_DRQ_INT3 : Endpoint 4 DRQ interrupt request of the USB ch.0
bits : 3 - 2 (0 bit)
access : read-only

USB_DRQ_INT4 : Endpoint 5 DRQ interrupt request of the USB ch.0
bits : 4 - 3 (0 bit)
access : read-only


IRQ079MON

IRQ079 Batch Read Register
address_offset : 0x340 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ079MON IRQ079MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_INT0 USB_INT1 USB_INT2 USB_INT3 USB_INT4 USB_INT5

USB_INT0 : Endpoint 0 DRQI interrupt request of the USB ch.0
bits : 0 - -1 (0 bit)
access : read-only

USB_INT1 : Endpoint 0 DRQO interrupt request of the USB ch.0
bits : 1 - 0 (0 bit)
access : read-only

USB_INT2 : SUSP/SOF/BRST/CONF/WKUP interrupt request of the USB ch.0
bits : 2 - 1 (0 bit)
access : read-only

USB_INT3 : SPK interrupt request of the USB ch.0
bits : 3 - 2 (0 bit)
access : read-only

USB_INT4 : DIRQ/URPIRQ/RWKIRQ/CNNIRQ interrupt request of the USB ch.0
bits : 4 - 3 (0 bit)
access : read-only

USB_INT5 : SOFIRQ/CMPIRQ interrupt request of the USB ch.0
bits : 5 - 4 (0 bit)
access : read-only


IRQ080MON

IRQ080 Batch Read Register
address_offset : 0x344 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ080MON IRQ080MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CANINT

CANINT : Interrupt request of the CAN ch.0
bits : 0 - -1 (0 bit)
access : read-only


IRQ081MON

IRQ081 Batch Read Register
address_offset : 0x348 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ081MON IRQ081MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CANINT CANDEINT CANSEINT CAN0INT CAN1INT

CANINT : Interrupt request of the CAN ch.1
bits : 0 - -1 (0 bit)
access : read-only

CANDEINT : Double bit error interrupt request of the CAN-FD
bits : 1 - 0 (0 bit)
access : read-only

CANSEINT : Single bit error interrupt request of the CAN-FD
bits : 2 - 1 (0 bit)
access : read-only

CAN0INT : CAN-FD 0 interrupt request
bits : 3 - 2 (0 bit)
access : read-only

CAN1INT : CAN-FD 1 interrupt request
bits : 4 - 3 (0 bit)
access : read-only


IRQ082MON

IRQ082 Batch Read Register
address_offset : 0x34C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ082MON IRQ082MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MACSBD MACPMT MACLPI

MACSBD : SBD interrupt request of the Ethernet MAC
bits : 0 - -1 (0 bit)
access : read-only

MACPMT : PMT interrupt request of the Ethernet MAC
bits : 1 - 0 (0 bit)
access : read-only

MACLPI : LPI interrupt request of the Ethernet MAC
bits : 2 - 1 (0 bit)
access : read-only


IRQ083MON

IRQ083 Batch Read Register
address_offset : 0x350 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ083MON IRQ083MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMACINT

DMACINT : Interrupt request of the DMAC ch.0
bits : 0 - -1 (0 bit)
access : read-only


IRQ084MON

IRQ084 Batch Read Register
address_offset : 0x354 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ084MON IRQ084MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMACINT

DMACINT : Interrupt request of the DMAC ch.1
bits : 0 - -1 (0 bit)
access : read-only


IRQ085MON

IRQ085 Batch Read Register
address_offset : 0x358 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ085MON IRQ085MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMACINT

DMACINT : Interrupt request of the DMAC ch.2
bits : 0 - -1 (0 bit)
access : read-only


IRQ086MON

IRQ086 Batch Read Register
address_offset : 0x35C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ086MON IRQ086MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMACINT

DMACINT : Interrupt request of the DMAC ch.3
bits : 0 - -1 (0 bit)
access : read-only


IRQ087MON

IRQ087 Batch Read Register
address_offset : 0x360 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ087MON IRQ087MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMACINT

DMACINT : Interrupt request of the DMAC ch.4
bits : 0 - -1 (0 bit)
access : read-only


IRQ088MON

IRQ088 Batch Read Register
address_offset : 0x364 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ088MON IRQ088MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMACINT

DMACINT : Interrupt request of the DMAC ch.5
bits : 0 - -1 (0 bit)
access : read-only


IRQ089MON

IRQ089 Batch Read Register
address_offset : 0x368 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ089MON IRQ089MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMACINT

DMACINT : Interrupt request of the DMAC ch.6
bits : 0 - -1 (0 bit)
access : read-only


IRQ090MON

IRQ090 Batch Read Register
address_offset : 0x36C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ090MON IRQ090MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMACINT

DMACINT : Interrupt request of the DMAC ch.7
bits : 0 - -1 (0 bit)
access : read-only


IRQ091MON

IRQ091 Batch Read Register
address_offset : 0x370 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ091MON IRQ091MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSTCINT0 DSTCINT1

DSTCINT0 : DSTC SWINT interrupt request
bits : 0 - -1 (0 bit)
access : read-only

DSTCINT1 : DSTC ERINT interrupt request
bits : 1 - 0 (0 bit)
access : read-only


IRQ092MON

IRQ092 Batch Read Register
address_offset : 0x374 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ092MON IRQ092MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTINT0 EXTINT1 EXTINT2 EXTINT3

EXTINT0 : Interrupt request of the external pin interrupt ch.16
bits : 0 - -1 (0 bit)
access : read-only

EXTINT1 : Interrupt request of the external pin interrupt ch.17
bits : 1 - 0 (0 bit)
access : read-only

EXTINT2 : Interrupt request of the external pin interrupt ch.18
bits : 2 - 1 (0 bit)
access : read-only

EXTINT3 : Interrupt request of the external pin interrupt ch.19
bits : 3 - 2 (0 bit)
access : read-only


IRQ093MON

IRQ093 Batch Read Register
address_offset : 0x378 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ093MON IRQ093MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTINT0 EXTINT1 EXTINT2 EXTINT3

EXTINT0 : Interrupt request of the external pin interrupt ch.20
bits : 0 - -1 (0 bit)
access : read-only

EXTINT1 : Interrupt request of the external pin interrupt ch.21
bits : 1 - 0 (0 bit)
access : read-only

EXTINT2 : Interrupt request of the external pin interrupt ch.22
bits : 2 - 1 (0 bit)
access : read-only

EXTINT3 : Interrupt request of the external pin interrupt ch.23
bits : 3 - 2 (0 bit)
access : read-only


IRQ094MON

IRQ094 Batch Read Register
address_offset : 0x37C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ094MON IRQ094MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTINT0 EXTINT1 EXTINT2 EXTINT3

EXTINT0 : Interrupt request of the external pin interrupt ch.24
bits : 0 - -1 (0 bit)
access : read-only

EXTINT1 : Interrupt request of the external pin interrupt ch.25
bits : 1 - 0 (0 bit)
access : read-only

EXTINT2 : Interrupt request of the external pin interrupt ch.26
bits : 2 - 1 (0 bit)
access : read-only

EXTINT3 : Interrupt request of the external pin interrupt ch.27
bits : 3 - 2 (0 bit)
access : read-only


IRQ095MON

IRQ095 Batch Read Register
address_offset : 0x380 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ095MON IRQ095MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTINT0 EXTINT1 EXTINT2 EXTINT3

EXTINT0 : Interrupt request of the external pin interrupt ch.28
bits : 0 - -1 (0 bit)
access : read-only

EXTINT1 : Interrupt request of the external pin interrupt ch.29
bits : 1 - 0 (0 bit)
access : read-only

EXTINT2 : Interrupt request of the external pin interrupt ch.30
bits : 2 - 1 (0 bit)
access : read-only

EXTINT3 : Interrupt request of the external pin interrupt ch.31
bits : 3 - 2 (0 bit)
access : read-only


IRQ096MON

IRQ096 Batch Read Register
address_offset : 0x384 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ096MON IRQ096MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QUDINT0 QUDINT1 QUDINT2 QUDINT3 QUDINT4 QUDINT5

QUDINT0 : PC match interrupt request of QPRC ch.2
bits : 0 - -1 (0 bit)
access : read-only

QUDINT1 : PC and RC match interrupt request of QPRC ch.2
bits : 1 - 0 (0 bit)
access : read-only

QUDINT2 : Overflow / underflow / zero index interrupt request of QPRC ch.2
bits : 2 - 1 (0 bit)
access : read-only

QUDINT3 : Count inversion interrupt request of QPRC ch.2
bits : 3 - 2 (0 bit)
access : read-only

QUDINT4 : Out-of-range interrupt request of QPRC ch.2QPRC ch.2
bits : 4 - 3 (0 bit)
access : read-only

QUDINT5 : PC match and RC match interrupt request of QPRC ch.2
bits : 5 - 4 (0 bit)
access : read-only


IRQ097MON

IRQ097 Batch Read Register
address_offset : 0x388 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ097MON IRQ097MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QUDINT0 QUDINT1 QUDINT2 QUDINT3 QUDINT4 QUDINT5

QUDINT0 : PC match interrupt request of QPRC ch.3
bits : 0 - -1 (0 bit)
access : read-only

QUDINT1 : PC and RC match interrupt request of QPRC ch.3
bits : 1 - 0 (0 bit)
access : read-only

QUDINT2 : Overflow / underflow / zero index interrupt request of QPRC ch.3
bits : 2 - 1 (0 bit)
access : read-only

QUDINT3 : Count inversion interrupt request of QPRC ch.3
bits : 3 - 2 (0 bit)
access : read-only

QUDINT4 : Out-of-range interrupt request of QPRC ch.3QPRC ch.3
bits : 4 - 3 (0 bit)
access : read-only

QUDINT5 : PC match and RC match interrupt request of QPRC ch.3
bits : 5 - 4 (0 bit)
access : read-only


IRQ098MON

IRQ098 Batch Read Register
address_offset : 0x38C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ098MON IRQ098MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BTINT0 BTINT1

BTINT0 : Interrupt request of source 0 (IRQ0) of the base timer ch.8
bits : 0 - -1 (0 bit)
access : read-only

BTINT1 : Interrupt request of source 1 (IRQ1) of the base timer ch.8
bits : 1 - 0 (0 bit)
access : read-only


IRQ099MON

IRQ099 Batch Read Register
address_offset : 0x390 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ099MON IRQ099MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BTINT0 BTINT1

BTINT0 : Interrupt request of source 0 (IRQ0) of the base timer ch.9
bits : 0 - -1 (0 bit)
access : read-only

BTINT1 : Interrupt request of source 1 (IRQ1) of the base timer ch.9
bits : 1 - 0 (0 bit)
access : read-only


IRQ100MON

IRQ100 Batch Read Register
address_offset : 0x394 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ100MON IRQ100MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BTINT0 BTINT1

BTINT0 : Interrupt request of source 0 (IRQ0) of the base timer ch.10
bits : 0 - -1 (0 bit)
access : read-only

BTINT1 : Interrupt request of source 1 (IRQ1) of the base timer ch.10
bits : 1 - 0 (0 bit)
access : read-only


IRQ101MON

IRQ101 Batch Read Register
address_offset : 0x398 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ101MON IRQ101MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BTINT0 BTINT1

BTINT0 : Interrupt request of source 0 (IRQ0) of the base timer ch.11
bits : 0 - -1 (0 bit)
access : read-only

BTINT1 : Interrupt request of source 1 (IRQ1) of the base timer ch.11
bits : 1 - 0 (0 bit)
access : read-only


IRQ102MON

IRQ102 Batch Read Register
address_offset : 0x39C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ102MON IRQ102MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BTINT0 BTINT1 BTINT2 BTINT3 BTINT4 BTINT5 BTINT6 BTINT7

BTINT0 : Interrupt request of source 0 (IRQ0) of the base timer ch.12
bits : 0 - -1 (0 bit)
access : read-only

BTINT1 : Interrupt request of source 1 (IRQ1) of the base timer ch.12
bits : 1 - 0 (0 bit)
access : read-only

BTINT2 : Interrupt request of source 0 (IRQ0) of the base timer ch.13
bits : 2 - 1 (0 bit)
access : read-only

BTINT3 : Interrupt request of source 1 (IRQ1) of the base timer ch.13
bits : 3 - 2 (0 bit)
access : read-only

BTINT4 : Interrupt request of source 0 (IRQ0) of the base timer ch.14
bits : 4 - 3 (0 bit)
access : read-only

BTINT5 : Interrupt request of source 1 (IRQ1) of the base timer ch.14
bits : 5 - 4 (0 bit)
access : read-only

BTINT6 : Interrupt request of source 0 (IRQ0) of the base timer ch.15
bits : 6 - 5 (0 bit)
access : read-only

BTINT7 : Interrupt request of source 1 (IRQ1) of the base timer ch.15
bits : 7 - 6 (0 bit)
access : read-only


IRQ103MON

IRQ103 Batch Read Register
address_offset : 0x3A0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ103MON IRQ103MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFSRINT

MFSRINT : Reception interrupt request of the MFS ch.8
bits : 0 - -1 (0 bit)
access : read-only


IRQ104MON

IRQ104 Batch Read Register
address_offset : 0x3A4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ104MON IRQ104MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFSINT0 MFSINT1

MFSINT0 : Transmission interrupt request of the MFS ch.8
bits : 0 - -1 (0 bit)
access : read-only

MFSINT1 : Status interrupt request of the MFS ch.8
bits : 1 - 0 (0 bit)
access : read-only


IRQ105MON

IRQ105 Batch Read Register
address_offset : 0x3A8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ105MON IRQ105MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFSRINT

MFSRINT : Reception interrupt request of the MFS ch.9
bits : 0 - -1 (0 bit)
access : read-only


IRQ106MON

IRQ106 Batch Read Register
address_offset : 0x3AC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ106MON IRQ106MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFSINT0 MFSINT1

MFSINT0 : Transmission interrupt request of the MFS ch.9
bits : 0 - -1 (0 bit)
access : read-only

MFSINT1 : Status interrupt request of the MFS ch.9
bits : 1 - 0 (0 bit)
access : read-only


IRQ107MON

IRQ107 Batch Read Register
address_offset : 0x3B0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ107MON IRQ107MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFSRINT

MFSRINT : Reception interrupt request of the MFS ch.10
bits : 0 - -1 (0 bit)
access : read-only


IRQ108MON

IRQ108 Batch Read Register
address_offset : 0x3B4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ108MON IRQ108MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFSINT0 MFSINT1

MFSINT0 : Transmission interrupt request of the MFS ch.10
bits : 0 - -1 (0 bit)
access : read-only

MFSINT1 : Status interrupt request of the MFS ch.10
bits : 1 - 0 (0 bit)
access : read-only


IRQ109MON

IRQ109 Batch Read Register
address_offset : 0x3B8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ109MON IRQ109MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFSRINT

MFSRINT : Reception interrupt request of the MFS ch.11
bits : 0 - -1 (0 bit)
access : read-only


IRQ110MON

IRQ110 Batch Read Register
address_offset : 0x3BC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ110MON IRQ110MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFSINT0 MFSINT1

MFSINT0 : Transmission interrupt request of the MFS ch.11
bits : 0 - -1 (0 bit)
access : read-only

MFSINT1 : Status interrupt request of the MFS ch.11
bits : 1 - 0 (0 bit)
access : read-only


IRQ111MON

IRQ111 Batch Read Register
address_offset : 0x3C0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ111MON IRQ111MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADCINT0 ADCINT1 ADCINT2 ADCINT3 ADCINT4

ADCINT0 : Priority conversion interrupt request of the A/D converter unit 2
bits : 0 - -1 (0 bit)
access : read-only

ADCINT1 : Scan conversion interrupt request of the A/D converter unit 2
bits : 1 - 0 (0 bit)
access : read-only

ADCINT2 : FIFO overrun interrupt request of the A/D converter unit 2
bits : 2 - 1 (0 bit)
access : read-only

ADCINT3 : Conversion result comparison interrupt request of the A/D converter unit 2
bits : 3 - 2 (0 bit)
access : read-only

ADCINT4 : Range comparison result interrupt request of the A/D converter unit 2
bits : 4 - 3 (0 bit)
access : read-only


IRQ112MON

IRQ112 Batch Read Register
address_offset : 0x3C4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ112MON IRQ112MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2SDINT0 I2SDINT1 QSPIDINT0 QSPIDINT1 PCRCDINT CANDINT

I2SDINT0 : Interrupt request of DSTC transfer end interrupt of I2S(reception)
bits : 0 - -1 (0 bit)
access : read-only

I2SDINT1 : Interrupt request of DSTC transfer end interrupt of I2S(transmission)
bits : 1 - 0 (0 bit)
access : read-only

QSPIDINT0 : Interrupt request of DSTC transfer end interrupt of Quad SPI(reception)
bits : 2 - 1 (0 bit)
access : read-only

QSPIDINT1 : Interrupt request of DSTC transfer end interrupt of Quad SPI(transmission)
bits : 3 - 2 (0 bit)
access : read-only

PCRCDINT : Interrupt request of DSTC transfer end interrupt of Programmable CRC
bits : 4 - 3 (0 bit)
access : read-only

CANDINT : Interrupt request of DSTC transfer end interrupt of CAN-FD
bits : 5 - 4 (0 bit)
access : read-only


IRQ113MON

IRQ113 Batch Read Register
address_offset : 0x3C8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ113MON IRQ113MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_DRQ_INT0 USB_DRQ_INT1 USB_DRQ_INT2 USB_DRQ_INT3 USB_DRQ_INT4 RCEC0INT

USB_DRQ_INT0 : ERROR!!!!!!!!!!!!!!!!!!!!
bits : 0 - -1 (0 bit)
access : read-only

USB_DRQ_INT1 : ERROR!!!!!!!!!!!!!!!!!!!!
bits : 1 - 0 (0 bit)
access : read-only

USB_DRQ_INT2 : ERROR!!!!!!!!!!!!!!!!!!!!
bits : 2 - 1 (0 bit)
access : read-only

USB_DRQ_INT3 : ERROR!!!!!!!!!!!!!!!!!!!!
bits : 3 - 2 (0 bit)
access : read-only

USB_DRQ_INT4 : ERROR!!!!!!!!!!!!!!!!!!!!
bits : 4 - 3 (0 bit)
access : read-only

RCEC0INT : ERROR!!!!!!!!!!!!!!!!!!!!
bits : 5 - 4 (0 bit)
access : read-only


IRQ114MON

ERROR!!!!!!!!!!!!!!!!!!!!
address_offset : 0x3CC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ114MON IRQ114MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_INT0 USB_INT1 USB_INT2 USB_INT3 USB_INT4 USB_INT5 RCEC1INT

USB_INT0 : ERROR!!!!!!!!!!!!!!!!!!!!
bits : 0 - -1 (0 bit)
access : read-only

USB_INT1 : ERROR!!!!!!!!!!!!!!!!!!!!
bits : 1 - 0 (0 bit)
access : read-only

USB_INT2 : ERROR!!!!!!!!!!!!!!!!!!!!
bits : 2 - 1 (0 bit)
access : read-only

USB_INT3 : ERROR!!!!!!!!!!!!!!!!!!!!
bits : 3 - 2 (0 bit)
access : read-only

USB_INT4 : ERROR!!!!!!!!!!!!!!!!!!!!
bits : 4 - 3 (0 bit)
access : read-only

USB_INT5 : ERROR!!!!!!!!!!!!!!!!!!!!
bits : 5 - 4 (0 bit)
access : read-only

RCEC1INT : ERROR!!!!!!!!!!!!!!!!!!!!
bits : 6 - 5 (0 bit)
access : read-only


IRQ115MON

ERROR!!!!!!!!!!!!!!!!!!!!
address_offset : 0x3D0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ115MON IRQ115MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QSPIINT0 QSPIINT1 QSPIINT2

QSPIINT0 : ERROR!!!!!!!!!!!!!!!!!!!!
bits : 0 - -1 (0 bit)
access : read-only

QSPIINT1 : ERROR!!!!!!!!!!!!!!!!!!!!
bits : 1 - 0 (0 bit)
access : read-only

QSPIINT2 : ERROR!!!!!!!!!!!!!!!!!!!!
bits : 2 - 1 (0 bit)
access : read-only


IRQ116MON

ERROR!!!!!!!!!!!!!!!!!!!!
address_offset : 0x3D4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ116MON IRQ116MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IRQ117MON

ERROR!!!!!!!!!!!!!!!!!!!!
address_offset : 0x3D8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ117MON IRQ117MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2SINT PRGCRC

I2SINT : ERROR!!!!!!!!!!!!!!!!!!!!
bits : 0 - -1 (0 bit)
access : read-only

PRGCRC : ERROR!!!!!!!!!!!!!!!!!!!!
bits : 1 - 0 (0 bit)
access : read-only


IRQ118MON

ERROR!!!!!!!!!!!!!!!!!!!!
address_offset : 0x3DC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ118MON IRQ118MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDINT0 SDINT1

SDINT0 : ERROR!!!!!!!!!!!!!!!!!!!!
bits : 0 - -1 (0 bit)
access : read-only

SDINT1 : ERROR!!!!!!!!!!!!!!!!!!!!
bits : 1 - 0 (0 bit)
access : read-only


IRQ119MON

ERROR!!!!!!!!!!!!!!!!!!!!
address_offset : 0x3E0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ119MON IRQ119MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FLINT

FLINT : ERROR!!!!!!!!!!!!!!!!!!!!
bits : 0 - -1 (0 bit)
access : read-only


IRQ120MON

ERROR!!!!!!!!!!!!!!!!!!!!
address_offset : 0x3E4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ120MON IRQ120MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFSRINT

MFSRINT : ERROR!!!!!!!!!!!!!!!!!!!!
bits : 0 - -1 (0 bit)
access : read-only


IRQ121MON

ERROR!!!!!!!!!!!!!!!!!!!!
address_offset : 0x3E8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ121MON IRQ121MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFSINT0 MFSINT1

MFSINT0 : ERROR!!!!!!!!!!!!!!!!!!!!
bits : 0 - -1 (0 bit)
access : read-only

MFSINT1 : ERROR!!!!!!!!!!!!!!!!!!!!
bits : 1 - 0 (0 bit)
access : read-only


IRQ122MON

ERROR!!!!!!!!!!!!!!!!!!!!
address_offset : 0x3EC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ122MON IRQ122MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFSRINT

MFSRINT : ERROR!!!!!!!!!!!!!!!!!!!!
bits : 0 - -1 (0 bit)
access : read-only


IRQ123MON

ERROR!!!!!!!!!!!!!!!!!!!!
address_offset : 0x3F0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ123MON IRQ123MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFSINT0 MFSINT1

MFSINT0 : ERROR!!!!!!!!!!!!!!!!!!!!
bits : 0 - -1 (0 bit)
access : read-only

MFSINT1 : ERROR!!!!!!!!!!!!!!!!!!!!
bits : 1 - 0 (0 bit)
access : read-only


IRQ124MON

ERROR!!!!!!!!!!!!!!!!!!!!
address_offset : 0x3F4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ124MON IRQ124MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFSRINT

MFSRINT : ERROR!!!!!!!!!!!!!!!!!!!!
bits : 0 - -1 (0 bit)
access : read-only


IRQ125MON

ERROR!!!!!!!!!!!!!!!!!!!!
address_offset : 0x3F8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ125MON IRQ125MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFSINT0 MFSINT1

MFSINT0 : ERROR!!!!!!!!!!!!!!!!!!!!
bits : 0 - -1 (0 bit)
access : read-only

MFSINT1 : ERROR!!!!!!!!!!!!!!!!!!!!
bits : 1 - 0 (0 bit)
access : read-only


IRQ126MON

ERROR!!!!!!!!!!!!!!!!!!!!
address_offset : 0x3FC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ126MON IRQ126MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFSRINT

MFSRINT : ERROR!!!!!!!!!!!!!!!!!!!!
bits : 0 - -1 (0 bit)
access : read-only


IRQ127MON

ERROR!!!!!!!!!!!!!!!!!!!!
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ127MON IRQ127MON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFSINT0 MFSINT1

MFSINT0 : ERROR!!!!!!!!!!!!!!!!!!!!
bits : 0 - -1 (0 bit)
access : read-only

MFSINT1 : ERROR!!!!!!!!!!!!!!!!!!!!
bits : 1 - 0 (0 bit)
access : read-only



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