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CAN0

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xE byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x10 Bytes (0x0)
size : 0xE byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x20 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x30 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x40 Bytes (0x0)
size : 0xE byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x50 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x60 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x80 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x90 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xA0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xB0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CTRLR

IF1CREQ

IF1CMSK

IF1MSK1

IF1MSK2

IF1ARB1

IF1ARB2

IF1MCTR

STATR

IF1DTA1_L

IF1DTA2_L

IF1DTB1_L

IF1DTB2_L

IF1DTA2_B

IF1DTA1_B

IF1DTB2_B

IF1DTB1_B

ERRCNT

IF2CREQ

IF2CMSK

IF2MSK1

IF2MSK2

IF2ARB1

IF2ARB2

IF2MCTR

IF2DTA1_L

IF2DTA2_L

IF2DTB1_L

IF2DTB2_L

BTR

IF2DTA2_B

IF2DTA1_B

IF2DTB2_B

IF2DTB1_B

INTR

TREQR1

TREQR2

NEWDT1

NEWDT2

TESTR

INTPND1

INTPND2

MSGVAL1

MSGVAL2

BRPER


CTRLR

CAN Control Register
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRLR CTRLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INIT IE SIE EIE DAR CCE TEST

INIT : Initialization bit
bits : 0 - -1 (0 bit)
access : read-write

IE : Interrupt enable bit
bits : 1 - 0 (0 bit)
access : read-write

SIE : Status interrupt code enable bit
bits : 2 - 1 (0 bit)
access : read-write

EIE : Error interrupt code enable bit
bits : 3 - 2 (0 bit)
access : read-write

DAR : Automatic retransmission disable bit
bits : 5 - 4 (0 bit)
access : read-write

CCE : Bit Timing Register write enable bit
bits : 6 - 5 (0 bit)
access : read-write

TEST : Test mode enable bit
bits : 7 - 6 (0 bit)
access : read-write


IF1CREQ

IF1 Command Request Register
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF1CREQ IF1CREQ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MESSAGENUMBER BUSY

MESSAGENUMBER : Message number
bits : 0 - 6 (7 bit)
access : read-write

BUSY : Busy flag bit
bits : 15 - 14 (0 bit)
access : read-write


IF1CMSK

IF1 Command Mask Register
address_offset : 0x12 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF1CMSK IF1CMSK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATAB DATAA NEWDAT CIP CONTROL ARB MASK WRRD

DATAB : Data 4-7 update bit
bits : 0 - -1 (0 bit)
access : read-write

DATAA : Data 0-3 update bit
bits : 1 - 0 (0 bit)
access : read-write

NEWDAT : Message transmission request bit
bits : 2 - 1 (0 bit)
access : read-write

CIP : Interrupt clear bit
bits : 3 - 2 (0 bit)
access : read-write

CONTROL : Control data update bit
bits : 4 - 3 (0 bit)
access : read-write

ARB : Arbitration data update bit
bits : 5 - 4 (0 bit)
access : read-write

MASK : Mask data update bit
bits : 6 - 5 (0 bit)
access : read-write

WRRD : Writing or reading control bit
bits : 7 - 6 (0 bit)
access : read-write


IF1MSK1

IF1 Mask Registers 1
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF1MSK1 IF1MSK1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MSK0 MSK1 MSK2 MSK3 MSK4 MSK5 MSK6 MSK7 MSK8 MSK9 MSK10 MSK11 MSK12 MSK13 MSK14 MSK15

MSK0 : Msk0
bits : 0 - -1 (0 bit)
access : read-write

MSK1 : Msk1
bits : 1 - 0 (0 bit)
access : read-write

MSK2 : Msk2
bits : 2 - 1 (0 bit)
access : read-write

MSK3 : Msk3
bits : 3 - 2 (0 bit)
access : read-write

MSK4 : Msk4
bits : 4 - 3 (0 bit)
access : read-write

MSK5 : Msk5
bits : 5 - 4 (0 bit)
access : read-write

MSK6 : Msk6
bits : 6 - 5 (0 bit)
access : read-write

MSK7 : Msk7
bits : 7 - 6 (0 bit)
access : read-write

MSK8 : Msk8
bits : 8 - 7 (0 bit)
access : read-write

MSK9 : Msk9
bits : 9 - 8 (0 bit)
access : read-write

MSK10 : Msk10
bits : 10 - 9 (0 bit)
access : read-write

MSK11 : Msk11
bits : 11 - 10 (0 bit)
access : read-write

MSK12 : Msk12
bits : 12 - 11 (0 bit)
access : read-write

MSK13 : Msk13
bits : 13 - 12 (0 bit)
access : read-write

MSK14 : Msk14
bits : 14 - 13 (0 bit)
access : read-write

MSK15 : Msk15
bits : 15 - 14 (0 bit)
access : read-write


IF1MSK2

IF1 Mask Registers 2
address_offset : 0x16 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF1MSK2 IF1MSK2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MSK16 MSK17 MSK18 MSK19 MSK20 MSK21 MSK22 MSK23 MSK24 MSK25 MSK26 MSK27 MSK28 MDIR MXTD

MSK16 : Msk16
bits : 0 - -1 (0 bit)
access : read-write

MSK17 : Msk17
bits : 1 - 0 (0 bit)
access : read-write

MSK18 : Msk18
bits : 2 - 1 (0 bit)
access : read-write

MSK19 : Msk19
bits : 3 - 2 (0 bit)
access : read-write

MSK20 : Msk20
bits : 4 - 3 (0 bit)
access : read-write

MSK21 : Msk21
bits : 5 - 4 (0 bit)
access : read-write

MSK22 : Msk22
bits : 6 - 5 (0 bit)
access : read-write

MSK23 : Msk23
bits : 7 - 6 (0 bit)
access : read-write

MSK24 : Msk24
bits : 8 - 7 (0 bit)
access : read-write

MSK25 : Msk25
bits : 9 - 8 (0 bit)
access : read-write

MSK26 : Msk26
bits : 10 - 9 (0 bit)
access : read-write

MSK27 : Msk27
bits : 11 - 10 (0 bit)
access : read-write

MSK28 : Msk28
bits : 12 - 11 (0 bit)
access : read-write

MDIR : MDir
bits : 14 - 13 (0 bit)
access : read-write

MXTD : MXtd
bits : 15 - 14 (0 bit)
access : read-write


IF1ARB1

IF1 Arbitration Registers 1
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF1ARB1 IF1ARB1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7 ID8 ID9 ID10 ID11 ID12 ID13 ID14 ID15

ID0 : ID0
bits : 0 - -1 (0 bit)
access : read-write

ID1 : ID1
bits : 1 - 0 (0 bit)
access : read-write

ID2 : ID2
bits : 2 - 1 (0 bit)
access : read-write

ID3 : ID3
bits : 3 - 2 (0 bit)
access : read-write

ID4 : ID4
bits : 4 - 3 (0 bit)
access : read-write

ID5 : ID5
bits : 5 - 4 (0 bit)
access : read-write

ID6 : ID6
bits : 6 - 5 (0 bit)
access : read-write

ID7 : ID7
bits : 7 - 6 (0 bit)
access : read-write

ID8 : ID8
bits : 8 - 7 (0 bit)
access : read-write

ID9 : ID9
bits : 9 - 8 (0 bit)
access : read-write

ID10 : ID10
bits : 10 - 9 (0 bit)
access : read-write

ID11 : ID11
bits : 11 - 10 (0 bit)
access : read-write

ID12 : ID12
bits : 12 - 11 (0 bit)
access : read-write

ID13 : ID13
bits : 13 - 12 (0 bit)
access : read-write

ID14 : ID14
bits : 14 - 13 (0 bit)
access : read-write

ID15 : ID15
bits : 15 - 14 (0 bit)
access : read-write


IF1ARB2

IF1 Arbitration Registers 2
address_offset : 0x1A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF1ARB2 IF1ARB2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID16 ID17 ID18 ID19 ID20 ID21 ID22 ID23 ID24 ID25 ID26 ID27 ID28 DIR XTD MSGVAL

ID16 : ID16
bits : 0 - -1 (0 bit)
access : read-write

ID17 : ID17
bits : 1 - 0 (0 bit)
access : read-write

ID18 : ID18
bits : 2 - 1 (0 bit)
access : read-write

ID19 : ID19
bits : 3 - 2 (0 bit)
access : read-write

ID20 : ID20
bits : 4 - 3 (0 bit)
access : read-write

ID21 : ID21
bits : 5 - 4 (0 bit)
access : read-write

ID22 : ID22
bits : 6 - 5 (0 bit)
access : read-write

ID23 : ID23
bits : 7 - 6 (0 bit)
access : read-write

ID24 : ID24
bits : 8 - 7 (0 bit)
access : read-write

ID25 : ID25
bits : 9 - 8 (0 bit)
access : read-write

ID26 : ID26
bits : 10 - 9 (0 bit)
access : read-write

ID27 : ID27
bits : 11 - 10 (0 bit)
access : read-write

ID28 : ID28
bits : 12 - 11 (0 bit)
access : read-write

DIR : Dir
bits : 13 - 12 (0 bit)
access : read-write

XTD : Xtd
bits : 14 - 13 (0 bit)
access : read-write

MSGVAL : MsgVal
bits : 15 - 14 (0 bit)
access : read-write


IF1MCTR

IF1 Message Control Register
address_offset : 0x1C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF1MCTR IF1MCTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLC EOB TXRQST RMTEN RXIE TXIE UMASK INTPND MSGLST NEWDAT

DLC : DLC
bits : 0 - 2 (3 bit)
access : read-write

EOB : EoB
bits : 7 - 6 (0 bit)
access : read-write

TXRQST : TxRqst
bits : 8 - 7 (0 bit)
access : read-write

RMTEN : RmtEn
bits : 9 - 8 (0 bit)
access : read-write

RXIE : RxIE
bits : 10 - 9 (0 bit)
access : read-write

TXIE : TxIE
bits : 11 - 10 (0 bit)
access : read-write

UMASK : UMask
bits : 12 - 11 (0 bit)
access : read-write

INTPND : IntPnd
bits : 13 - 12 (0 bit)
access : read-write

MSGLST : MsgLst
bits : 14 - 13 (0 bit)
access : read-write

NEWDAT : NewDat
bits : 15 - 14 (0 bit)
access : read-write


STATR

CAN Status Register
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATR STATR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LEC TXOK RXOK EPASS EWARN BOFF

LEC : Last error code bits
bits : 0 - 1 (2 bit)
access : read-write

TXOK : Successful message transmission bit
bits : 3 - 2 (0 bit)
access : read-write

RXOK : Successful message reception bit
bits : 4 - 3 (0 bit)
access : read-write

EPASS : Error passive bit
bits : 5 - 4 (0 bit)
access : read-only

EWARN : Warning bit
bits : 6 - 5 (0 bit)
access : read-only

BOFF : Busoff bit
bits : 7 - 6 (0 bit)
access : read-only


IF1DTA1_L

IF1 Data Registers A1
address_offset : 0x20 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF1DTA1_L IF1DTA1_L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA_0_ DATA_1_

DATA_0_ : Data(0)
bits : 0 - 6 (7 bit)
access : read-write

DATA_1_ : Data(1)
bits : 8 - 14 (7 bit)
access : read-write


IF1DTA2_L

IF1 Data Registers A2
address_offset : 0x22 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF1DTA2_L IF1DTA2_L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA_2_ DATA_3_

DATA_2_ : Data(2)
bits : 0 - 6 (7 bit)
access : read-write

DATA_3_ : Data(3)
bits : 8 - 14 (7 bit)
access : read-write


IF1DTB1_L

IF1 Data Registers B1
address_offset : 0x24 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF1DTB1_L IF1DTB1_L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA_4_ DATA_5_

DATA_4_ : Data(4)
bits : 0 - 6 (7 bit)
access : read-write

DATA_5_ : Data(5)
bits : 8 - 14 (7 bit)
access : read-write


IF1DTB2_L

IF1 Data Registers B2
address_offset : 0x26 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF1DTB2_L IF1DTB2_L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA_6_ DATA_7_

DATA_6_ : Data(6)
bits : 0 - 6 (7 bit)
access : read-write

DATA_7_ : Data(7)
bits : 8 - 14 (7 bit)
access : read-write


IF1DTA2_B

IF1 Data Registers A2
address_offset : 0x30 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF1DTA2_B IF1DTA2_B read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA_3_ DATA_2_

DATA_3_ : Data(3)
bits : 0 - 6 (7 bit)
access : read-write

DATA_2_ : Data(2)
bits : 8 - 14 (7 bit)
access : read-write


IF1DTA1_B

IF1 Data Registers A1
address_offset : 0x32 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF1DTA1_B IF1DTA1_B read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA_1_ DATA_0_

DATA_1_ : Data(1)
bits : 0 - 6 (7 bit)
access : read-write

DATA_0_ : Data(0)
bits : 8 - 14 (7 bit)
access : read-write


IF1DTB2_B

IF1 Data Registers B2
address_offset : 0x34 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF1DTB2_B IF1DTB2_B read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA_7_ DATA_6_

DATA_7_ : Data(7)
bits : 0 - 6 (7 bit)
access : read-write

DATA_6_ : Data(6)
bits : 8 - 14 (7 bit)
access : read-write


IF1DTB1_B

IF1 Data Registers B1
address_offset : 0x36 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF1DTB1_B IF1DTB1_B read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA_5_ DATA_4_

DATA_5_ : Data(5)
bits : 0 - 6 (7 bit)
access : read-write

DATA_4_ : Data(4)
bits : 8 - 14 (7 bit)
access : read-write


ERRCNT

CAN Error Counter
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ERRCNT ERRCNT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEC REC RP

TEC : Send error counter
bits : 0 - 6 (7 bit)
access : read-only

REC : Receive error counter
bits : 8 - 13 (6 bit)
access : read-only

RP : Receive error passive indication
bits : 15 - 14 (0 bit)
access : read-only


IF2CREQ

IF2 Command Request Register
address_offset : 0x40 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF2CREQ IF2CREQ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MESSAGENUMBER BUSY

MESSAGENUMBER : Message number
bits : 0 - 6 (7 bit)
access : read-write

BUSY : Busy flag bit
bits : 15 - 14 (0 bit)
access : read-write


IF2CMSK

IF2 Command Mask Register
address_offset : 0x42 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF2CMSK IF2CMSK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATAB DATAA NEWDAT CIP CONTROL ARB MASK WRRD

DATAB : Data 4-7 update bit
bits : 0 - -1 (0 bit)
access : read-write

DATAA : Data 0-3 update bit
bits : 1 - 0 (0 bit)
access : read-write

NEWDAT : Message transmission request bit
bits : 2 - 1 (0 bit)
access : read-write

CIP : Interrupt clear bit
bits : 3 - 2 (0 bit)
access : read-write

CONTROL : Control data update bit
bits : 4 - 3 (0 bit)
access : read-write

ARB : Arbitration data update bit
bits : 5 - 4 (0 bit)
access : read-write

MASK : Mask data update bit
bits : 6 - 5 (0 bit)
access : read-write

WRRD : Writing or reading control bit
bits : 7 - 6 (0 bit)
access : read-write


IF2MSK1

IF2 Mask Registers 1
address_offset : 0x44 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF2MSK1 IF2MSK1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MSK0 MSK1 MSK2 MSK3 MSK4 MSK5 MSK6 MSK7 MSK8 MSK9 MSK10 MSK11 MSK12 MSK13 MSK14 MSK15

MSK0 : Msk0
bits : 0 - -1 (0 bit)
access : read-write

MSK1 : Msk1
bits : 1 - 0 (0 bit)
access : read-write

MSK2 : Msk2
bits : 2 - 1 (0 bit)
access : read-write

MSK3 : Msk3
bits : 3 - 2 (0 bit)
access : read-write

MSK4 : Msk4
bits : 4 - 3 (0 bit)
access : read-write

MSK5 : Msk5
bits : 5 - 4 (0 bit)
access : read-write

MSK6 : Msk6
bits : 6 - 5 (0 bit)
access : read-write

MSK7 : Msk7
bits : 7 - 6 (0 bit)
access : read-write

MSK8 : Msk8
bits : 8 - 7 (0 bit)
access : read-write

MSK9 : Msk9
bits : 9 - 8 (0 bit)
access : read-write

MSK10 : Msk10
bits : 10 - 9 (0 bit)
access : read-write

MSK11 : Msk11
bits : 11 - 10 (0 bit)
access : read-write

MSK12 : Msk12
bits : 12 - 11 (0 bit)
access : read-write

MSK13 : Msk13
bits : 13 - 12 (0 bit)
access : read-write

MSK14 : Msk14
bits : 14 - 13 (0 bit)
access : read-write

MSK15 : Msk15
bits : 15 - 14 (0 bit)
access : read-write


IF2MSK2

IF2 Mask Registers 2
address_offset : 0x46 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF2MSK2 IF2MSK2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MSK16 MSK17 MSK18 MSK19 MSK20 MSK21 MSK22 MSK23 MSK24 MSK25 MSK26 MSK27 MSK28 MDIR MXTD

MSK16 : Msk16
bits : 0 - -1 (0 bit)
access : read-write

MSK17 : Msk17
bits : 1 - 0 (0 bit)
access : read-write

MSK18 : Msk18
bits : 2 - 1 (0 bit)
access : read-write

MSK19 : Msk19
bits : 3 - 2 (0 bit)
access : read-write

MSK20 : Msk20
bits : 4 - 3 (0 bit)
access : read-write

MSK21 : Msk21
bits : 5 - 4 (0 bit)
access : read-write

MSK22 : Msk22
bits : 6 - 5 (0 bit)
access : read-write

MSK23 : Msk23
bits : 7 - 6 (0 bit)
access : read-write

MSK24 : Msk24
bits : 8 - 7 (0 bit)
access : read-write

MSK25 : Msk25
bits : 9 - 8 (0 bit)
access : read-write

MSK26 : Msk26
bits : 10 - 9 (0 bit)
access : read-write

MSK27 : Msk27
bits : 11 - 10 (0 bit)
access : read-write

MSK28 : Msk28
bits : 12 - 11 (0 bit)
access : read-write

MDIR : MDir
bits : 14 - 13 (0 bit)
access : read-write

MXTD : MXtd
bits : 15 - 14 (0 bit)
access : read-write


IF2ARB1

IF2 Arbitration Registers 1
address_offset : 0x48 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF2ARB1 IF2ARB1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7 ID8 ID9 ID10 ID11 ID12 ID13 ID14 ID15

ID0 : ID0
bits : 0 - -1 (0 bit)
access : read-write

ID1 : ID1
bits : 1 - 0 (0 bit)
access : read-write

ID2 : ID2
bits : 2 - 1 (0 bit)
access : read-write

ID3 : ID3
bits : 3 - 2 (0 bit)
access : read-write

ID4 : ID4
bits : 4 - 3 (0 bit)
access : read-write

ID5 : ID5
bits : 5 - 4 (0 bit)
access : read-write

ID6 : ID6
bits : 6 - 5 (0 bit)
access : read-write

ID7 : ID7
bits : 7 - 6 (0 bit)
access : read-write

ID8 : ID8
bits : 8 - 7 (0 bit)
access : read-write

ID9 : ID9
bits : 9 - 8 (0 bit)
access : read-write

ID10 : ID10
bits : 10 - 9 (0 bit)
access : read-write

ID11 : ID11
bits : 11 - 10 (0 bit)
access : read-write

ID12 : ID12
bits : 12 - 11 (0 bit)
access : read-write

ID13 : ID13
bits : 13 - 12 (0 bit)
access : read-write

ID14 : ID14
bits : 14 - 13 (0 bit)
access : read-write

ID15 : ID15
bits : 15 - 14 (0 bit)
access : read-write


IF2ARB2

IF2 Arbitration Registers 2
address_offset : 0x4A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF2ARB2 IF2ARB2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID16 ID17 ID18 ID19 ID20 ID21 ID22 ID23 ID24 ID25 ID26 ID27 ID28 DIR XTD MSGVAL

ID16 : ID16
bits : 0 - -1 (0 bit)
access : read-write

ID17 : ID17
bits : 1 - 0 (0 bit)
access : read-write

ID18 : ID18
bits : 2 - 1 (0 bit)
access : read-write

ID19 : ID19
bits : 3 - 2 (0 bit)
access : read-write

ID20 : ID20
bits : 4 - 3 (0 bit)
access : read-write

ID21 : ID21
bits : 5 - 4 (0 bit)
access : read-write

ID22 : ID22
bits : 6 - 5 (0 bit)
access : read-write

ID23 : ID23
bits : 7 - 6 (0 bit)
access : read-write

ID24 : ID24
bits : 8 - 7 (0 bit)
access : read-write

ID25 : ID25
bits : 9 - 8 (0 bit)
access : read-write

ID26 : ID26
bits : 10 - 9 (0 bit)
access : read-write

ID27 : ID27
bits : 11 - 10 (0 bit)
access : read-write

ID28 : ID28
bits : 12 - 11 (0 bit)
access : read-write

DIR : Dir
bits : 13 - 12 (0 bit)
access : read-write

XTD : Xtd
bits : 14 - 13 (0 bit)
access : read-write

MSGVAL : MsgVal
bits : 15 - 14 (0 bit)
access : read-write


IF2MCTR

IF2 Message Control Register
address_offset : 0x4C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF2MCTR IF2MCTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLC EOB TXRQST RMTEN RXIE TXIE UMASK INTPND MSGLST NEWDAT

DLC : DLC
bits : 0 - 2 (3 bit)
access : read-write

EOB : EoB
bits : 7 - 6 (0 bit)
access : read-write

TXRQST : TxRqst
bits : 8 - 7 (0 bit)
access : read-write

RMTEN : RmtEn
bits : 9 - 8 (0 bit)
access : read-write

RXIE : RxIE
bits : 10 - 9 (0 bit)
access : read-write

TXIE : TxIE
bits : 11 - 10 (0 bit)
access : read-write

UMASK : UMask
bits : 12 - 11 (0 bit)
access : read-write

INTPND : IntPnd
bits : 13 - 12 (0 bit)
access : read-write

MSGLST : MsgLst
bits : 14 - 13 (0 bit)
access : read-write

NEWDAT : NewDat
bits : 15 - 14 (0 bit)
access : read-write


IF2DTA1_L

IF2 Data Registers A1
address_offset : 0x50 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF2DTA1_L IF2DTA1_L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA_0_ DATA_1_

DATA_0_ : Data(0)
bits : 0 - 6 (7 bit)
access : read-write

DATA_1_ : Data(1)
bits : 8 - 14 (7 bit)
access : read-write


IF2DTA2_L

IF2 Data Registers A2
address_offset : 0x52 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF2DTA2_L IF2DTA2_L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA_2_ DATA_3_

DATA_2_ : Data(2)
bits : 0 - 6 (7 bit)
access : read-write

DATA_3_ : Data(3)
bits : 8 - 14 (7 bit)
access : read-write


IF2DTB1_L

IF2 Data Registers B1
address_offset : 0x54 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF2DTB1_L IF2DTB1_L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA_4_ DATA_5_

DATA_4_ : Data(4)
bits : 0 - 6 (7 bit)
access : read-write

DATA_5_ : Data(5)
bits : 8 - 14 (7 bit)
access : read-write


IF2DTB2_L

IF2 Data Registers B2
address_offset : 0x56 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF2DTB2_L IF2DTB2_L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA_6_ DATA_7_

DATA_6_ : Data(6)
bits : 0 - 6 (7 bit)
access : read-write

DATA_7_ : Data(7)
bits : 8 - 14 (7 bit)
access : read-write


BTR

CAN Bit Timing Register
address_offset : 0x6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BTR BTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BRP SJW TSEG1 TSEG2

BRP : Baud rate prescaler setting bits
bits : 0 - 4 (5 bit)
access : read-write

SJW : Resynchronization jump width setting bits
bits : 6 - 6 (1 bit)
access : read-write

TSEG1 : Time segment 1 setting bits
bits : 8 - 10 (3 bit)
access : read-write

TSEG2 : Time segment 2 setting bits
bits : 12 - 13 (2 bit)
access : read-write


IF2DTA2_B

IF2 Data Registers A2
address_offset : 0x60 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF2DTA2_B IF2DTA2_B read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA_3_ DATA_2_

DATA_3_ : Data(3)
bits : 0 - 6 (7 bit)
access : read-write

DATA_2_ : Data(2)
bits : 8 - 14 (7 bit)
access : read-write


IF2DTA1_B

IF2 Data Registers A1
address_offset : 0x62 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF2DTA1_B IF2DTA1_B read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA_1_ DATA_0_

DATA_1_ : Data(1)
bits : 0 - 6 (7 bit)
access : read-write

DATA_0_ : Data(0)
bits : 8 - 14 (7 bit)
access : read-write


IF2DTB2_B

IF2 Data Registers B2
address_offset : 0x64 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF2DTB2_B IF2DTB2_B read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA_7_ DATA_6_

DATA_7_ : Data(7)
bits : 0 - 6 (7 bit)
access : read-write

DATA_6_ : Data(6)
bits : 8 - 14 (7 bit)
access : read-write


IF2DTB1_B

IF2 Data Registers B1
address_offset : 0x66 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF2DTB1_B IF2DTB1_B read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA_5_ DATA_4_

DATA_5_ : Data(5)
bits : 0 - 6 (7 bit)
access : read-write

DATA_4_ : Data(4)
bits : 8 - 14 (7 bit)
access : read-write


INTR

CAN Interrupt Register
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INTR INTR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTID

INTID : Interrupt Code
bits : 0 - 14 (15 bit)
access : read-only


TREQR1

CAN Transmit Request Registers 1
address_offset : 0x80 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TREQR1 TREQR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXRQST1 TXRQST2 TXRQST3 TXRQST4 TXRQST5 TXRQST6 TXRQST7 TXRQST8 TXRQST9 TXRQST10 TXRQST11 TXRQST12 TXRQST13 TXRQST14 TXRQST15 TXRQST16

TXRQST1 : Bit0 of TREQR1
bits : 0 - -1 (0 bit)
access : read-only

TXRQST2 : Bit1 of TREQR1
bits : 1 - 0 (0 bit)
access : read-only

TXRQST3 : Bit2 of TREQR1
bits : 2 - 1 (0 bit)
access : read-only

TXRQST4 : Bit3 of TREQR1
bits : 3 - 2 (0 bit)
access : read-only

TXRQST5 : Bit4 of TREQR1
bits : 4 - 3 (0 bit)
access : read-only

TXRQST6 : Bit5 of TREQR1
bits : 5 - 4 (0 bit)
access : read-only

TXRQST7 : Bit6 of TREQR1
bits : 6 - 5 (0 bit)
access : read-only

TXRQST8 : Bit7 of TREQR1
bits : 7 - 6 (0 bit)
access : read-only

TXRQST9 : Bit8 of TREQR1
bits : 8 - 7 (0 bit)
access : read-only

TXRQST10 : Bit9 of TREQR1
bits : 9 - 8 (0 bit)
access : read-only

TXRQST11 : Bit10 of TREQR1
bits : 10 - 9 (0 bit)
access : read-only

TXRQST12 : Bit11 of TREQR1
bits : 11 - 10 (0 bit)
access : read-only

TXRQST13 : Bit12 of TREQR1
bits : 12 - 11 (0 bit)
access : read-only

TXRQST14 : Bit13 of TREQR1
bits : 13 - 12 (0 bit)
access : read-only

TXRQST15 : Bit14 of TREQR1
bits : 14 - 13 (0 bit)
access : read-only

TXRQST16 : Bit15 of TREQR1
bits : 15 - 14 (0 bit)
access : read-only


TREQR2

CAN Transmit Request Registers 2
address_offset : 0x82 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TREQR2 TREQR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXRQST17 TXRQST18 TXRQST19 TXRQST20 TXRQST21 TXRQST22 TXRQST23 TXRQST24 TXRQST25 TXRQST26 TXRQST27 TXRQST28 TXRQST29 TXRQST30 TXRQST31 TXRQST32

TXRQST17 : Bit0 of TREQR2
bits : 0 - -1 (0 bit)
access : read-only

TXRQST18 : Bit1 of TREQR2
bits : 1 - 0 (0 bit)
access : read-only

TXRQST19 : Bit2 of TREQR2
bits : 2 - 1 (0 bit)
access : read-only

TXRQST20 : Bit3 of TREQR2
bits : 3 - 2 (0 bit)
access : read-only

TXRQST21 : Bit4 of TREQR2
bits : 4 - 3 (0 bit)
access : read-only

TXRQST22 : Bit5 of TREQR2
bits : 5 - 4 (0 bit)
access : read-only

TXRQST23 : Bit6 of TREQR2
bits : 6 - 5 (0 bit)
access : read-only

TXRQST24 : Bit7 of TREQR2
bits : 7 - 6 (0 bit)
access : read-only

TXRQST25 : Bit8 of TREQR2
bits : 8 - 7 (0 bit)
access : read-only

TXRQST26 : Bit9 of TREQR2
bits : 9 - 8 (0 bit)
access : read-only

TXRQST27 : Bit10 of TREQR2
bits : 10 - 9 (0 bit)
access : read-only

TXRQST28 : Bit11 of TREQR2
bits : 11 - 10 (0 bit)
access : read-only

TXRQST29 : Bit12 of TREQR2
bits : 12 - 11 (0 bit)
access : read-only

TXRQST30 : Bit13 of TREQR2
bits : 13 - 12 (0 bit)
access : read-only

TXRQST31 : Bit14 of TREQR2
bits : 14 - 13 (0 bit)
access : read-only

TXRQST32 : Bit15 of TREQR2
bits : 15 - 14 (0 bit)
access : read-only


NEWDT1

CAN New Data Registers 1
address_offset : 0x90 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

NEWDT1 NEWDT1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NEWDAT1 NEWDAT2 NEWDAT3 NEWDAT4 NEWDAT5 NEWDAT6 NEWDAT7 NEWDAT8 NEWDAT9 NEWDAT10 NEWDAT11 NEWDAT12 NEWDAT13 NEWDAT14 NEWDAT15 NEWDAT16

NEWDAT1 : Bit0 of NEWDT1
bits : 0 - -1 (0 bit)
access : read-only

NEWDAT2 : Bit1 of NEWDT1
bits : 1 - 0 (0 bit)
access : read-only

NEWDAT3 : Bit2 of NEWDT1
bits : 2 - 1 (0 bit)
access : read-only

NEWDAT4 : Bit3 of NEWDT1
bits : 3 - 2 (0 bit)
access : read-only

NEWDAT5 : Bit4 of NEWDT1
bits : 4 - 3 (0 bit)
access : read-only

NEWDAT6 : Bit5 of NEWDT1
bits : 5 - 4 (0 bit)
access : read-only

NEWDAT7 : Bit6 of NEWDT1
bits : 6 - 5 (0 bit)
access : read-only

NEWDAT8 : Bit7 of NEWDT1
bits : 7 - 6 (0 bit)
access : read-only

NEWDAT9 : Bit8 of NEWDT1
bits : 8 - 7 (0 bit)
access : read-only

NEWDAT10 : Bit9 of NEWDT1
bits : 9 - 8 (0 bit)
access : read-only

NEWDAT11 : Bit10 of NEWDT1
bits : 10 - 9 (0 bit)
access : read-only

NEWDAT12 : Bit11 of NEWDT1
bits : 11 - 10 (0 bit)
access : read-only

NEWDAT13 : Bit12 of NEWDT1
bits : 12 - 11 (0 bit)
access : read-only

NEWDAT14 : Bit13 of NEWDT1
bits : 13 - 12 (0 bit)
access : read-only

NEWDAT15 : Bit14 of NEWDT1
bits : 14 - 13 (0 bit)
access : read-only

NEWDAT16 : Bit15 of NEWDT1
bits : 15 - 14 (0 bit)
access : read-only


NEWDT2

CAN New Data Registers 2
address_offset : 0x92 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

NEWDT2 NEWDT2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NEWDAT17 NEWDAT18 NEWDAT19 NEWDAT20 NEWDAT21 NEWDAT22 NEWDAT23 NEWDAT24 NEWDAT25 NEWDAT26 NEWDAT27 NEWDAT28 NEWDAT29 NEWDAT30 NEWDAT31 NEWDAT32

NEWDAT17 : Bit0 of NEWDT2
bits : 0 - -1 (0 bit)
access : read-only

NEWDAT18 : Bit1 of NEWDT2
bits : 1 - 0 (0 bit)
access : read-only

NEWDAT19 : Bit2 of NEWDT2
bits : 2 - 1 (0 bit)
access : read-only

NEWDAT20 : Bit3 of NEWDT2
bits : 3 - 2 (0 bit)
access : read-only

NEWDAT21 : Bit4 of NEWDT2
bits : 4 - 3 (0 bit)
access : read-only

NEWDAT22 : Bit5 of NEWDT2
bits : 5 - 4 (0 bit)
access : read-only

NEWDAT23 : Bit6 of NEWDT2
bits : 6 - 5 (0 bit)
access : read-only

NEWDAT24 : Bit7 of NEWDT2
bits : 7 - 6 (0 bit)
access : read-only

NEWDAT25 : Bit8 of NEWDT2
bits : 8 - 7 (0 bit)
access : read-only

NEWDAT26 : Bit9 of NEWDT2
bits : 9 - 8 (0 bit)
access : read-only

NEWDAT27 : Bit10 of NEWDT2
bits : 10 - 9 (0 bit)
access : read-only

NEWDAT28 : Bit11 of NEWDT2
bits : 11 - 10 (0 bit)
access : read-only

NEWDAT29 : Bit12 of NEWDT2
bits : 12 - 11 (0 bit)
access : read-only

NEWDAT30 : Bit13 of NEWDT2
bits : 13 - 12 (0 bit)
access : read-only

NEWDAT31 : Bit14 of NEWDT2
bits : 14 - 13 (0 bit)
access : read-only

NEWDAT32 : Bit15 of NEWDT2
bits : 15 - 14 (0 bit)
access : read-only


TESTR

CAN Test Register
address_offset : 0xA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TESTR TESTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BASIC SILENT LBACK TX RX

BASIC : Basic mode
bits : 2 - 1 (0 bit)
access : read-write

SILENT : Silent mode
bits : 3 - 2 (0 bit)
access : read-write

LBACK : Loop back mode
bits : 4 - 3 (0 bit)
access : read-write

TX : TX pin control bit
bits : 5 - 5 (1 bit)
access : read-write

RX : Rx pin monitor bit
bits : 7 - 6 (0 bit)
access : read-only


INTPND1

CAN Interrupt Pending Registers 1
address_offset : 0xA0 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INTPND1 INTPND1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTPND1 INTPND2 INTPND3 INTPND4 INTPND5 INTPND6 INTPND7 INTPND8 INTPND9 INTPND10 INTPND11 INTPND12 INTPND13 INTPND14 INTPND15 INTPND16

INTPND1 : Bit0 of INTPND1
bits : 0 - -1 (0 bit)
access : read-only

INTPND2 : Bit1 of INTPND1
bits : 1 - 0 (0 bit)
access : read-only

INTPND3 : Bit2 of INTPND1
bits : 2 - 1 (0 bit)
access : read-only

INTPND4 : Bit3 of INTPND1
bits : 3 - 2 (0 bit)
access : read-only

INTPND5 : Bit4 of INTPND1
bits : 4 - 3 (0 bit)
access : read-only

INTPND6 : Bit5 of INTPND1
bits : 5 - 4 (0 bit)
access : read-only

INTPND7 : Bit6 of INTPND1
bits : 6 - 5 (0 bit)
access : read-only

INTPND8 : Bit7 of INTPND1
bits : 7 - 6 (0 bit)
access : read-only

INTPND9 : Bit8 of INTPND1
bits : 8 - 7 (0 bit)
access : read-only

INTPND10 : Bit9 of INTPND1
bits : 9 - 8 (0 bit)
access : read-only

INTPND11 : Bit10 of INTPND1
bits : 10 - 9 (0 bit)
access : read-only

INTPND12 : Bit11 of INTPND1
bits : 11 - 10 (0 bit)
access : read-only

INTPND13 : Bit12 of INTPND1
bits : 12 - 11 (0 bit)
access : read-only

INTPND14 : Bit13 of INTPND1
bits : 13 - 12 (0 bit)
access : read-only

INTPND15 : Bit14 of INTPND1
bits : 14 - 13 (0 bit)
access : read-only

INTPND16 : Bit15 of INTPND1
bits : 15 - 14 (0 bit)
access : read-only


INTPND2

CAN Interrupt Pending Registers 2
address_offset : 0xA2 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INTPND2 INTPND2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTPND17 INTPND18 INTPND19 INTPND20 INTPND21 INTPND22 INTPND23 INTPND24 INTPND25 INTPND26 INTPND27 INTPND28 INTPND29 INTPND30 INTPND31 INTPND32

INTPND17 : Bit0 of INTPND2
bits : 0 - -1 (0 bit)
access : read-only

INTPND18 : Bit1 of INTPND2
bits : 1 - 0 (0 bit)
access : read-only

INTPND19 : Bit2 of INTPND2
bits : 2 - 1 (0 bit)
access : read-only

INTPND20 : Bit3 of INTPND2
bits : 3 - 2 (0 bit)
access : read-only

INTPND21 : Bit4 of INTPND2
bits : 4 - 3 (0 bit)
access : read-only

INTPND22 : Bit5 of INTPND2
bits : 5 - 4 (0 bit)
access : read-only

INTPND23 : Bit6 of INTPND2
bits : 6 - 5 (0 bit)
access : read-only

INTPND24 : Bit7 of INTPND2
bits : 7 - 6 (0 bit)
access : read-only

INTPND25 : Bit8 of INTPND2
bits : 8 - 7 (0 bit)
access : read-only

INTPND26 : Bit9 of INTPND2
bits : 9 - 8 (0 bit)
access : read-only

INTPND27 : Bit10 of INTPND2
bits : 10 - 9 (0 bit)
access : read-only

INTPND28 : Bit11 of INTPND2
bits : 11 - 10 (0 bit)
access : read-only

INTPND29 : Bit12 of INTPND2
bits : 12 - 11 (0 bit)
access : read-only

INTPND30 : Bit13 of INTPND2
bits : 13 - 12 (0 bit)
access : read-only

INTPND31 : Bit14 of INTPND2
bits : 14 - 13 (0 bit)
access : read-only

INTPND32 : Bit15 of INTPND2
bits : 15 - 14 (0 bit)
access : read-only


MSGVAL1

CAN Message Valid Registers 1
address_offset : 0xB0 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MSGVAL1 MSGVAL1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MSGVAL1 MSGVAL2 MSGVAL3 MSGVAL4 MSGVAL5 MSGVAL6 MSGVAL7 MSGVAL8 MSGVAL9 MSGVAL10 MSGVAL11 MSGVAL12 MSGVAL13 MSGVAL14 MSGVAL15 MSGVAL16

MSGVAL1 : Bit0 of MSGVAL1
bits : 0 - -1 (0 bit)
access : read-only

MSGVAL2 : Bit1 of MSGVAL1
bits : 1 - 0 (0 bit)
access : read-only

MSGVAL3 : Bit2 of MSGVAL1
bits : 2 - 1 (0 bit)
access : read-only

MSGVAL4 : Bit3 of MSGVAL1
bits : 3 - 2 (0 bit)
access : read-only

MSGVAL5 : Bit4 of MSGVAL1
bits : 4 - 3 (0 bit)
access : read-only

MSGVAL6 : Bit5 of MSGVAL1
bits : 5 - 4 (0 bit)
access : read-only

MSGVAL7 : Bit6 of MSGVAL1
bits : 6 - 5 (0 bit)
access : read-only

MSGVAL8 : Bit7 of MSGVAL1
bits : 7 - 6 (0 bit)
access : read-only

MSGVAL9 : Bit8 of MSGVAL1
bits : 8 - 7 (0 bit)
access : read-only

MSGVAL10 : Bit9 of MSGVAL1
bits : 9 - 8 (0 bit)
access : read-only

MSGVAL11 : Bit10 of MSGVAL1
bits : 10 - 9 (0 bit)
access : read-only

MSGVAL12 : Bit11 of MSGVAL1
bits : 11 - 10 (0 bit)
access : read-only

MSGVAL13 : Bit12 of MSGVAL1
bits : 12 - 11 (0 bit)
access : read-only

MSGVAL14 : Bit13 of MSGVAL1
bits : 13 - 12 (0 bit)
access : read-only

MSGVAL15 : Bit14 of MSGVAL1
bits : 14 - 13 (0 bit)
access : read-only

MSGVAL16 : Bit15 of MSGVAL1
bits : 15 - 14 (0 bit)
access : read-only


MSGVAL2

CAN Message Valid Registers 2
address_offset : 0xB2 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MSGVAL2 MSGVAL2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MSGVAL17 MSGVAL18 MSGVAL19 MSGVAL20 MSGVAL21 MSGVAL22 MSGVAL23 MSGVAL24 MSGVAL25 MSGVAL26 MSGVAL27 MSGVAL28 MSGVAL29 MSGVAL30 MSGVAL31 MSGVAL32

MSGVAL17 : Bit0 of MSGVAL2
bits : 0 - -1 (0 bit)
access : read-only

MSGVAL18 : Bit1 of MSGVAL2
bits : 1 - 0 (0 bit)
access : read-only

MSGVAL19 : Bit2 of MSGVAL2
bits : 2 - 1 (0 bit)
access : read-only

MSGVAL20 : Bit3 of MSGVAL2
bits : 3 - 2 (0 bit)
access : read-only

MSGVAL21 : Bit4 of MSGVAL2
bits : 4 - 3 (0 bit)
access : read-only

MSGVAL22 : Bit5 of MSGVAL2
bits : 5 - 4 (0 bit)
access : read-only

MSGVAL23 : Bit6 of MSGVAL2
bits : 6 - 5 (0 bit)
access : read-only

MSGVAL24 : Bit7 of MSGVAL2
bits : 7 - 6 (0 bit)
access : read-only

MSGVAL25 : Bit8 of MSGVAL2
bits : 8 - 7 (0 bit)
access : read-only

MSGVAL26 : Bit9 of MSGVAL2
bits : 9 - 8 (0 bit)
access : read-only

MSGVAL27 : Bit10 of MSGVAL2
bits : 10 - 9 (0 bit)
access : read-only

MSGVAL28 : Bit11 of MSGVAL2
bits : 11 - 10 (0 bit)
access : read-only

MSGVAL29 : Bit12 of MSGVAL2
bits : 12 - 11 (0 bit)
access : read-only

MSGVAL30 : Bit13 of MSGVAL2
bits : 13 - 12 (0 bit)
access : read-only

MSGVAL31 : Bit14 of MSGVAL2
bits : 14 - 13 (0 bit)
access : read-only

MSGVAL32 : Bit15 of MSGVAL2
bits : 15 - 14 (0 bit)
access : read-only


BRPER

CAN Prescaler Extension Register
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BRPER BRPER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BRPE

BRPE : Baud rate prescaler extension bit
bits : 0 - 2 (3 bit)
access : read-write



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