\n

RSTCU

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

RSTCU_GRSR (GRSR)

RSTCU_APBPRSTR0 (APBPRSTR0)

RSTCU_APBPRSTR1 (APBPRSTR1)


RSTCU_GRSR (GRSR)

RSTCU_GRSR
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RSTCU_GRSR RSTCU_GRSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSRSTF EXTRSTF WDTRSTF PORSTF RESERVED

SYSRSTF : SYSRSTF
bits : 0 - 0 (1 bit)
access : read-write

EXTRSTF : EXTRSTF
bits : 1 - 2 (2 bit)
access : read-write

WDTRSTF : WDTRSTF
bits : 2 - 4 (3 bit)
access : read-write

PORSTF : PORSTF
bits : 3 - 6 (4 bit)
access : read-write

RESERVED : Reserved.
bits : 4 - 35 (32 bit)
access : read-write


RSTCU_APBPRSTR0 (APBPRSTR0)

RSTCU_APBPRSTR0
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RSTCU_APBPRSTR0 RSTCU_APBPRSTR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2CRST SPIRST URRST AFIORST EXTIRST PARST PBRST RESERVED

I2CRST : I2CRST
bits : 0 - 0 (1 bit)
access : read-write

SPIRST : SPIRST
bits : 4 - 8 (5 bit)
access : read-write

URRST : URRST
bits : 8 - 16 (9 bit)
access : read-write

AFIORST : AFIORST
bits : 14 - 28 (15 bit)
access : read-write

EXTIRST : EXTIRST
bits : 15 - 30 (16 bit)
access : read-write

PARST : PARST
bits : 16 - 32 (17 bit)
access : read-write

PBRST : PBRST
bits : 17 - 34 (18 bit)
access : read-write

RESERVED : Reserved.
bits : 18 - 49 (32 bit)
access : read-write


RSTCU_APBPRSTR1 (APBPRSTR1)

RSTCU_APBPRSTR1
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RSTCU_APBPRSTR1 RSTCU_APBPRSTR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDTRST GPTM0RST GPTM1RST OPA0RST OPA1RST ADCRST RESERVED

WDTRST : WDTRST
bits : 4 - 8 (5 bit)
access : read-write

GPTM0RST : GPTM0RST
bits : 8 - 16 (9 bit)
access : read-write

GPTM1RST : GPTM1RST
bits : 9 - 18 (10 bit)
access : read-write

OPA0RST : OPA0RST
bits : 22 - 44 (23 bit)
access : read-write

OPA1RST : OPA1RST
bits : 23 - 46 (24 bit)
access : read-write

ADCRST : ADCRST
bits : 24 - 48 (25 bit)
access : read-write

RESERVED : Reserved.
bits : 25 - 56 (32 bit)
access : read-write



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.