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ADC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

ADC_LST0 (LST0)

ADC_TCR (TCR)

ADC_TSR (TSR)

ADC_WCR (WCR)

ADC_LTR (LTR)

ADC_UTR (UTR)

ADC_IMR (IMR)

ADC_IRAW (IRAW)

ADC_IMASK (IMASK)

ADC_ICLR (ICLR)

ADC_LST1 (LST1)

ADC_DMAR (DMAR)

ADC_OFR0 (OFR0)

ADC_OFR1 (OFR1)

ADC_OFR2 (OFR2)

ADC_OFR3 (OFR3)

ADC_RST (RST)

ADC_OFR4 (OFR4)

ADC_OFR5 (OFR5)

ADC_OFR6 (OFR6)

ADC_OFR7 (OFR7)

ADC_STR0 (STR0)

ADC_STR1 (STR1)

ADC_STR2 (STR2)

ADC_STR3 (STR3)

ADC_CONV (CONV)

ADC_STR4 (STR4)

ADC_STR5 (STR5)

ADC_STR6 (STR6)

ADC_STR7 (STR7)

ADC_DR0 (DR0)

ADC_DR1 (DR1)

ADC_DR2 (DR2)

ADC_DR3 (DR3)

ADC_DR4 (DR4)

ADC_DR5 (DR5)

ADC_DR6 (DR6)

ADC_DR7 (DR7)


ADC_LST0 (LST0)

ADC_LST0
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_LST0 ADC_LST0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADSEQ0 ADSEQ1 ADSEQ2 ADSEQ3 RESERVED

ADSEQ0 : ADSEQ0
bits : 0 - 4 (5 bit)
access : read-write

ADSEQ1 : ADSEQ1
bits : 8 - 20 (13 bit)
access : read-write

ADSEQ2 : ADSEQ2
bits : 16 - 36 (21 bit)
access : read-write

ADSEQ3 : ADSEQ3
bits : 24 - 52 (29 bit)
access : read-write

RESERVED : Reserved.
bits : 29 - 60 (32 bit)
access : read-write


ADC_TCR (TCR)

ADC_TCR
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_TCR ADC_TCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADSW ADEXTI TM BFTM RESERVED

ADSW : ADSW
bits : 0 - 0 (1 bit)
access : read-write

ADEXTI : ADEXTI
bits : 1 - 2 (2 bit)
access : read-write

TM : TM
bits : 2 - 4 (3 bit)
access : read-write

BFTM : BFTM
bits : 3 - 6 (4 bit)
access : read-write

RESERVED : Reserved.
bits : 4 - 35 (32 bit)
access : read-write


ADC_TSR (TSR)

ADC_TSR
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_TSR ADC_TSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADSC ADEXTIS TMS BFTMS TME RESERVED

ADSC : ADSC
bits : 0 - 0 (1 bit)
access : read-write

ADEXTIS : ADEXTIS
bits : 8 - 19 (12 bit)
access : read-write

TMS : TMS
bits : 16 - 34 (19 bit)
access : read-write

BFTMS : BFTMS
bits : 19 - 38 (20 bit)
access : read-write

TME : TME
bits : 24 - 50 (27 bit)
access : read-write

RESERVED : Reserved.
bits : 27 - 58 (32 bit)
access : read-write


ADC_WCR (WCR)

ADC_WCR
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_WCR ADC_WCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADWLE ADWUE ADWALL ADWCH ADLCH ADUCH RESERVED

ADWLE : ADWLE
bits : 0 - 0 (1 bit)
access : read-write

ADWUE : ADWUE
bits : 1 - 2 (2 bit)
access : read-write

ADWALL : ADWALL
bits : 2 - 4 (3 bit)
access : read-write

ADWCH : ADWCH
bits : 8 - 19 (12 bit)
access : read-write

ADLCH : ADLCH
bits : 16 - 35 (20 bit)
access : read-write

ADUCH : ADUCH
bits : 24 - 51 (28 bit)
access : read-write

RESERVED : Reserved.
bits : 28 - 59 (32 bit)
access : read-write


ADC_LTR (LTR)

ADC_LTR
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_LTR ADC_LTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADLT RESERVED

ADLT : ADLT
bits : 0 - 11 (12 bit)
access : read-write

RESERVED : Reserved.
bits : 12 - 43 (32 bit)
access : read-write


ADC_UTR (UTR)

ADC_UTR
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_UTR ADC_UTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADUT RESERVED

ADUT : ADUT
bits : 0 - 11 (12 bit)
access : read-write

RESERVED : Reserved.
bits : 12 - 43 (32 bit)
access : read-write


ADC_IMR (IMR)

ADC_IMR
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_IMR ADC_IMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADIMS ADIMG ADIMC ADIML ADIMU ADIMO RESERVED

ADIMS : ADIMS
bits : 0 - 0 (1 bit)
access : read-write

ADIMG : ADIMG
bits : 1 - 2 (2 bit)
access : read-write

ADIMC : ADIMC
bits : 2 - 4 (3 bit)
access : read-write

ADIML : ADIML
bits : 16 - 32 (17 bit)
access : read-write

ADIMU : ADIMU
bits : 17 - 34 (18 bit)
access : read-write

ADIMO : ADIMO
bits : 24 - 48 (25 bit)
access : read-write

RESERVED : Reserved.
bits : 25 - 56 (32 bit)
access : read-write


ADC_IRAW (IRAW)

ADC_IRAW
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_IRAW ADC_IRAW read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADIRAWS ADIRAWG ADIRAWC ADIRAWL ADIRAWU ADIRAWO RESERVED

ADIRAWS : ADIRAWS
bits : 0 - 0 (1 bit)
access : read-write

ADIRAWG : ADIRAWG
bits : 1 - 2 (2 bit)
access : read-write

ADIRAWC : ADIRAWC
bits : 2 - 4 (3 bit)
access : read-write

ADIRAWL : ADIRAWL
bits : 16 - 32 (17 bit)
access : read-write

ADIRAWU : ADIRAWU
bits : 17 - 34 (18 bit)
access : read-write

ADIRAWO : ADIRAWO
bits : 24 - 48 (25 bit)
access : read-write

RESERVED : Reserved.
bits : 25 - 56 (32 bit)
access : read-write


ADC_IMASK (IMASK)

ADC_IMASK
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_IMASK ADC_IMASK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADIMASKS ADIMASKG ADIMASKC ADIMASKL ADIMASKU ADIMASKO RESERVED

ADIMASKS : ADIMASKS
bits : 0 - 0 (1 bit)
access : read-write

ADIMASKG : ADIMASKG
bits : 1 - 2 (2 bit)
access : read-write

ADIMASKC : ADIMASKC
bits : 2 - 4 (3 bit)
access : read-write

ADIMASKL : ADIMASKL
bits : 16 - 32 (17 bit)
access : read-write

ADIMASKU : ADIMASKU
bits : 17 - 34 (18 bit)
access : read-write

ADIMASKO : ADIMASKO
bits : 24 - 48 (25 bit)
access : read-write

RESERVED : Reserved.
bits : 25 - 56 (32 bit)
access : read-write


ADC_ICLR (ICLR)

ADC_ICLR
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_ICLR ADC_ICLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADICLRS ADICLRG ADICLRC ADICLRL ADICLRU ADICLRO RESERVED

ADICLRS : ADICLRS
bits : 0 - 0 (1 bit)
access : read-write

ADICLRG : ADICLRG
bits : 1 - 2 (2 bit)
access : read-write

ADICLRC : ADICLRC
bits : 2 - 4 (3 bit)
access : read-write

ADICLRL : ADICLRL
bits : 16 - 32 (17 bit)
access : read-write

ADICLRU : ADICLRU
bits : 17 - 34 (18 bit)
access : read-write

ADICLRO : ADICLRO
bits : 24 - 48 (25 bit)
access : read-write

RESERVED : Reserved.
bits : 25 - 56 (32 bit)
access : read-write


ADC_LST1 (LST1)

ADC_LST1
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_LST1 ADC_LST1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADSEQ4 ADSEQ5 ADSEQ6 ADSEQ7 RESERVED

ADSEQ4 : ADSEQ4
bits : 0 - 4 (5 bit)
access : read-write

ADSEQ5 : ADSEQ5
bits : 8 - 20 (13 bit)
access : read-write

ADSEQ6 : ADSEQ6
bits : 16 - 36 (21 bit)
access : read-write

ADSEQ7 : ADSEQ7
bits : 24 - 52 (29 bit)
access : read-write

RESERVED : Reserved.
bits : 29 - 60 (32 bit)
access : read-write


ADC_DMAR (DMAR)

ADC_DMAR
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_DMAR ADC_DMAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDMAS ADDMAG ADDMAC RESERVED

ADDMAS : ADDMAS
bits : 0 - 0 (1 bit)
access : read-write

ADDMAG : ADDMAG
bits : 1 - 2 (2 bit)
access : read-write

ADDMAC : ADDMAC
bits : 2 - 4 (3 bit)
access : read-write

RESERVED : Reserved.
bits : 3 - 34 (32 bit)
access : read-write


ADC_OFR0 (OFR0)

ADC_OFR0
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_OFR0 ADC_OFR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADOF0 ADOFE0 RESERVED

ADOF0 : ADOF0
bits : 0 - 11 (12 bit)
access : read-write

ADOFE0 : ADOFE0
bits : 15 - 30 (16 bit)
access : read-write

RESERVED : Reserved.
bits : 16 - 47 (32 bit)
access : read-write


ADC_OFR1 (OFR1)

ADC_OFR1
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_OFR1 ADC_OFR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADOF1 ADOFE1 RESERVED

ADOF1 : ADOF1
bits : 0 - 11 (12 bit)
access : read-write

ADOFE1 : ADOFE1
bits : 15 - 30 (16 bit)
access : read-write

RESERVED : Reserved.
bits : 16 - 47 (32 bit)
access : read-write


ADC_OFR2 (OFR2)

ADC_OFR2
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_OFR2 ADC_OFR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADOF2 ADOFE2 RESERVED

ADOF2 : ADOF2
bits : 0 - 11 (12 bit)
access : read-write

ADOFE2 : ADOFE2
bits : 15 - 30 (16 bit)
access : read-write

RESERVED : Reserved.
bits : 16 - 47 (32 bit)
access : read-write


ADC_OFR3 (OFR3)

ADC_OFR3
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_OFR3 ADC_OFR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADOF3 ADOFE3 RESERVED

ADOF3 : ADOF3
bits : 0 - 11 (12 bit)
access : read-write

ADOFE3 : ADOFE3
bits : 15 - 30 (16 bit)
access : read-write

RESERVED : Reserved.
bits : 16 - 47 (32 bit)
access : read-write


ADC_RST (RST)

ADC_RST
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_RST ADC_RST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADRST RESERVED

ADRST : ADRST
bits : 0 - 0 (1 bit)
access : read-write

RESERVED : Reserved.
bits : 1 - 32 (32 bit)
access : read-write


ADC_OFR4 (OFR4)

ADC_OFR4
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_OFR4 ADC_OFR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADOF4 ADOFE4 RESERVED

ADOF4 : ADOF4
bits : 0 - 11 (12 bit)
access : read-write

ADOFE4 : ADOFE4
bits : 15 - 30 (16 bit)
access : read-write

RESERVED : Reserved.
bits : 16 - 47 (32 bit)
access : read-write


ADC_OFR5 (OFR5)

ADC_OFR5
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_OFR5 ADC_OFR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADOF5 ADOFE5 RESERVED

ADOF5 : ADOF5
bits : 0 - 11 (12 bit)
access : read-write

ADOFE5 : ADOFE5
bits : 15 - 30 (16 bit)
access : read-write

RESERVED : Reserved.
bits : 16 - 47 (32 bit)
access : read-write


ADC_OFR6 (OFR6)

ADC_OFR6
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_OFR6 ADC_OFR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADOF6 ADOFE6 RESERVED

ADOF6 : ADOF6
bits : 0 - 11 (12 bit)
access : read-write

ADOFE6 : ADOFE6
bits : 15 - 30 (16 bit)
access : read-write

RESERVED : Reserved.
bits : 16 - 47 (32 bit)
access : read-write


ADC_OFR7 (OFR7)

ADC_OFR7
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_OFR7 ADC_OFR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADOF7 ADOFE7 RESERVED

ADOF7 : ADOF7
bits : 0 - 11 (12 bit)
access : read-write

ADOFE7 : ADOFE7
bits : 15 - 30 (16 bit)
access : read-write

RESERVED : Reserved.
bits : 16 - 47 (32 bit)
access : read-write


ADC_STR0 (STR0)

ADC_STR0
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_STR0 ADC_STR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADST0 RESERVED

ADST0 : ADST0
bits : 0 - 7 (8 bit)
access : read-write

RESERVED : Reserved.
bits : 8 - 39 (32 bit)
access : read-write


ADC_STR1 (STR1)

ADC_STR1
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_STR1 ADC_STR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADST1 RESERVED

ADST1 : ADST1
bits : 0 - 7 (8 bit)
access : read-write

RESERVED : Reserved.
bits : 8 - 39 (32 bit)
access : read-write


ADC_STR2 (STR2)

ADC_STR2
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_STR2 ADC_STR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADST2 RESERVED

ADST2 : ADST2
bits : 0 - 7 (8 bit)
access : read-write

RESERVED : Reserved.
bits : 8 - 39 (32 bit)
access : read-write


ADC_STR3 (STR3)

ADC_STR3
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_STR3 ADC_STR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADST3 RESERVED

ADST3 : ADST3
bits : 0 - 7 (8 bit)
access : read-write

RESERVED : Reserved.
bits : 8 - 39 (32 bit)
access : read-write


ADC_CONV (CONV)

ADC_CONV
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_CONV ADC_CONV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADMODE ADSEQL ADSUBL RESERVED

ADMODE : ADMODE
bits : 0 - 1 (2 bit)
access : read-write

ADSEQL : ADSEQL
bits : 8 - 18 (11 bit)
access : read-write

ADSUBL : ADSUBL
bits : 16 - 34 (19 bit)
access : read-write

RESERVED : Reserved.
bits : 19 - 50 (32 bit)
access : read-write


ADC_STR4 (STR4)

ADC_STR4
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_STR4 ADC_STR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADST4 RESERVED

ADST4 : ADST4
bits : 0 - 7 (8 bit)
access : read-write

RESERVED : Reserved.
bits : 8 - 39 (32 bit)
access : read-write


ADC_STR5 (STR5)

ADC_STR5
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_STR5 ADC_STR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADST5 RESERVED

ADST5 : ADST5
bits : 0 - 7 (8 bit)
access : read-write

RESERVED : Reserved.
bits : 8 - 39 (32 bit)
access : read-write


ADC_STR6 (STR6)

ADC_STR6
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_STR6 ADC_STR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADST6 RESERVED

ADST6 : ADST6
bits : 0 - 7 (8 bit)
access : read-write

RESERVED : Reserved.
bits : 8 - 39 (32 bit)
access : read-write


ADC_STR7 (STR7)

ADC_STR7
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_STR7 ADC_STR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADST7 RESERVED

ADST7 : ADST7
bits : 0 - 7 (8 bit)
access : read-write

RESERVED : Reserved.
bits : 8 - 39 (32 bit)
access : read-write


ADC_DR0 (DR0)

ADC_DR0
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_DR0 ADC_DR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADD0 ADVLD0

ADD0 : ADD0
bits : 0 - 15 (16 bit)
access : read-write

ADVLD0 : ADVLD0
bits : 31 - 62 (32 bit)
access : read-write


ADC_DR1 (DR1)

ADC_DR1
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_DR1 ADC_DR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADD1 ADVLD1

ADD1 : ADD1
bits : 0 - 15 (16 bit)
access : read-write

ADVLD1 : ADVLD1
bits : 31 - 62 (32 bit)
access : read-write


ADC_DR2 (DR2)

ADC_DR2
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_DR2 ADC_DR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADD2 ADVLD2

ADD2 : ADD2
bits : 0 - 15 (16 bit)
access : read-write

ADVLD2 : ADVLD2
bits : 31 - 62 (32 bit)
access : read-write


ADC_DR3 (DR3)

ADC_DR3
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_DR3 ADC_DR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADD3 ADVLD3

ADD3 : ADD3
bits : 0 - 15 (16 bit)
access : read-write

ADVLD3 : ADVLD3
bits : 31 - 62 (32 bit)
access : read-write


ADC_DR4 (DR4)

ADC_DR4
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_DR4 ADC_DR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADD4 ADVLD4

ADD4 : ADD4
bits : 0 - 15 (16 bit)
access : read-write

ADVLD4 : ADVLD4
bits : 31 - 62 (32 bit)
access : read-write


ADC_DR5 (DR5)

ADC_DR5
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_DR5 ADC_DR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADD5 ADVLD5

ADD5 : ADD5
bits : 0 - 15 (16 bit)
access : read-write

ADVLD5 : ADVLD5
bits : 31 - 62 (32 bit)
access : read-write


ADC_DR6 (DR6)

ADC_DR6
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_DR6 ADC_DR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADD6 ADVLD6

ADD6 : ADD6
bits : 0 - 15 (16 bit)
access : read-write

ADVLD6 : ADVLD6
bits : 31 - 62 (32 bit)
access : read-write


ADC_DR7 (DR7)

ADC_DR7
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_DR7 ADC_DR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADD7 ADVLD7

ADD7 : ADD7
bits : 0 - 15 (16 bit)
access : read-write

ADVLD7 : ADVLD7
bits : 31 - 62 (32 bit)
access : read-write



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