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SPI

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

SPI0_CR0 (CR0)

SPI_CR0

SPI0_DR (DR)

SPI_DR

SPI0_SR (SR)

SPI_SR

SPI0_FCR (FCR)

SPI_FCR

SPI0_FSR (FSR)

SPI_FSR

SPI0_FTOCR (FTOCR)

SPI_FTOCR

SPI0_CR1 (CR1)

SPI_CR1

SPI0_IER (IER)

SPI_IER

SPI0_CPR (CPR)

SPI_CPR


SPI0_CR0 (CR0)

SPI0_CR0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPI0_CR0 SPI0_CR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPIEN TXDMAE RXDMAE SELOEN SSELC RESERVED

SPIEN : SPIEN
bits : 0 - 0 (1 bit)
access : read-write

TXDMAE : TXDMAE
bits : 1 - 2 (2 bit)
access : read-write

RXDMAE : RXDMAE
bits : 2 - 4 (3 bit)
access : read-write

SELOEN : SELOEN
bits : 3 - 6 (4 bit)
access : read-write

SSELC : SSELC
bits : 4 - 8 (5 bit)
access : read-write

RESERVED : Reserved.
bits : 5 - 36 (32 bit)
access : read-write


SPI_CR0

SPI_CR0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPI_CR0 SPI_CR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPIEN TXDMAE RXDMAE SELOEN SSELC

SPIEN : SPIEN
bits : 0 - 0 (1 bit)
access : read-write

TXDMAE : TXDMAE
bits : 1 - 2 (2 bit)
access : read-write

RXDMAE : RXDMAE
bits : 2 - 4 (3 bit)
access : read-write

SELOEN : SELOEN
bits : 3 - 6 (4 bit)
access : read-write

SSELC : SSELC
bits : 4 - 8 (5 bit)
access : read-write


SPI0_DR (DR)

SPI0_DR
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPI0_DR SPI0_DR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DR RESERVED

DR : DR
bits : 0 - 15 (16 bit)
access : read-write

RESERVED : Reserved.
bits : 16 - 47 (32 bit)
access : read-write


SPI_DR

SPI_DR
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPI_DR SPI_DR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DR

DR : DR
bits : 0 - 15 (16 bit)
access : read-write


SPI0_SR (SR)

SPI0_SR
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPI0_SR SPI0_SR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXBE TXE RXBNE WC RO MF SA TO BUSY RESERVED

TXBE : TXBE
bits : 0 - 0 (1 bit)
access : read-write

TXE : TXE
bits : 1 - 2 (2 bit)
access : read-write

RXBNE : RXBNE
bits : 2 - 4 (3 bit)
access : read-write

WC : WC
bits : 3 - 6 (4 bit)
access : read-write

RO : RO
bits : 4 - 8 (5 bit)
access : read-write

MF : MF
bits : 5 - 10 (6 bit)
access : read-write

SA : SA
bits : 6 - 12 (7 bit)
access : read-write

TO : TO
bits : 7 - 14 (8 bit)
access : read-write

BUSY : BUSY
bits : 8 - 16 (9 bit)
access : read-write

RESERVED : Reserved.
bits : 9 - 40 (32 bit)
access : read-write


SPI_SR

SPI_SR
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPI_SR SPI_SR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXBE TXE RXBNE WC RO MF SA TO BUSY

TXBE : TXBE
bits : 0 - 0 (1 bit)
access : read-write

TXE : TXE
bits : 1 - 2 (2 bit)
access : read-write

RXBNE : RXBNE
bits : 2 - 4 (3 bit)
access : read-write

WC : WC
bits : 3 - 6 (4 bit)
access : read-write

RO : RO
bits : 4 - 8 (5 bit)
access : read-write

MF : MF
bits : 5 - 10 (6 bit)
access : read-write

SA : SA
bits : 6 - 12 (7 bit)
access : read-write

TO : TO
bits : 7 - 14 (8 bit)
access : read-write

BUSY : BUSY
bits : 8 - 16 (9 bit)
access : read-write


SPI0_FCR (FCR)

SPI0_FCR
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPI0_FCR SPI0_FCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXFTLS RXFTLS TFPR RFPR FIFOEN RESERVED

TXFTLS : TXFTLS
bits : 0 - 3 (4 bit)
access : read-write

RXFTLS : RXFTLS
bits : 4 - 11 (8 bit)
access : read-write

TFPR : TFPR
bits : 8 - 16 (9 bit)
access : read-write

RFPR : RFPR
bits : 9 - 18 (10 bit)
access : read-write

FIFOEN : FIFOEN
bits : 10 - 20 (11 bit)
access : read-write

RESERVED : Reserved.
bits : 11 - 42 (32 bit)
access : read-write


SPI_FCR

SPI_FCR
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPI_FCR SPI_FCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXFTLS RXFTLS TFPR RFPR FIFOEN

TXFTLS : TXFTLS
bits : 0 - 3 (4 bit)
access : read-write

RXFTLS : RXFTLS
bits : 4 - 11 (8 bit)
access : read-write

TFPR : TFPR
bits : 8 - 16 (9 bit)
access : read-write

RFPR : RFPR
bits : 9 - 18 (10 bit)
access : read-write

FIFOEN : FIFOEN
bits : 10 - 20 (11 bit)
access : read-write


SPI0_FSR (FSR)

SPI0_FSR
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPI0_FSR SPI0_FSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXFS RXFS RESERVED

TXFS : TXFS
bits : 0 - 3 (4 bit)
access : read-write

RXFS : RXFS
bits : 4 - 11 (8 bit)
access : read-write

RESERVED : Reserved.
bits : 8 - 39 (32 bit)
access : read-write


SPI_FSR

SPI_FSR
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPI_FSR SPI_FSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXFS RXFS

TXFS : TXFS
bits : 0 - 3 (4 bit)
access : read-write

RXFS : RXFS
bits : 4 - 11 (8 bit)
access : read-write


SPI0_FTOCR (FTOCR)

SPI0_FTOCR
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPI0_FTOCR SPI0_FTOCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TOC

TOC : TOC
bits : 0 - 31 (32 bit)
access : read-write


SPI_FTOCR

SPI_FTOCR
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPI_FTOCR SPI_FTOCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TOC

TOC : TOC
bits : 0 - 31 (32 bit)
access : read-write


SPI0_CR1 (CR1)

SPI0_CR1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPI0_CR1 SPI0_CR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DFL FORMAT SELAP FIRSTBIT SELM MODE RESERVED

DFL : DFL
bits : 0 - 3 (4 bit)
access : read-write

FORMAT : FORMAT
bits : 8 - 18 (11 bit)
access : read-write

SELAP : SELAP
bits : 11 - 22 (12 bit)
access : read-write

FIRSTBIT : FIRSTBIT
bits : 12 - 24 (13 bit)
access : read-write

SELM : SELM
bits : 13 - 26 (14 bit)
access : read-write

MODE : MODE
bits : 14 - 28 (15 bit)
access : read-write

RESERVED : Reserved.
bits : 15 - 46 (32 bit)
access : read-write


SPI_CR1

SPI_CR1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPI_CR1 SPI_CR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DFL FORMAT SELAP FIRSTBIT SELM MODE

DFL : DFL
bits : 0 - 3 (4 bit)
access : read-write

FORMAT : FORMAT
bits : 8 - 18 (11 bit)
access : read-write

SELAP : SELAP
bits : 11 - 22 (12 bit)
access : read-write

FIRSTBIT : FIRSTBIT
bits : 12 - 24 (13 bit)
access : read-write

SELM : SELM
bits : 13 - 26 (14 bit)
access : read-write

MODE : MODE
bits : 14 - 28 (15 bit)
access : read-write


SPI0_IER (IER)

SPI0_IER
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPI0_IER SPI0_IER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXBEIEN TXEIEN RXBNEIEN WCIEN ROIEN MFIEN SAIEN TOIEN RESERVED

TXBEIEN : TXBEIEN
bits : 0 - 0 (1 bit)
access : read-write

TXEIEN : TXEIEN
bits : 1 - 2 (2 bit)
access : read-write

RXBNEIEN : RXBNEIEN
bits : 2 - 4 (3 bit)
access : read-write

WCIEN : WCIEN
bits : 3 - 6 (4 bit)
access : read-write

ROIEN : ROIEN
bits : 4 - 8 (5 bit)
access : read-write

MFIEN : MFIEN
bits : 5 - 10 (6 bit)
access : read-write

SAIEN : SAIEN
bits : 6 - 12 (7 bit)
access : read-write

TOIEN : TOIEN
bits : 7 - 14 (8 bit)
access : read-write

RESERVED : Reserved.
bits : 8 - 39 (32 bit)
access : read-write


SPI_IER

SPI_IER
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPI_IER SPI_IER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXBEIEN TXEIEN RXBNEIEN WCIEN ROIEN MFIEN SAIEN TOIEN

TXBEIEN : TXBEIEN
bits : 0 - 0 (1 bit)
access : read-write

TXEIEN : TXEIEN
bits : 1 - 2 (2 bit)
access : read-write

RXBNEIEN : RXBNEIEN
bits : 2 - 4 (3 bit)
access : read-write

WCIEN : WCIEN
bits : 3 - 6 (4 bit)
access : read-write

ROIEN : ROIEN
bits : 4 - 8 (5 bit)
access : read-write

MFIEN : MFIEN
bits : 5 - 10 (6 bit)
access : read-write

SAIEN : SAIEN
bits : 6 - 12 (7 bit)
access : read-write

TOIEN : TOIEN
bits : 7 - 14 (8 bit)
access : read-write


SPI0_CPR (CPR)

SPI0_CPR
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPI0_CPR SPI0_CPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CP RESERVED

CP : CP
bits : 0 - 15 (16 bit)
access : read-write

RESERVED : Reserved.
bits : 16 - 47 (32 bit)
access : read-write


SPI_CPR

SPI_CPR
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPI_CPR SPI_CPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CP

CP : CP
bits : 0 - 15 (16 bit)
access : read-write



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