\n

CSIF

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CSIF_ENR (ENR)

CSIF_WCR1 (WCR1)

CSIF_SMP (SMP)

CSIF_SMPCOL (SMPCOL)

CSIF_SMPROW (SMPROW)

CSIF_FIFO0 (FIFO0)

CSIF_FIFO1 (FIFO1)

CSIF_FIFO2 (FIFO2)

CSIF_FIFO3 (FIFO3)

CSIF_FIFO4 (FIFO4)

CSIF_FIFO5 (FIFO5)

CSIF_FIFO6 (FIFO6)

CSIF_FIFO7 (FIFO7)

CSIF_CR (CR)

CSIF_IER (IER)

CSIF_SR (SR)

CSIF_IMGWH (IMGWH)

CSIF_WCR0 (WCR0)


CSIF_ENR (ENR)

CSIF_ENR
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSIF_ENR CSIF_ENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED CSIF_EN

RESERVED : Reserved.
bits : 0 - 30 (31 bit)
access : read-write

CSIF_EN : CSIF_EN
bits : 31 - 62 (32 bit)
access : read-write


CSIF_WCR1 (WCR1)

CSIF_WCR1
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSIF_WCR1 CSIF_WCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WIN_WID WIN_HGH RESERVED

WIN_WID : WIN_WID
bits : 0 - 10 (11 bit)
access : read-write

WIN_HGH : WIN_HGH
bits : 16 - 42 (27 bit)
access : read-write

RESERVED : Reserved.
bits : 27 - 58 (32 bit)
access : read-write


CSIF_SMP (SMP)

CSIF_SMP
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSIF_SMP CSIF_SMP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSML RSML SMP_EN

CSML : CSML
bits : 8 - 20 (13 bit)
access : read-write

RSML : RSML
bits : 16 - 36 (21 bit)
access : read-write

SMP_EN : SMP_EN
bits : 31 - 62 (32 bit)
access : read-write


CSIF_SMPCOL (SMPCOL)

CSIF_SMPCOL
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSIF_SMPCOL CSIF_SMPCOL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSM

CSM : CSM
bits : 0 - 31 (32 bit)
access : read-write


CSIF_SMPROW (SMPROW)

CSIF_SMPROW
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSIF_SMPROW CSIF_SMPROW read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSM

RSM : RSM
bits : 0 - 31 (32 bit)
access : read-write


CSIF_FIFO0 (FIFO0)

CSIF_FIFO0
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSIF_FIFO0 CSIF_FIFO0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FIFODATA

FIFODATA : FIFODATA
bits : 0 - 31 (32 bit)
access : read-write


CSIF_FIFO1 (FIFO1)

CSIF_FIFO1
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSIF_FIFO1 CSIF_FIFO1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FIFODATA

FIFODATA : FIFODATA
bits : 0 - 31 (32 bit)
access : read-write


CSIF_FIFO2 (FIFO2)

CSIF_FIFO2
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSIF_FIFO2 CSIF_FIFO2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FIFODATA

FIFODATA : FIFODATA
bits : 0 - 31 (32 bit)
access : read-write


CSIF_FIFO3 (FIFO3)

CSIF_FIFO3
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSIF_FIFO3 CSIF_FIFO3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FIFODATA

FIFODATA : FIFODATA
bits : 0 - 31 (32 bit)
access : read-write


CSIF_FIFO4 (FIFO4)

CSIF_FIFO4
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSIF_FIFO4 CSIF_FIFO4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FIFODATA

FIFODATA : FIFODATA
bits : 0 - 31 (32 bit)
access : read-write


CSIF_FIFO5 (FIFO5)

CSIF_FIFO5
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSIF_FIFO5 CSIF_FIFO5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FIFODATA

FIFODATA : FIFODATA
bits : 0 - 31 (32 bit)
access : read-write


CSIF_FIFO6 (FIFO6)

CSIF_FIFO6
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSIF_FIFO6 CSIF_FIFO6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FIFODATA

FIFODATA : FIFODATA
bits : 0 - 31 (32 bit)
access : read-write


CSIF_FIFO7 (FIFO7)

CSIF_FIFO7
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSIF_FIFO7 CSIF_FIFO7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FIFODATA

FIFODATA : FIFODATA
bits : 0 - 31 (32 bit)
access : read-write


CSIF_CR (CR)

CSIF_CR
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSIF_CR CSIF_CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSYNCTYP HSYNCTYP CLKEDGE IMG_FMT VSYNCPOL HSYNCPOL IMG_SLD IMG_SFD RESERVED

VSYNCTYP : VSYNCTYP
bits : 1 - 2 (2 bit)
access : read-write

HSYNCTYP : HSYNCTYP
bits : 2 - 4 (3 bit)
access : read-write

CLKEDGE : CLKEDGE
bits : 3 - 6 (4 bit)
access : read-write

IMG_FMT : IMG_FMT
bits : 4 - 8 (5 bit)
access : read-write

VSYNCPOL : VSYNCPOL
bits : 6 - 12 (7 bit)
access : read-write

HSYNCPOL : HSYNCPOL
bits : 7 - 14 (8 bit)
access : read-write

IMG_SLD : IMG_SLD
bits : 8 - 23 (16 bit)
access : read-write

IMG_SFD : IMG_SFD
bits : 16 - 39 (24 bit)
access : read-write

RESERVED : Reserved.
bits : 24 - 55 (32 bit)
access : read-write


CSIF_IER (IER)

CSIF_IER
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSIF_IER CSIF_IER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOFFLGE EOFFLGE CAPSTAE CAPSTSE BADFRME FIFOOVRE FIFOEMPE FIFOFULE RESERVED

SOFFLGE : SOFFLGE
bits : 0 - 0 (1 bit)
access : read-write

EOFFLGE : EOFFLGE
bits : 1 - 2 (2 bit)
access : read-write

CAPSTAE : CAPSTAE
bits : 2 - 4 (3 bit)
access : read-write

CAPSTSE : CAPSTSE
bits : 3 - 6 (4 bit)
access : read-write

BADFRME : BADFRME
bits : 4 - 8 (5 bit)
access : read-write

FIFOOVRE : FIFOOVRE
bits : 8 - 16 (9 bit)
access : read-write

FIFOEMPE : FIFOEMPE
bits : 9 - 18 (10 bit)
access : read-write

FIFOFULE : FIFOFULE
bits : 10 - 20 (11 bit)
access : read-write

RESERVED : Reserved.
bits : 11 - 42 (32 bit)
access : read-write


CSIF_SR (SR)

CSIF_SR
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSIF_SR CSIF_SR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOF_FLG EOF_FLG CAP_STA CAP_STS BAD_FRM FIFO_OVR FIFO_EMP FIFO_FUL RESERVED

SOF_FLG : SOF_FLG
bits : 0 - 0 (1 bit)
access : read-write

EOF_FLG : EOF_FLG
bits : 1 - 2 (2 bit)
access : read-write

CAP_STA : CAP_STA
bits : 2 - 4 (3 bit)
access : read-write

CAP_STS : CAP_STS
bits : 3 - 6 (4 bit)
access : read-write

BAD_FRM : BAD_FRM
bits : 4 - 8 (5 bit)
access : read-write

FIFO_OVR : FIFO_OVR
bits : 8 - 16 (9 bit)
access : read-write

FIFO_EMP : FIFO_EMP
bits : 9 - 18 (10 bit)
access : read-write

FIFO_FUL : FIFO_FUL
bits : 10 - 20 (11 bit)
access : read-write

RESERVED : Reserved.
bits : 11 - 42 (32 bit)
access : read-write


CSIF_IMGWH (IMGWH)

CSIF_IMGWH
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSIF_IMGWH CSIF_IMGWH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IMG_WID IMG_HGH RESERVED

IMG_WID : IMG_WID
bits : 0 - 10 (11 bit)
access : read-write

IMG_HGH : IMG_HGH
bits : 16 - 42 (27 bit)
access : read-write

RESERVED : Reserved.
bits : 27 - 58 (32 bit)
access : read-write


CSIF_WCR0 (WCR0)

CSIF_WCR0
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSIF_WCR0 CSIF_WCR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WIN_HSTR WIN_VSTR WIN_EN

WIN_HSTR : WIN_HSTR
bits : 0 - 10 (11 bit)
access : read-write

WIN_VSTR : WIN_VSTR
bits : 16 - 42 (27 bit)
access : read-write

WIN_EN : WIN_EN
bits : 31 - 62 (32 bit)
access : read-write



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.