\n
Transmit Data Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Transmit data
bits : 0 - 7 (8 bit)
full : Transmit FIFO full
bits : 31 - 62 (32 bit)
Interrupt Enable Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
txwm : Transmit watermark interrupt enable
bits : 0 - 0 (1 bit)
rxwm : Receive watermark interrupt enable
bits : 1 - 2 (2 bit)
Interrupt Pending Register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
txwm : Transmit watermark interrupt pending
bits : 0 - 0 (1 bit)
rxwm : Receive watermark interrupt pending
bits : 1 - 2 (2 bit)
Baud Rate Divisor Register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
div : Baud rate divisor
bits : 0 - 15 (16 bit)
Receive Data Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Received data
bits : 0 - 7 (8 bit)
empty : Receive FIFO empty
bits : 31 - 62 (32 bit)
Transmit Control Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
txen : Transmit enable
bits : 0 - 0 (1 bit)
nstop : Number of stop bits
bits : 1 - 2 (2 bit)
txcnt : Transmit watermark level
bits : 16 - 34 (19 bit)
Receive Control Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
rxen : Receive enable
bits : 0 - 0 (1 bit)
rxcnt : Receive watermark level
bits : 16 - 34 (19 bit)
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