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UARTHS

Peripheral Memory Blocks

Registers

txdata

ie

ip

div

rxdata

txctrl

rxctrl


txdata

Transmit Data Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

txdata txdata read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data full

data : Transmit data
bits : 0 - 7 (8 bit)

full : Transmit FIFO full
bits : 31 - 62 (32 bit)


ie

Interrupt Enable Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ie ie read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txwm rxwm

txwm : Transmit watermark interrupt enable
bits : 0 - 0 (1 bit)

rxwm : Receive watermark interrupt enable
bits : 1 - 2 (2 bit)


ip

Interrupt Pending Register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ip ip read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txwm rxwm

txwm : Transmit watermark interrupt pending
bits : 0 - 0 (1 bit)

rxwm : Receive watermark interrupt pending
bits : 1 - 2 (2 bit)


div

Baud Rate Divisor Register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

div div read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 div

div : Baud rate divisor
bits : 0 - 15 (16 bit)


rxdata

Receive Data Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

rxdata rxdata read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data empty

data : Received data
bits : 0 - 7 (8 bit)

empty : Receive FIFO empty
bits : 31 - 62 (32 bit)


txctrl

Transmit Control Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

txctrl txctrl read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txen nstop txcnt

txen : Transmit enable
bits : 0 - 0 (1 bit)

nstop : Number of stop bits
bits : 1 - 2 (2 bit)

txcnt : Transmit watermark level
bits : 16 - 34 (19 bit)


rxctrl

Receive Control Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

rxctrl rxctrl read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rxen rxcnt

rxen : Receive enable
bits : 0 - 0 (1 bit)

rxcnt : Receive watermark level
bits : 16 - 34 (19 bit)



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