\n
address_offset : 0x0 Bytes (0x0)
size : 0x2C byte (0x0)
mem_usage : registers
protection : not protected
Timerx Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CK_PSCx : HRTIM Timer x Clock prescaler
bits : 0 - 2 (3 bit)
CONT : Continuous mode
bits : 3 - 3 (1 bit)
RETRIG : Re-triggerable mode
bits : 4 - 4 (1 bit)
HALF : Half mode enable
bits : 5 - 5 (1 bit)
PSHPLL : Push-Pull mode enable
bits : 6 - 6 (1 bit)
INTLVD : Interleaved mode
bits : 7 - 8 (2 bit)
RSYNCU : Re-Synchronized Update
bits : 9 - 9 (1 bit)
SYNCRSTx : Synchronization Resets Timer x
bits : 10 - 10 (1 bit)
SYNCSTRTx : Synchronization Starts Timer x
bits : 11 - 11 (1 bit)
DELCMP2 : Delayed CMP2 mode
bits : 12 - 13 (2 bit)
DELCMP4 : Delayed CMP4 mode
bits : 14 - 15 (2 bit)
TFU : TFU
bits : 16 - 16 (1 bit)
TxREPU : Timer x Repetition update
bits : 17 - 17 (1 bit)
TxRSTU : Timerx reset update
bits : 18 - 18 (1 bit)
TAU : TAU
bits : 19 - 19 (1 bit)
TBU : TBU
bits : 20 - 20 (1 bit)
TCU : TCU
bits : 21 - 21 (1 bit)
TEU : TEU
bits : 23 - 23 (1 bit)
MSTU : Master Timer update
bits : 24 - 24 (1 bit)
DACSYNC : AC Synchronization
bits : 25 - 26 (2 bit)
PREEN : Preload enable
bits : 27 - 27 (1 bit)
UPDGAT : Update Gating
bits : 28 - 31 (4 bit)
Timerx Counter Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNTx : Timerx Counter value
bits : 0 - 15 (16 bit)
Timerx Period Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERx : Timerx Period value
bits : 0 - 15 (16 bit)
Timerx Repetition Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REPx : Timerx Repetition counter value
bits : 0 - 7 (8 bit)
Timerx Compare 1 Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMP1x : Timerx Compare 1 value
bits : 0 - 15 (16 bit)
Timerx Compare 1 Compound Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMP1x : Timerx Compare 1 value
bits : 0 - 15 (16 bit)
REPx : Timerx Repetition value (aliased from HRTIM_REPx register)
bits : 16 - 23 (8 bit)
Timerx Compare 2 Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMP2x : Timerx Compare 2 value
bits : 0 - 15 (16 bit)
Timerx Compare 3 Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMP3x : Timerx Compare 3 value
bits : 0 - 15 (16 bit)
Timerx Compare 4 Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMP4x : Timerx Compare 4 value
bits : 0 - 15 (16 bit)
Timerx Capture 1 Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CPT1x : Timerx Capture 1 value
bits : 0 - 15 (16 bit)
DIR : Timerx Capture 1 Direction status
bits : 16 - 16 (1 bit)
Timerx Capture 2 Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CPT2x : Timerx Capture 2 value
bits : 0 - 15 (16 bit)
DIR : Timerx Capture 1 Direction status
bits : 16 - 16 (1 bit)
Timerx Deadtime Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTRx : Deadtime Rising value
bits : 0 - 8 (9 bit)
SDTRx : Sign Deadtime Rising value
bits : 9 - 9 (1 bit)
DTPRSC : Deadtime Prescaler
bits : 10 - 12 (3 bit)
DTRSLKx : Deadtime Rising Sign Lock
bits : 14 - 14 (1 bit)
DTRLKx : Deadtime Rising Lock
bits : 15 - 15 (1 bit)
DTFx : Deadtime Falling value
bits : 16 - 24 (9 bit)
SDTFx : Sign Deadtime Falling value
bits : 25 - 25 (1 bit)
DTFSLKx : Deadtime Falling Sign Lock
bits : 30 - 30 (1 bit)
DTFLKx : Deadtime Falling Lock
bits : 31 - 31 (1 bit)
Timerx Output1 Set Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SST : Software Set trigger
bits : 0 - 0 (1 bit)
RESYNC : Timer A resynchronizaton
bits : 1 - 1 (1 bit)
PER : Timer A Period
bits : 2 - 2 (1 bit)
CMP1 : Timer A compare 1
bits : 3 - 3 (1 bit)
CMP2 : Timer A compare 2
bits : 4 - 4 (1 bit)
CMP3 : Timer A compare 3
bits : 5 - 5 (1 bit)
CMP4 : Timer A compare 4
bits : 6 - 6 (1 bit)
MSTPER : Master Period
bits : 7 - 7 (1 bit)
MSTCMP1 : Master Compare 1
bits : 8 - 8 (1 bit)
MSTCMP2 : Master Compare 2
bits : 9 - 9 (1 bit)
MSTCMP3 : Master Compare 3
bits : 10 - 10 (1 bit)
MSTCMP4 : Master Compare 4
bits : 11 - 11 (1 bit)
TIMEVNT1 : Timer Event 1
bits : 12 - 12 (1 bit)
TIMEVNT2 : Timer Event 2
bits : 13 - 13 (1 bit)
TIMEVNT3 : Timer Event 3
bits : 14 - 14 (1 bit)
TIMEVNT4 : Timer Event 4
bits : 15 - 15 (1 bit)
TIMEVNT5 : Timer Event 5
bits : 16 - 16 (1 bit)
TIMEVNT6 : Timer Event 6
bits : 17 - 17 (1 bit)
TIMEVNT7 : Timer Event 7
bits : 18 - 18 (1 bit)
TIMEVNT8 : Timer Event 8
bits : 19 - 19 (1 bit)
TIMEVNT9 : Timer Event 9
bits : 20 - 20 (1 bit)
EXTEVNT1 : External Event 1
bits : 21 - 21 (1 bit)
EXTEVNT2 : External Event 2
bits : 22 - 22 (1 bit)
EXTEVNT3 : External Event 3
bits : 23 - 23 (1 bit)
EXTEVNT4 : External Event 4
bits : 24 - 24 (1 bit)
EXTEVNT5 : External Event 5
bits : 25 - 25 (1 bit)
EXTEVNT6 : External Event 6
bits : 26 - 26 (1 bit)
EXTEVNT7 : External Event 7
bits : 27 - 27 (1 bit)
EXTEVNT8 : External Event 8
bits : 28 - 28 (1 bit)
EXTEVNT9 : External Event 9
bits : 29 - 29 (1 bit)
EXTEVNT10 : External Event 10
bits : 30 - 30 (1 bit)
UPDATE : Registers update (transfer preload to active)
bits : 31 - 31 (1 bit)
Timerx Interrupt Status Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CMP1 : Compare 1 Interrupt Flag
bits : 0 - 0 (1 bit)
CMP2 : Compare 2 Interrupt Flag
bits : 1 - 1 (1 bit)
CMP3 : Compare 3 Interrupt Flag
bits : 2 - 2 (1 bit)
CMP4 : Compare 4 Interrupt Flag
bits : 3 - 3 (1 bit)
REP : Repetition Interrupt Flag
bits : 4 - 4 (1 bit)
UPD : Update Interrupt Flag
bits : 6 - 6 (1 bit)
CPT1 : Capture1 Interrupt Flag
bits : 7 - 7 (1 bit)
CPT2 : Capture2 Interrupt Flag
bits : 8 - 8 (1 bit)
SETx1 : Output 1 Set Interrupt Flag
bits : 9 - 9 (1 bit)
RSTx1 : Output 1 Reset Interrupt Flag
bits : 10 - 10 (1 bit)
SETx2 : Output 2 Set Interrupt Flag
bits : 11 - 11 (1 bit)
RSTx2 : Output 2 Reset Interrupt Flag
bits : 12 - 12 (1 bit)
RST : Reset Interrupt Flag
bits : 13 - 13 (1 bit)
DLYPRT : Delayed Protection Flag
bits : 14 - 14 (1 bit)
CPPSTAT : Current Push Pull Status
bits : 16 - 16 (1 bit)
IPPSTAT : Idle Push Pull Status
bits : 17 - 17 (1 bit)
O1STAT : Output 1 State
bits : 18 - 18 (1 bit)
O2STAT : Output 2 State
bits : 19 - 19 (1 bit)
O1CPY : Output 1 Copy
bits : 20 - 20 (1 bit)
O2CPY : Output 2 Copy
bits : 21 - 21 (1 bit)
Timerx Output1 Reset Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRT : SRT
bits : 0 - 0 (1 bit)
RESYNC : RESYNC
bits : 1 - 1 (1 bit)
PER : PER
bits : 2 - 2 (1 bit)
CMP1 : CMP1
bits : 3 - 3 (1 bit)
CMP2 : CMP2
bits : 4 - 4 (1 bit)
CMP3 : CMP3
bits : 5 - 5 (1 bit)
CMP4 : CMP4
bits : 6 - 6 (1 bit)
MSTPER : MSTPER
bits : 7 - 7 (1 bit)
MSTCMP1 : MSTCMP1
bits : 8 - 8 (1 bit)
MSTCMP2 : MSTCMP2
bits : 9 - 9 (1 bit)
MSTCMP3 : MSTCMP3
bits : 10 - 10 (1 bit)
MSTCMP4 : MSTCMP4
bits : 11 - 11 (1 bit)
TIMEVNT1 : TIMEVNT1
bits : 12 - 12 (1 bit)
TIMEVNT2 : TIMEVNT2
bits : 13 - 13 (1 bit)
TIMEVNT3 : TIMEVNT3
bits : 14 - 14 (1 bit)
TIMEVNT4 : TIMEVNT4
bits : 15 - 15 (1 bit)
TIMEVNT5 : TIMEVNT5
bits : 16 - 16 (1 bit)
TIMEVNT6 : TIMEVNT6
bits : 17 - 17 (1 bit)
TIMEVNT7 : TIMEVNT7
bits : 18 - 18 (1 bit)
TIMEVNT8 : TIMEVNT8
bits : 19 - 19 (1 bit)
TIMEVNT9 : TIMEVNT9
bits : 20 - 20 (1 bit)
EXTEVNT1 : EXTEVNT1
bits : 21 - 21 (1 bit)
EXTEVNT2 : EXTEVNT2
bits : 22 - 22 (1 bit)
EXTEVNT3 : EXTEVNT3
bits : 23 - 23 (1 bit)
EXTEVNT4 : EXTEVNT4
bits : 24 - 24 (1 bit)
EXTEVNT5 : EXTEVNT5
bits : 25 - 25 (1 bit)
EXTEVNT6 : EXTEVNT6
bits : 26 - 26 (1 bit)
EXTEVNT7 : EXTEVNT7
bits : 27 - 27 (1 bit)
EXTEVNT8 : EXTEVNT8
bits : 28 - 28 (1 bit)
EXTEVNT9 : EXTEVNT9
bits : 29 - 29 (1 bit)
EXTEVNT10 : EXTEVNT10
bits : 30 - 30 (1 bit)
UPDATE : UPDATE
bits : 31 - 31 (1 bit)
Timerx Output2 Set Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SST : SST
bits : 0 - 0 (1 bit)
RESYNC : RESYNC
bits : 1 - 1 (1 bit)
PER : PER
bits : 2 - 2 (1 bit)
CMP1 : CMP1
bits : 3 - 3 (1 bit)
CMP2 : CMP2
bits : 4 - 4 (1 bit)
CMP3 : CMP3
bits : 5 - 5 (1 bit)
CMP4 : CMP4
bits : 6 - 6 (1 bit)
MSTPER : MSTPER
bits : 7 - 7 (1 bit)
MSTCMP1 : MSTCMP1
bits : 8 - 8 (1 bit)
MSTCMP2 : MSTCMP2
bits : 9 - 9 (1 bit)
MSTCMP3 : MSTCMP3
bits : 10 - 10 (1 bit)
MSTCMP4 : MSTCMP4
bits : 11 - 11 (1 bit)
TIMEVNT1 : TIMEVNT1
bits : 12 - 12 (1 bit)
TIMEVNT2 : TIMEVNT2
bits : 13 - 13 (1 bit)
TIMEVNT3 : TIMEVNT3
bits : 14 - 14 (1 bit)
TIMEVNT4 : TIMEVNT4
bits : 15 - 15 (1 bit)
TIMEVNT5 : TIMEVNT5
bits : 16 - 16 (1 bit)
TIMEVNT6 : TIMEVNT6
bits : 17 - 17 (1 bit)
TIMEVNT7 : TIMEVNT7
bits : 18 - 18 (1 bit)
TIMEVNT8 : TIMEVNT8
bits : 19 - 19 (1 bit)
TIMEVNT9 : TIMEVNT9
bits : 20 - 20 (1 bit)
EXTEVNT1 : EXTEVNT1
bits : 21 - 21 (1 bit)
EXTEVNT2 : EXTEVNT2
bits : 22 - 22 (1 bit)
EXTEVNT3 : EXTEVNT3
bits : 23 - 23 (1 bit)
EXTEVNT4 : EXTEVNT4
bits : 24 - 24 (1 bit)
EXTEVNT5 : EXTEVNT5
bits : 25 - 25 (1 bit)
EXTEVNT6 : EXTEVNT6
bits : 26 - 26 (1 bit)
EXTEVNT7 : EXTEVNT7
bits : 27 - 27 (1 bit)
EXTEVNT8 : EXTEVNT8
bits : 28 - 28 (1 bit)
EXTEVNT9 : EXTEVNT9
bits : 29 - 29 (1 bit)
EXTEVNT10 : EXTEVNT10
bits : 30 - 30 (1 bit)
UPDATE : UPDATE
bits : 31 - 31 (1 bit)
Timerx Output2 Reset Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRT : SRT
bits : 0 - 0 (1 bit)
RESYNC : RESYNC
bits : 1 - 1 (1 bit)
PER : PER
bits : 2 - 2 (1 bit)
CMP1 : CMP1
bits : 3 - 3 (1 bit)
CMP2 : CMP2
bits : 4 - 4 (1 bit)
CMP3 : CMP3
bits : 5 - 5 (1 bit)
CMP4 : CMP4
bits : 6 - 6 (1 bit)
MSTPER : MSTPER
bits : 7 - 7 (1 bit)
MSTCMP1 : MSTCMP1
bits : 8 - 8 (1 bit)
MSTCMP2 : MSTCMP2
bits : 9 - 9 (1 bit)
MSTCMP3 : MSTCMP3
bits : 10 - 10 (1 bit)
MSTCMP4 : MSTCMP4
bits : 11 - 11 (1 bit)
TIMEVNT1 : TIMEVNT1
bits : 12 - 12 (1 bit)
TIMEVNT2 : TIMEVNT2
bits : 13 - 13 (1 bit)
TIMEVNT3 : TIMEVNT3
bits : 14 - 14 (1 bit)
TIMEVNT4 : TIMEVNT4
bits : 15 - 15 (1 bit)
TIMEVNT5 : TIMEVNT5
bits : 16 - 16 (1 bit)
TIMEVNT6 : TIMEVNT6
bits : 17 - 17 (1 bit)
TIMEVNT7 : TIMEVNT7
bits : 18 - 18 (1 bit)
TIMEVNT8 : TIMEVNT8
bits : 19 - 19 (1 bit)
TIMEVNT9 : TIMEVNT9
bits : 20 - 20 (1 bit)
EXTEVNT1 : EXTEVNT1
bits : 21 - 21 (1 bit)
EXTEVNT2 : EXTEVNT2
bits : 22 - 22 (1 bit)
EXTEVNT3 : EXTEVNT3
bits : 23 - 23 (1 bit)
EXTEVNT4 : EXTEVNT4
bits : 24 - 24 (1 bit)
EXTEVNT5 : EXTEVNT5
bits : 25 - 25 (1 bit)
EXTEVNT6 : EXTEVNT6
bits : 26 - 26 (1 bit)
EXTEVNT7 : EXTEVNT7
bits : 27 - 27 (1 bit)
EXTEVNT8 : EXTEVNT8
bits : 28 - 28 (1 bit)
EXTEVNT9 : EXTEVNT9
bits : 29 - 29 (1 bit)
EXTEVNT10 : EXTEVNT10
bits : 30 - 30 (1 bit)
UPDATE : UPDATE
bits : 31 - 31 (1 bit)
Timerx External Event Filtering Register 1
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EE1LTCH : External Event 1 latch
bits : 0 - 0 (1 bit)
EE1FLTR : External Event 1 filter
bits : 1 - 4 (4 bit)
EE2LTCH : External Event 2 latch
bits : 6 - 6 (1 bit)
EE2FLTR : External Event 2 filter
bits : 7 - 10 (4 bit)
EE3LTCH : External Event 3 latch
bits : 12 - 12 (1 bit)
EE3FLTR : External Event 3 filter
bits : 13 - 16 (4 bit)
EE4LTCH : External Event 4 latch
bits : 18 - 18 (1 bit)
EE4FLTR : External Event 4 filter
bits : 19 - 22 (4 bit)
EE5LTCH : External Event 5 latch
bits : 24 - 24 (1 bit)
EE5FLTR : External Event 5 filter
bits : 25 - 28 (4 bit)
Timerx External Event Filtering Register 2
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EE6LTCH : External Event 6 latch
bits : 0 - 0 (1 bit)
EE6FLTR : External Event 6 filter
bits : 1 - 4 (4 bit)
EE7LTCH : External Event 7 latch
bits : 6 - 6 (1 bit)
EE7FLTR : External Event 7 filter
bits : 7 - 10 (4 bit)
EE8LTCH : External Event 8 latch
bits : 12 - 12 (1 bit)
EE8FLTR : External Event 8 filter
bits : 13 - 16 (4 bit)
EE9LTCH : External Event 9 latch
bits : 18 - 18 (1 bit)
EE9FLTR : External Event 9 filter
bits : 19 - 22 (4 bit)
EE10LTCH : External Event 10 latch
bits : 24 - 24 (1 bit)
EE10FLTR : External Event 10 filter
bits : 25 - 28 (4 bit)
TimerA Reset Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIMFCMP1 : Timer A Update reset
bits : 0 - 0 (1 bit)
UPDT : Timer A Update reset
bits : 1 - 1 (1 bit)
CMP2 : Timer A compare 2 reset
bits : 2 - 2 (1 bit)
CMP4 : Timer A compare 4 reset
bits : 3 - 3 (1 bit)
MSTPER : Master timer Period
bits : 4 - 4 (1 bit)
MSTCMP1 : Master compare 1
bits : 5 - 5 (1 bit)
MSTCMP2 : Master compare 2
bits : 6 - 6 (1 bit)
MSTCMP3 : Master compare 3
bits : 7 - 7 (1 bit)
MSTCMP4 : Master compare 4
bits : 8 - 8 (1 bit)
EXTEVNT1 : External Event 1
bits : 9 - 9 (1 bit)
EXTEVNT2 : External Event 2
bits : 10 - 10 (1 bit)
EXTEVNT3 : External Event 3
bits : 11 - 11 (1 bit)
EXTEVNT4 : External Event 4
bits : 12 - 12 (1 bit)
EXTEVNT5 : External Event 5
bits : 13 - 13 (1 bit)
EXTEVNT6 : External Event 6
bits : 14 - 14 (1 bit)
EXTEVNT7 : External Event 7
bits : 15 - 15 (1 bit)
EXTEVNT8 : External Event 8
bits : 16 - 16 (1 bit)
EXTEVNT9 : External Event 9
bits : 17 - 17 (1 bit)
EXTEVNT10 : External Event 10
bits : 18 - 18 (1 bit)
TIMACMP1 : Timer A Compare 1
bits : 19 - 19 (1 bit)
TIMACMP2 : Timer A Compare 2
bits : 20 - 20 (1 bit)
TIMACMP4 : Timer A Compare 4
bits : 21 - 21 (1 bit)
TIMBCMP1 : Timer B Compare 1
bits : 22 - 22 (1 bit)
TIMBCMP2 : Timer B Compare 2
bits : 23 - 23 (1 bit)
TIMBCMP4 : Timer B Compare 4
bits : 24 - 24 (1 bit)
TIMCCMP1 : Timer C Compare 1
bits : 25 - 25 (1 bit)
TIMCCMP2 : Timer C Compare 2
bits : 26 - 26 (1 bit)
TIMCCMP4 : Timer C Compare 4
bits : 27 - 27 (1 bit)
TIMECMP1 : Timer E Compare 1
bits : 28 - 28 (1 bit)
TIMECMP2 : Timer E Compare 2
bits : 29 - 29 (1 bit)
TIMECMP4 : Timer E Compare 4
bits : 30 - 30 (1 bit)
TIMFCPM2 : Timer F Compare 2
bits : 31 - 31 (1 bit)
Timerx Chopper Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHPFRQ : Timerx carrier frequency value
bits : 0 - 3 (4 bit)
CHPDTY : Timerx chopper duty cycle value
bits : 4 - 6 (3 bit)
STRTPW : STRTPW
bits : 7 - 10 (4 bit)
Timerx Capture 2 Control Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWCPT : Software Capture
bits : 0 - 0 (1 bit)
UDPCPT : Update Capture
bits : 1 - 1 (1 bit)
EXEV1CPT : External Event 1 Capture
bits : 2 - 2 (1 bit)
EXEV2CPT : External Event 2 Capture
bits : 3 - 3 (1 bit)
EXEV3CPT : External Event 3 Capture
bits : 4 - 4 (1 bit)
EXEV4CPT : External Event 4 Capture
bits : 5 - 5 (1 bit)
EXEV5CPT : External Event 5 Capture
bits : 6 - 6 (1 bit)
EXEV6CPT : External Event 6 Capture
bits : 7 - 7 (1 bit)
EXEV7CPT : External Event 7 Capture
bits : 8 - 8 (1 bit)
EXEV8CPT : External Event 8 Capture
bits : 9 - 9 (1 bit)
EXEV9CPT : External Event 9 Capture
bits : 10 - 10 (1 bit)
EXEV10CPT : External Event 10 Capture
bits : 11 - 11 (1 bit)
TA1SET : Timer A output 1 Set
bits : 12 - 12 (1 bit)
TA1RST : Timer A output 1 Reset
bits : 13 - 13 (1 bit)
TACMP1 : Timer A Compare 1
bits : 14 - 14 (1 bit)
TACMP2 : Timer A Compare 2
bits : 15 - 15 (1 bit)
TB1SET : Timer B output 1 Set
bits : 16 - 16 (1 bit)
TB1RST : Timer B output 1 Reset
bits : 17 - 17 (1 bit)
TBCMP1 : Timer B Compare 1
bits : 18 - 18 (1 bit)
TBCMP2 : Timer B Compare 2
bits : 19 - 19 (1 bit)
TC1SET : Timer C output 1 Set
bits : 20 - 20 (1 bit)
TC1RST : Timer C output 1 Reset
bits : 21 - 21 (1 bit)
TCCMP1 : Timer C Compare 1
bits : 22 - 22 (1 bit)
TCCMP2 : Timer C Compare 2
bits : 23 - 23 (1 bit)
TF1SET : TF1SET
bits : 24 - 24 (1 bit)
TF1RST : TF1RST
bits : 25 - 25 (1 bit)
TFCMP1 : TFCMP1
bits : 26 - 26 (1 bit)
TFCMP2 : TFCMP2
bits : 27 - 27 (1 bit)
TE1SET : Timer E output 1 Set
bits : 28 - 28 (1 bit)
TE1RST : Timer E output 1 Reset
bits : 29 - 29 (1 bit)
TECMP1 : Timer E Compare 1
bits : 30 - 30 (1 bit)
TECMP2 : Timer E Compare 2
bits : 31 - 31 (1 bit)
CPT2xCR
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWCPT : Software Capture
bits : 0 - 0 (1 bit)
UDPCPT : Update Capture
bits : 1 - 1 (1 bit)
EXEV1CPT : External Event 1 Capture
bits : 2 - 2 (1 bit)
EXEV2CPT : External Event 2 Capture
bits : 3 - 3 (1 bit)
EXEV3CPT : External Event 3 Capture
bits : 4 - 4 (1 bit)
EXEV4CPT : External Event 4 Capture
bits : 5 - 5 (1 bit)
EXEV5CPT : External Event 5 Capture
bits : 6 - 6 (1 bit)
EXEV6CPT : External Event 6 Capture
bits : 7 - 7 (1 bit)
EXEV7CPT : External Event 7 Capture
bits : 8 - 8 (1 bit)
EXEV8CPT : External Event 8 Capture
bits : 9 - 9 (1 bit)
EXEV9CPT : External Event 9 Capture
bits : 10 - 10 (1 bit)
EXEV10CPT : External Event 10 Capture
bits : 11 - 11 (1 bit)
TA1SET : Timer A output 1 Set
bits : 12 - 12 (1 bit)
TA1RST : Timer A output 1 Reset
bits : 13 - 13 (1 bit)
TACMP1 : Timer A Compare 1
bits : 14 - 14 (1 bit)
TACMP2 : Timer A Compare 2
bits : 15 - 15 (1 bit)
TB1SET : Timer B output 1 Set
bits : 16 - 16 (1 bit)
TB1RST : Timer B output 1 Reset
bits : 17 - 17 (1 bit)
TBCMP1 : Timer B Compare 1
bits : 18 - 18 (1 bit)
TBCMP2 : Timer B Compare 2
bits : 19 - 19 (1 bit)
TC1SET : Timer C output 1 Set
bits : 20 - 20 (1 bit)
TC1RST : Timer C output 1 Reset
bits : 21 - 21 (1 bit)
TCCMP1 : Timer C Compare 1
bits : 22 - 22 (1 bit)
TCCMP2 : Timer C Compare 2
bits : 23 - 23 (1 bit)
TF1SET : TF1SET
bits : 24 - 24 (1 bit)
TF1RST : TF1RST
bits : 25 - 25 (1 bit)
TFCMP1 : TFCMP1
bits : 26 - 26 (1 bit)
TFCMP2 : TFCMP2
bits : 27 - 27 (1 bit)
TE1SET : Timer E output 1 Set
bits : 28 - 28 (1 bit)
TE1RST : Timer E output 1 Reset
bits : 29 - 29 (1 bit)
TECMP1 : Timer E Compare 1
bits : 30 - 30 (1 bit)
TECMP2 : Timer E Compare 2
bits : 31 - 31 (1 bit)
Timerx Output Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POL1 : Output 1 polarity
bits : 1 - 1 (1 bit)
IDLEM1 : Output 1 Idle mode
bits : 2 - 2 (1 bit)
IDLES1 : Output 1 Idle State
bits : 3 - 3 (1 bit)
FAULT1 : Output 1 Fault state
bits : 4 - 5 (2 bit)
CHP1 : Output 1 Chopper enable
bits : 6 - 6 (1 bit)
DIDL1 : Output 1 Deadtime upon burst mode Idle entry
bits : 7 - 7 (1 bit)
DTEN : Deadtime enable
bits : 8 - 8 (1 bit)
DLYPRTEN : Delayed Protection Enable
bits : 9 - 9 (1 bit)
DLYPRT : Delayed Protection
bits : 10 - 12 (3 bit)
BIAR : Balanced Idle Automatic Resume
bits : 14 - 14 (1 bit)
POL2 : Output 2 polarity
bits : 17 - 17 (1 bit)
IDLEM2 : Output 2 Idle mode
bits : 18 - 18 (1 bit)
IDLES2 : Output 2 Idle State
bits : 19 - 19 (1 bit)
FAULT2 : Output 2 Fault state
bits : 20 - 21 (2 bit)
CHP2 : Output 2 Chopper enable
bits : 22 - 22 (1 bit)
DIDL2 : Output 2 Deadtime upon burst mode Idle entry
bits : 23 - 23 (1 bit)
Timerx Fault Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLT1EN : Fault 1 enable
bits : 0 - 0 (1 bit)
FLT2EN : Fault 2 enable
bits : 1 - 1 (1 bit)
FLT3EN : Fault 3 enable
bits : 2 - 2 (1 bit)
FLT4EN : Fault 4 enable
bits : 3 - 3 (1 bit)
FLT5EN : Fault 5 enable
bits : 4 - 4 (1 bit)
FLT6EN : Fault 6 enable
bits : 5 - 5 (1 bit)
FLTLCK : Fault sources Lock
bits : 31 - 31 (1 bit)
HRTIM Timerx Control Register 2
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCDE : Dual Channel DAC trigger enable
bits : 0 - 0 (1 bit)
DCDS : Dual Channel DAC Step trigger
bits : 1 - 1 (1 bit)
DCDR : Dual Channel DAC Reset trigger
bits : 2 - 2 (1 bit)
UDM : Up-Down Mode
bits : 4 - 4 (1 bit)
ROM : Roll-Over Mode
bits : 6 - 7 (2 bit)
OUTROM : Output Roll-Over Mode
bits : 8 - 9 (2 bit)
ADROM : ADC Roll-Over Mode
bits : 10 - 11 (2 bit)
BMROM : Burst Mode Roll-Over Mode
bits : 12 - 13 (2 bit)
FEROM : Fault and Event Roll-Over Mode
bits : 14 - 15 (2 bit)
GTCMP1 : Greater than Compare 1 PWM mode
bits : 16 - 16 (1 bit)
GTCMP3 : Greater than Compare 3 PWM mode
bits : 17 - 17 (1 bit)
TRGHLF : Triggered-half mode
bits : 20 - 20 (1 bit)
HRTIM Timerx External Event Filtering Register 3
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EEVACE : External Event A Counter Enable
bits : 0 - 0 (1 bit)
EEVACRES : External Event A Counter Reset
bits : 1 - 1 (1 bit)
EEVARSTM : External Event A Reset Mode
bits : 2 - 2 (1 bit)
EEVASEL : External Event A Selection
bits : 4 - 7 (4 bit)
EEVACNT : External Event A counter
bits : 8 - 13 (6 bit)
Timerx Interrupt Clear Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CMP1C : Compare 1 Interrupt flag Clear
bits : 0 - 0 (1 bit)
CMP2C : Compare 2 Interrupt flag Clear
bits : 1 - 1 (1 bit)
CMP3C : Compare 3 Interrupt flag Clear
bits : 2 - 2 (1 bit)
CMP4C : Compare 4 Interrupt flag Clear
bits : 3 - 3 (1 bit)
REPC : Repetition Interrupt flag Clear
bits : 4 - 4 (1 bit)
UPDC : Update Interrupt flag Clear
bits : 6 - 6 (1 bit)
CPT1C : Capture1 Interrupt flag Clear
bits : 7 - 7 (1 bit)
CPT2C : Capture2 Interrupt flag Clear
bits : 8 - 8 (1 bit)
SET1xC : Output 1 Set flag Clear
bits : 9 - 9 (1 bit)
RSTx1C : Output 1 Reset flag Clear
bits : 10 - 10 (1 bit)
SET2xC : Output 2 Set flag Clear
bits : 11 - 11 (1 bit)
RSTx2C : Output 2 Reset flag Clear
bits : 12 - 12 (1 bit)
RSTC : Reset Interrupt flag Clear
bits : 13 - 13 (1 bit)
DLYPRTC : Delayed Protection Flag Clear
bits : 14 - 14 (1 bit)
TIMxDIER
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMP1IE : CMP1IE
bits : 0 - 0 (1 bit)
CMP2IE : CMP2IE
bits : 1 - 1 (1 bit)
CMP3IE : CMP3IE
bits : 2 - 2 (1 bit)
CMP4IE : CMP4IE
bits : 3 - 3 (1 bit)
REPIE : REPIE
bits : 4 - 4 (1 bit)
UPDIE : UPDIE
bits : 6 - 6 (1 bit)
CPT1IE : CPT1IE
bits : 7 - 7 (1 bit)
CPT2IE : CPT2IE
bits : 8 - 8 (1 bit)
SET1xIE : SET1xIE
bits : 9 - 9 (1 bit)
RSTx1IE : RSTx1IE
bits : 10 - 10 (1 bit)
SETx2IE : SETx2IE
bits : 11 - 11 (1 bit)
RSTx2IE : RSTx2IE
bits : 12 - 12 (1 bit)
RSTIE : RSTIE
bits : 13 - 13 (1 bit)
DLYPRTIE : DLYPRTIE
bits : 14 - 14 (1 bit)
CMP1DE : CMP1DE
bits : 16 - 16 (1 bit)
CMP2DE : CMP2DE
bits : 17 - 17 (1 bit)
CMP3DE : CMP3DE
bits : 18 - 18 (1 bit)
CMP4DE : CMP4DE
bits : 19 - 19 (1 bit)
REPDE : REPDE
bits : 20 - 20 (1 bit)
UPDDE : UPDDE
bits : 22 - 22 (1 bit)
CPT1DE : CPT1DE
bits : 23 - 23 (1 bit)
CPT2DE : CPT2DE
bits : 24 - 24 (1 bit)
SET1xDE : SET1xDE
bits : 25 - 25 (1 bit)
RSTx1DE : RSTx1DE
bits : 26 - 26 (1 bit)
SETx2DE : SETx2DE
bits : 27 - 27 (1 bit)
RSTx2DE : RSTx2DE
bits : 28 - 28 (1 bit)
RSTDE : RSTDE
bits : 29 - 29 (1 bit)
DLYPRTDE : DLYPRTDE
bits : 30 - 30 (1 bit)
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