Registers
FFT input data fifo
address_offset : 0x0 Bytes (0x0)
size : 64 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
fifo_ctrl
FIFO control
address_offset : 0x10 Bytes (0x0)
size : 64 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
resp_fifo_flush : Response memory initialization flag
bits : 0 - 0 (1 bit)
cmd_fifo_flush : Command memory initialization flag
bits : 1 - 2 (2 bit)
gs_fifo_flush : Output interface memory initialization flag
bits : 2 - 4 (3 bit)
intr_mask
interrupt mask
address_offset : 0x18 Bytes (0x0)
size : 64 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
fft_done : FFT done
bits : 0 - 0 (1 bit)
interrupt mask
intr_mask
address_offset : 0x18 Bytes (0x0)
size : 64 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
fft_done : FFT done
bits : 0 - 0 (1 bit)
intr_clear
Interrupt clear
address_offset : 0x20 Bytes (0x0)
size : 64 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
fft_done : FFT done
bits : 0 - 0 (1 bit)
status
FFT status register
address_offset : 0x28 Bytes (0x0)
size : 64 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
fft_done : FFT done
bits : 0 - 0 (1 bit)
status_raw
FFT status raw
address_offset : 0x30 Bytes (0x0)
size : 64 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
fft_done : FFT done
bits : 0 - 0 (1 bit)
fft_work : FFT work
bits : 1 - 2 (2 bit)
output_fifo
FFT output FIFO
address_offset : 0x38 Bytes (0x0)
size : 64 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ctrl
FFT control register
address_offset : 0x8 Bytes (0x0)
size : 64 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
point : FFT calculation data length
bits : 0 - 2 (3 bit)
Enumeration:
0 : p512
512 point
1 : p256
256 point
2 : p128
128 point
3 : p64
64 point
End of enumeration elements list.
mode : FFT mode
bits : 3 - 6 (4 bit)
Enumeration:
0 : fft
FFT mode
1 : ifft
Inverse FFT mode
End of enumeration elements list.
shift : Corresponding to the nine layer butterfly shift operation, 0x0: does not shift; 0x1: shift 1st layer. ...
bits : 4 - 16 (13 bit)
enable : FFT enable
bits : 13 - 26 (14 bit)
dma_send : FFT DMA enable
bits : 14 - 28 (15 bit)
input_mode : Input data arrangement
bits : 15 - 31 (17 bit)
Enumeration:
0 : riri
RIRI (real imaginary interleaved)
1 : rrrr
RRRR (only real part)
2 : rrii
First input the real part and then input the imaginary part
End of enumeration elements list.
data_mode : Effective width of input data
bits : 17 - 34 (18 bit)
Enumeration:
0 : width_64
64 bit effective
1 : width_128
128 bit effective
End of enumeration elements list.
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !