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DMAC

Peripheral Memory Blocks

Registers

id

cfg

channel[0]-sar

channel[0]-dar

channel[0]-block_ts

channel[0]-ctl

channel[0]-cfg

channel[0]-llp

channel[0]-status

channel[0]-swhssrc

channel[0]-swhsdst

channel[0]-blk_tfr

channel[0]-axi_id

channel[5]-channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-sar

channel[5]-channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-dar

channel[5]-channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-block_ts

channel[5]-channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-ctl

channel[5]-channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-cfg

channel[5]-channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-llp

channel[5]-channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-status

channel[5]-channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-swhssrc

channel[5]-channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-swhsdst

channel[5]-channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-blk_tfr

channel[5]-channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-axi_id

channel[5]-channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-axi_qos

channel[0]-axi_qos

channel[5]-channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-intstatus_en

channel[5]-channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-intstatus

channel[5]-channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-intsignal_en

channel[5]-channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-intclear

channel[5]-channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-_reserved

chen

channel[0]-intstatus_en

channel[0]-intstatus

channel[0]-intsignal_en

channel[0]-intclear

channel[0]-_reserved

intstatus

channel[1]-channel[0]-sar

channel[1]-channel[0]-dar

channel[1]-channel[0]-block_ts

channel[1]-channel[0]-ctl

channel[1]-channel[0]-cfg

channel[1]-channel[0]-llp

channel[1]-channel[0]-status

channel[1]-channel[0]-swhssrc

channel[1]-channel[0]-swhsdst

channel[1]-channel[0]-blk_tfr

channel[1]-channel[0]-axi_id

channel[1]-channel[0]-axi_qos

com_intclear

channel[1]-channel[0]-intstatus_en

channel[1]-channel[0]-intstatus

channel[1]-channel[0]-intsignal_en

channel[1]-channel[0]-intclear

channel[1]-channel[0]-_reserved

com_intstatus_en

com_intsignal_en

com_intstatus

reset

channel[2]-channel[1]-channel[0]-sar

channel[2]-channel[1]-channel[0]-dar

channel[2]-channel[1]-channel[0]-block_ts

channel[2]-channel[1]-channel[0]-ctl

channel[2]-channel[1]-channel[0]-cfg

channel[2]-channel[1]-channel[0]-llp

channel[2]-channel[1]-channel[0]-status

channel[2]-channel[1]-channel[0]-swhssrc

channel[2]-channel[1]-channel[0]-swhsdst

channel[2]-channel[1]-channel[0]-blk_tfr

channel[2]-channel[1]-channel[0]-axi_id

channel[2]-channel[1]-channel[0]-axi_qos

channel[2]-channel[1]-channel[0]-intstatus_en

channel[2]-channel[1]-channel[0]-intstatus

channel[2]-channel[1]-channel[0]-intsignal_en

channel[2]-channel[1]-channel[0]-intclear

channel[2]-channel[1]-channel[0]-_reserved

compver

channel[3]-channel[2]-channel[1]-channel[0]-sar

channel[3]-channel[2]-channel[1]-channel[0]-dar

channel[3]-channel[2]-channel[1]-channel[0]-block_ts

channel[3]-channel[2]-channel[1]-channel[0]-ctl

channel[3]-channel[2]-channel[1]-channel[0]-cfg

channel[3]-channel[2]-channel[1]-channel[0]-llp

channel[3]-channel[2]-channel[1]-channel[0]-status

channel[3]-channel[2]-channel[1]-channel[0]-swhssrc

channel[3]-channel[2]-channel[1]-channel[0]-swhsdst

channel[3]-channel[2]-channel[1]-channel[0]-blk_tfr

channel[3]-channel[2]-channel[1]-channel[0]-axi_id

channel[3]-channel[2]-channel[1]-channel[0]-axi_qos

channel[3]-channel[2]-channel[1]-channel[0]-intstatus_en

channel[3]-channel[2]-channel[1]-channel[0]-intstatus

channel[3]-channel[2]-channel[1]-channel[0]-intsignal_en

channel[3]-channel[2]-channel[1]-channel[0]-intclear

channel[3]-channel[2]-channel[1]-channel[0]-_reserved

channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-sar

channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-dar

channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-block_ts

channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-ctl

channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-cfg

channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-llp

channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-status

channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-swhssrc

channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-swhsdst

channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-blk_tfr

channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-axi_id

channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-axi_qos

channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-intstatus_en

channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-intstatus

channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-intsignal_en

channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-intclear

channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-_reserved


id

ID Register
address_offset : 0x0 Bytes (0x0)
size : 64 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

id id read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 Resets to Resets to Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

cfg

Configure Register
address_offset : 0x10 Bytes (0x0)
size : 64 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

cfg cfg read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 Resets to Resets to Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dmac_en int_en

dmac_en : Enable DMAC
bits : 0 - 0 (1 bit)

int_en : Globally enable interrupt generation
bits : 1 - 2 (2 bit)


channel[0]-sar

SAR Address Register
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[0]-sar channel[0]-sar read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

channel[0]-dar

DAR Address Register
address_offset : 0x108 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[0]-dar channel[0]-dar read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

channel[0]-block_ts

Block Transfer Size Register
address_offset : 0x110 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[0]-block_ts channel[0]-block_ts read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 block_ts

block_ts : Block transfer size
bits : 0 - 21 (22 bit)


channel[0]-ctl

Control Register
address_offset : 0x118 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[0]-ctl channel[0]-ctl read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sms dms sinc dinc src_tr_width dst_tr_width src_msize dst_msize nonposted_lastwrite_en arlen_en arlen awlen_en awlen src_stat_en dst_stat_en ioc_blktfr shadowreg_or_lli_last shadowreg_or_lli_valid

sms : Source master select
bits : 0 - 0 (1 bit)

Enumeration: MASTER_SELECT

0 : axi_master_1

AXI master 1

1 : axi_master_2

AXI master 2

End of enumeration elements list.

dms : Destination master select
bits : 2 - 4 (3 bit)

Enumeration:

End of enumeration elements list.

sinc : Source address increment
bits : 4 - 8 (5 bit)

Enumeration: INCREMENT

0 : increment

Increment address

1 : nochange

Don't increment address

End of enumeration elements list.

dinc : Destination address increment
bits : 6 - 12 (7 bit)

Enumeration:

End of enumeration elements list.

src_tr_width : Source transfer width
bits : 8 - 18 (11 bit)

Enumeration: TRANSFER_WIDTH

0 : width_8

8 bits

1 : width_16

16 bits

2 : width_32

32 bits

3 : width_64

64 bits

4 : width_128

128 bits

5 : width_256

256 bits

6 : width_512

512 bits

End of enumeration elements list.

dst_tr_width : Destination transfer width
bits : 11 - 24 (14 bit)

Enumeration:

End of enumeration elements list.

src_msize : Source burst transaction length
bits : 14 - 31 (18 bit)

Enumeration: BURST_LENGTH

0 : length_1

1 data item

1 : length_4

4 data items

2 : length_8

8 data items

3 : length_16

16 data items

4 : length_32

32 data items

5 : length_64

64 data items

6 : length_128

128 data items

7 : length_256

256 data items

8 : length_512

512 data items

9 : length_1024

1024 data items

End of enumeration elements list.

dst_msize : Destination burst transaction length
bits : 18 - 39 (22 bit)

Enumeration:

End of enumeration elements list.

nonposted_lastwrite_en : Non Posted Last Write Enable (posted writes may be used till the end of the block)
bits : 30 - 60 (31 bit)

arlen_en : Source burst length enable
bits : 38 - 76 (39 bit)

arlen : Source burst length
bits : 39 - 85 (47 bit)

awlen_en : Destination burst length enable
bits : 47 - 94 (48 bit)

awlen : Destination burst length
bits : 48 - 103 (56 bit)

src_stat_en : Source status enable
bits : 56 - 112 (57 bit)

dst_stat_en : Destination status enable
bits : 57 - 114 (58 bit)

ioc_blktfr : Interrupt completion of block transfer
bits : 58 - 116 (59 bit)

shadowreg_or_lli_last : Last shadow linked list item (indicates shadowreg/LLI content is the last one)
bits : 62 - 124 (63 bit)

shadowreg_or_lli_valid : last shadow linked list item valid (indicate shadowreg/LLI content is valid)
bits : 63 - 126 (64 bit)


channel[0]-cfg

Configure Register
address_offset : 0x120 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[0]-cfg channel[0]-cfg read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 src_multblk_type dst_multblk_type tt_fc hs_sel_src hs_sel_dst src_hwhs_pol dst_hwhs_pol src_per dst_per ch_prior lock_ch lock_ch_l src_osr_lmt dst_osr_lmt

src_multblk_type : Source multi-block transfer type
bits : 0 - 1 (2 bit)

Enumeration: MULTIBLK_TRANSFER_TYPE

0 : contiguous

Continuous multi-block type

1 : reload

Reload multi-block type

2 : shadow_register

Shadow register based multi-block type

3 : linked_list

Linked list based multi-block type

End of enumeration elements list.

dst_multblk_type : Destination multi-block transfer type
bits : 2 - 5 (4 bit)

Enumeration:

End of enumeration elements list.

tt_fc : Transfer type and flow control
bits : 32 - 66 (35 bit)

Enumeration:

0 : mem2mem_dma

Transfer memory to memory and flow controller is DMAC

1 : mem2prf_dma

Transfer memory to peripheral and flow controller is DMAC

2 : prf2mem_dma

Transfer peripheral to memory and flow controller is DMAC

3 : prf2prf_dma

Transfer peripheral to peripheral and flow controller is DMAC

4 : prf2mem_prf

Transfer peripheral to memory and flow controller is source peripheral

5 : prf2prf_srcprf

Transfer peripheral to peripheral and flow controller is source peripheral

6 : mem2prf_prf

Transfer memory to peripheral and flow controller is destination peripheral

7 : prf2prf_dstprf

Transfer peripheral to peripheral and flow controller is destination peripheral

End of enumeration elements list.

hs_sel_src : Source software or hardware handshaking select
bits : 35 - 70 (36 bit)

Enumeration: HANDSHAKING

0 : hardware

Hardware handshaking is used

1 : software

Software handshaking is used

End of enumeration elements list.

hs_sel_dst : Destination software or hardware handshaking select
bits : 36 - 72 (37 bit)

Enumeration:

End of enumeration elements list.

src_hwhs_pol : Source hardware handshaking interface polarity
bits : 37 - 74 (38 bit)

Enumeration: POLARITY

0 : active_high

Active high

1 : active_low

Active low

End of enumeration elements list.

dst_hwhs_pol : Destination hardware handshaking interface polarity
bits : 38 - 76 (39 bit)

Enumeration:

End of enumeration elements list.

src_per : Assign a hardware handshaking interface to source of channel
bits : 39 - 81 (43 bit)

dst_per : Assign a hardware handshaking interface to destination of channel
bits : 44 - 91 (48 bit)

ch_prior : Channel priority (7 is highest, 0 is lowest)
bits : 49 - 100 (52 bit)

lock_ch : Channel lock bit
bits : 52 - 104 (53 bit)

lock_ch_l : Channel lock level
bits : 53 - 107 (55 bit)

Enumeration:

0 : dma_transfer

Duration of channel is locked for entire DMA transfer

1 : block_transfer

Duration of channel is locked for current block transfer

2 : transaction

Duration of channel is locked for current transaction

End of enumeration elements list.

src_osr_lmt : Source outstanding request limit
bits : 55 - 113 (59 bit)

dst_osr_lmt : Destination outstanding request limit
bits : 59 - 121 (63 bit)


channel[0]-llp

Linked List Pointer register
address_offset : 0x128 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[0]-llp channel[0]-llp read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 lms loc

lms : LLI master select
bits : 0 - 0 (1 bit)

Enumeration:

End of enumeration elements list.

loc : Starting address memeory of LLI block
bits : 6 - 69 (64 bit)


channel[0]-status

Channel Status Register
address_offset : 0x130 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[0]-status channel[0]-status read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cmpltd_blk_size

cmpltd_blk_size : Completed block transfer size
bits : 0 - 21 (22 bit)


channel[0]-swhssrc

Channel Software handshake Source Register
address_offset : 0x138 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[0]-swhssrc channel[0]-swhssrc read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 req req_we sglreq sglreq_we lst lst_we

req : Software handshake request for channel source
bits : 0 - 0 (1 bit)

req_we : Write enable bit for software handshake request
bits : 1 - 2 (2 bit)

sglreq : Software handshake single request for channel source
bits : 2 - 4 (3 bit)

sglreq_we : Write enable bit for software handshake
bits : 3 - 6 (4 bit)

lst : Software handshake last request for channel source
bits : 4 - 8 (5 bit)

lst_we : Write enable bit for software handshake last request
bits : 5 - 10 (6 bit)


channel[0]-swhsdst

Channel Software handshake Destination Register
address_offset : 0x140 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[0]-swhsdst channel[0]-swhsdst read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 req req_we sglreq sglreq_we lst lst_we

req : Software handshake request for channel destination
bits : 0 - 0 (1 bit)

req_we : Write enable bit for software handshake request
bits : 1 - 2 (2 bit)

sglreq : Software handshake single request for channel destination
bits : 2 - 4 (3 bit)

sglreq_we : Write enable bit for software handshake
bits : 3 - 6 (4 bit)

lst : Software handshake last request for channel destination
bits : 4 - 8 (5 bit)

lst_we : Write enable bit for software handshake last request
bits : 5 - 10 (6 bit)


channel[0]-blk_tfr

Channel Block Transfer Resume Request Register
address_offset : 0x148 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[0]-blk_tfr channel[0]-blk_tfr read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 resumereq

resumereq : Block transfer resume request
bits : 0 - 0 (1 bit)


channel[0]-axi_id

Channel AXI ID Register
address_offset : 0x150 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[0]-axi_id channel[0]-axi_id read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

channel[5]-channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-sar

SAR Address Register
address_offset : 0x1500 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[5]-channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-sar channel[5]-channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-sar read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

channel[5]-channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-dar

DAR Address Register
address_offset : 0x1508 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[5]-channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-dar channel[5]-channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-dar read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

channel[5]-channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-block_ts

Block Transfer Size Register
address_offset : 0x1510 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[5]-channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-block_ts channel[5]-channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-block_ts read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 block_ts

block_ts : Block transfer size
bits : 0 - 21 (22 bit)


channel[5]-channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-ctl

Control Register
address_offset : 0x1518 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[5]-channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-ctl channel[5]-channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-ctl read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sms dms sinc dinc src_tr_width dst_tr_width src_msize dst_msize nonposted_lastwrite_en arlen_en arlen awlen_en awlen src_stat_en dst_stat_en ioc_blktfr shadowreg_or_lli_last shadowreg_or_lli_valid

sms : Source master select
bits : 0 - 0 (1 bit)

Enumeration: MASTER_SELECT

0 : axi_master_1

AXI master 1

1 : axi_master_2

AXI master 2

End of enumeration elements list.

dms : Destination master select
bits : 2 - 4 (3 bit)

Enumeration:

End of enumeration elements list.

sinc : Source address increment
bits : 4 - 8 (5 bit)

Enumeration: INCREMENT

0 : increment

Increment address

1 : nochange

Don't increment address

End of enumeration elements list.

dinc : Destination address increment
bits : 6 - 12 (7 bit)

Enumeration:

End of enumeration elements list.

src_tr_width : Source transfer width
bits : 8 - 18 (11 bit)

Enumeration: TRANSFER_WIDTH

0 : width_8

8 bits

1 : width_16

16 bits

2 : width_32

32 bits

3 : width_64

64 bits

4 : width_128

128 bits

5 : width_256

256 bits

6 : width_512

512 bits

End of enumeration elements list.

dst_tr_width : Destination transfer width
bits : 11 - 24 (14 bit)

Enumeration:

End of enumeration elements list.

src_msize : Source burst transaction length
bits : 14 - 31 (18 bit)

Enumeration: BURST_LENGTH

0 : length_1

1 data item

1 : length_4

4 data items

2 : length_8

8 data items

3 : length_16

16 data items

4 : length_32

32 data items

5 : length_64

64 data items

6 : length_128

128 data items

7 : length_256

256 data items

8 : length_512

512 data items

9 : length_1024

1024 data items

End of enumeration elements list.

dst_msize : Destination burst transaction length
bits : 18 - 39 (22 bit)

Enumeration:

End of enumeration elements list.

nonposted_lastwrite_en : Non Posted Last Write Enable (posted writes may be used till the end of the block)
bits : 30 - 60 (31 bit)

arlen_en : Source burst length enable
bits : 38 - 76 (39 bit)

arlen : Source burst length
bits : 39 - 85 (47 bit)

awlen_en : Destination burst length enable
bits : 47 - 94 (48 bit)

awlen : Destination burst length
bits : 48 - 103 (56 bit)

src_stat_en : Source status enable
bits : 56 - 112 (57 bit)

dst_stat_en : Destination status enable
bits : 57 - 114 (58 bit)

ioc_blktfr : Interrupt completion of block transfer
bits : 58 - 116 (59 bit)

shadowreg_or_lli_last : Last shadow linked list item (indicates shadowreg/LLI content is the last one)
bits : 62 - 124 (63 bit)

shadowreg_or_lli_valid : last shadow linked list item valid (indicate shadowreg/LLI content is valid)
bits : 63 - 126 (64 bit)


channel[5]-channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-cfg

Configure Register
address_offset : 0x1520 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[5]-channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-cfg channel[5]-channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-cfg read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 src_multblk_type dst_multblk_type tt_fc hs_sel_src hs_sel_dst src_hwhs_pol dst_hwhs_pol src_per dst_per ch_prior lock_ch lock_ch_l src_osr_lmt dst_osr_lmt

src_multblk_type : Source multi-block transfer type
bits : 0 - 1 (2 bit)

Enumeration: MULTIBLK_TRANSFER_TYPE

0 : contiguous

Continuous multi-block type

1 : reload

Reload multi-block type

2 : shadow_register

Shadow register based multi-block type

3 : linked_list

Linked list based multi-block type

End of enumeration elements list.

dst_multblk_type : Destination multi-block transfer type
bits : 2 - 5 (4 bit)

Enumeration:

End of enumeration elements list.

tt_fc : Transfer type and flow control
bits : 32 - 66 (35 bit)

Enumeration:

0 : mem2mem_dma

Transfer memory to memory and flow controller is DMAC

1 : mem2prf_dma

Transfer memory to peripheral and flow controller is DMAC

2 : prf2mem_dma

Transfer peripheral to memory and flow controller is DMAC

3 : prf2prf_dma

Transfer peripheral to peripheral and flow controller is DMAC

4 : prf2mem_prf

Transfer peripheral to memory and flow controller is source peripheral

5 : prf2prf_srcprf

Transfer peripheral to peripheral and flow controller is source peripheral

6 : mem2prf_prf

Transfer memory to peripheral and flow controller is destination peripheral

7 : prf2prf_dstprf

Transfer peripheral to peripheral and flow controller is destination peripheral

End of enumeration elements list.

hs_sel_src : Source software or hardware handshaking select
bits : 35 - 70 (36 bit)

Enumeration: HANDSHAKING

0 : hardware

Hardware handshaking is used

1 : software

Software handshaking is used

End of enumeration elements list.

hs_sel_dst : Destination software or hardware handshaking select
bits : 36 - 72 (37 bit)

Enumeration:

End of enumeration elements list.

src_hwhs_pol : Source hardware handshaking interface polarity
bits : 37 - 74 (38 bit)

Enumeration: POLARITY

0 : active_high

Active high

1 : active_low

Active low

End of enumeration elements list.

dst_hwhs_pol : Destination hardware handshaking interface polarity
bits : 38 - 76 (39 bit)

Enumeration:

End of enumeration elements list.

src_per : Assign a hardware handshaking interface to source of channel
bits : 39 - 81 (43 bit)

dst_per : Assign a hardware handshaking interface to destination of channel
bits : 44 - 91 (48 bit)

ch_prior : Channel priority (7 is highest, 0 is lowest)
bits : 49 - 100 (52 bit)

lock_ch : Channel lock bit
bits : 52 - 104 (53 bit)

lock_ch_l : Channel lock level
bits : 53 - 107 (55 bit)

Enumeration:

0 : dma_transfer

Duration of channel is locked for entire DMA transfer

1 : block_transfer

Duration of channel is locked for current block transfer

2 : transaction

Duration of channel is locked for current transaction

End of enumeration elements list.

src_osr_lmt : Source outstanding request limit
bits : 55 - 113 (59 bit)

dst_osr_lmt : Destination outstanding request limit
bits : 59 - 121 (63 bit)


channel[5]-channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-llp

Linked List Pointer register
address_offset : 0x1528 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[5]-channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-llp channel[5]-channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-llp read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 lms loc

lms : LLI master select
bits : 0 - 0 (1 bit)

Enumeration:

End of enumeration elements list.

loc : Starting address memeory of LLI block
bits : 6 - 69 (64 bit)


channel[5]-channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-status

Channel Status Register
address_offset : 0x1530 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[5]-channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-status channel[5]-channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-status read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cmpltd_blk_size

cmpltd_blk_size : Completed block transfer size
bits : 0 - 21 (22 bit)


channel[5]-channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-swhssrc

Channel Software handshake Source Register
address_offset : 0x1538 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[5]-channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-swhssrc channel[5]-channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-swhssrc read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 req req_we sglreq sglreq_we lst lst_we

req : Software handshake request for channel source
bits : 0 - 0 (1 bit)

req_we : Write enable bit for software handshake request
bits : 1 - 2 (2 bit)

sglreq : Software handshake single request for channel source
bits : 2 - 4 (3 bit)

sglreq_we : Write enable bit for software handshake
bits : 3 - 6 (4 bit)

lst : Software handshake last request for channel source
bits : 4 - 8 (5 bit)

lst_we : Write enable bit for software handshake last request
bits : 5 - 10 (6 bit)


channel[5]-channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-swhsdst

Channel Software handshake Destination Register
address_offset : 0x1540 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[5]-channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-swhsdst channel[5]-channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-swhsdst read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 req req_we sglreq sglreq_we lst lst_we

req : Software handshake request for channel destination
bits : 0 - 0 (1 bit)

req_we : Write enable bit for software handshake request
bits : 1 - 2 (2 bit)

sglreq : Software handshake single request for channel destination
bits : 2 - 4 (3 bit)

sglreq_we : Write enable bit for software handshake
bits : 3 - 6 (4 bit)

lst : Software handshake last request for channel destination
bits : 4 - 8 (5 bit)

lst_we : Write enable bit for software handshake last request
bits : 5 - 10 (6 bit)


channel[5]-channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-blk_tfr

Channel Block Transfer Resume Request Register
address_offset : 0x1548 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[5]-channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-blk_tfr channel[5]-channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-blk_tfr read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 resumereq

resumereq : Block transfer resume request
bits : 0 - 0 (1 bit)


channel[5]-channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-axi_id

Channel AXI ID Register
address_offset : 0x1550 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[5]-channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-axi_id channel[5]-channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-axi_id read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

channel[5]-channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-axi_qos

AXI QOS Register
address_offset : 0x1558 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[5]-channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-axi_qos channel[5]-channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-axi_qos read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

channel[0]-axi_qos

AXI QOS Register
address_offset : 0x158 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[0]-axi_qos channel[0]-axi_qos read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

channel[5]-channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-intstatus_en

Interrupt Status Enable Register
address_offset : 0x1580 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[5]-channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-intstatus_en channel[5]-channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-intstatus_en read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 block_tfr_done tfr_done src_transcomp dst_transcomp src_dec_err dst_dec_err src_slv_err dst_slv_err lli_rd_dec_err lli_wr_dec_err lli_rd_slv_err lli_wr_slv_err

block_tfr_done : Block transfer done
bits : 0 - 0 (1 bit)

tfr_done : Transfer done
bits : 1 - 2 (2 bit)

src_transcomp : Source transaction complete
bits : 3 - 6 (4 bit)

dst_transcomp : Destination transaction complete
bits : 4 - 8 (5 bit)

src_dec_err : Source Decode Error
bits : 5 - 10 (6 bit)

dst_dec_err : Destination Decode Error
bits : 6 - 12 (7 bit)

src_slv_err : Source Slave Error
bits : 7 - 14 (8 bit)

dst_slv_err : Destination Slave Error
bits : 8 - 16 (9 bit)

lli_rd_dec_err : LLI Read Decode Error Status Enable
bits : 9 - 18 (10 bit)

lli_wr_dec_err : LLI WRITE Decode Error
bits : 10 - 20 (11 bit)

lli_rd_slv_err : LLI Read Slave Error
bits : 11 - 22 (12 bit)

lli_wr_slv_err : LLI WRITE Slave Error
bits : 12 - 24 (13 bit)


channel[5]-channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-intstatus

Channel Interrupt Status Register
address_offset : 0x1588 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[5]-channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-intstatus channel[5]-channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-intstatus read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 block_tfr_done tfr_done src_transcomp dst_transcomp src_dec_err dst_dec_err src_slv_err dst_slv_err lli_rd_dec_err lli_wr_dec_err lli_rd_slv_err lli_wr_slv_err

block_tfr_done : Block transfer done
bits : 0 - 0 (1 bit)

tfr_done : Transfer done
bits : 1 - 2 (2 bit)

src_transcomp : Source transaction complete
bits : 3 - 6 (4 bit)

dst_transcomp : Destination transaction complete
bits : 4 - 8 (5 bit)

src_dec_err : Source Decode Error
bits : 5 - 10 (6 bit)

dst_dec_err : Destination Decode Error
bits : 6 - 12 (7 bit)

src_slv_err : Source Slave Error
bits : 7 - 14 (8 bit)

dst_slv_err : Destination Slave Error
bits : 8 - 16 (9 bit)

lli_rd_dec_err : LLI Read Decode Error Status Enable
bits : 9 - 18 (10 bit)

lli_wr_dec_err : LLI WRITE Decode Error
bits : 10 - 20 (11 bit)

lli_rd_slv_err : LLI Read Slave Error
bits : 11 - 22 (12 bit)

lli_wr_slv_err : LLI WRITE Slave Error
bits : 12 - 24 (13 bit)


channel[5]-channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-intsignal_en

Interrupt Signal Enable Register
address_offset : 0x1590 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[5]-channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-intsignal_en channel[5]-channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-intsignal_en read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 block_tfr_done tfr_done src_transcomp dst_transcomp src_dec_err dst_dec_err src_slv_err dst_slv_err lli_rd_dec_err lli_wr_dec_err lli_rd_slv_err lli_wr_slv_err

block_tfr_done : Block transfer done
bits : 0 - 0 (1 bit)

tfr_done : Transfer done
bits : 1 - 2 (2 bit)

src_transcomp : Source transaction complete
bits : 3 - 6 (4 bit)

dst_transcomp : Destination transaction complete
bits : 4 - 8 (5 bit)

src_dec_err : Source Decode Error
bits : 5 - 10 (6 bit)

dst_dec_err : Destination Decode Error
bits : 6 - 12 (7 bit)

src_slv_err : Source Slave Error
bits : 7 - 14 (8 bit)

dst_slv_err : Destination Slave Error
bits : 8 - 16 (9 bit)

lli_rd_dec_err : LLI Read Decode Error Status Enable
bits : 9 - 18 (10 bit)

lli_wr_dec_err : LLI WRITE Decode Error
bits : 10 - 20 (11 bit)

lli_rd_slv_err : LLI Read Slave Error
bits : 11 - 22 (12 bit)

lli_wr_slv_err : LLI WRITE Slave Error
bits : 12 - 24 (13 bit)


channel[5]-channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-intclear

Interrupt Clear Register
address_offset : 0x1598 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[5]-channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-intclear channel[5]-channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-intclear read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 block_tfr_done tfr_done src_transcomp dst_transcomp src_dec_err dst_dec_err src_slv_err dst_slv_err lli_rd_dec_err lli_wr_dec_err lli_rd_slv_err lli_wr_slv_err

block_tfr_done : Block transfer done
bits : 0 - 0 (1 bit)

tfr_done : Transfer done
bits : 1 - 2 (2 bit)

src_transcomp : Source transaction complete
bits : 3 - 6 (4 bit)

dst_transcomp : Destination transaction complete
bits : 4 - 8 (5 bit)

src_dec_err : Source Decode Error
bits : 5 - 10 (6 bit)

dst_dec_err : Destination Decode Error
bits : 6 - 12 (7 bit)

src_slv_err : Source Slave Error
bits : 7 - 14 (8 bit)

dst_slv_err : Destination Slave Error
bits : 8 - 16 (9 bit)

lli_rd_dec_err : LLI Read Decode Error Status Enable
bits : 9 - 18 (10 bit)

lli_wr_dec_err : LLI WRITE Decode Error
bits : 10 - 20 (11 bit)

lli_rd_slv_err : LLI Read Slave Error
bits : 11 - 22 (12 bit)

lli_wr_slv_err : LLI WRITE Slave Error
bits : 12 - 24 (13 bit)


channel[5]-channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-_reserved

Padding to make structure size 256 bytes so that channels[] is an array
address_offset : 0x15F8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[5]-channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-_reserved channel[5]-channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-_reserved read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

chen

Channel Enable Register
address_offset : 0x18 Bytes (0x0)
size : 64 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

chen chen read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 Resets to Resets to Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ch1_en ch2_en ch3_en ch4_en ch5_en ch6_en ch1_en_we ch2_en_we ch3_en_we ch4_en_we ch5_en_we ch6_en_we ch1_susp ch2_susp ch3_susp ch4_susp ch5_susp ch6_susp ch1_susp_we ch2_susp_we ch3_susp_we ch4_susp_we ch5_susp_we ch6_susp_we ch1_abort ch2_abort ch3_abort ch4_abort ch5_abort ch6_abort ch1_abort_we ch2_abort_we ch3_abort_we ch4_abort_we ch5_abort_we ch6_abort_we

ch1_en : Enable channel %s
bits : 0 - 0 (1 bit)

ch2_en : Enable channel %s
bits : 0 - 0 (1 bit)

ch3_en : Enable channel %s
bits : 0 - 0 (1 bit)

ch4_en : Enable channel %s
bits : 0 - 0 (1 bit)

ch5_en : Enable channel %s
bits : 0 - 0 (1 bit)

ch6_en : Enable channel %s
bits : 0 - 0 (1 bit)

ch1_en_we : Write enable channel %s
bits : 8 - 16 (9 bit)

ch2_en_we : Write enable channel %s
bits : 8 - 16 (9 bit)

ch3_en_we : Write enable channel %s
bits : 8 - 16 (9 bit)

ch4_en_we : Write enable channel %s
bits : 8 - 16 (9 bit)

ch5_en_we : Write enable channel %s
bits : 8 - 16 (9 bit)

ch6_en_we : Write enable channel %s
bits : 8 - 16 (9 bit)

ch1_susp : Suspend request channel %s
bits : 16 - 32 (17 bit)

ch2_susp : Suspend request channel %s
bits : 16 - 32 (17 bit)

ch3_susp : Suspend request channel %s
bits : 16 - 32 (17 bit)

ch4_susp : Suspend request channel %s
bits : 16 - 32 (17 bit)

ch5_susp : Suspend request channel %s
bits : 16 - 32 (17 bit)

ch6_susp : Suspend request channel %s
bits : 16 - 32 (17 bit)

ch1_susp_we : Enable write to ch%s_susp bit
bits : 24 - 48 (25 bit)

ch2_susp_we : Enable write to ch%s_susp bit
bits : 24 - 48 (25 bit)

ch3_susp_we : Enable write to ch%s_susp bit
bits : 24 - 48 (25 bit)

ch4_susp_we : Enable write to ch%s_susp bit
bits : 24 - 48 (25 bit)

ch5_susp_we : Enable write to ch%s_susp bit
bits : 24 - 48 (25 bit)

ch6_susp_we : Enable write to ch%s_susp bit
bits : 24 - 48 (25 bit)

ch1_abort : Abort request channel %s
bits : 32 - 64 (33 bit)

ch2_abort : Abort request channel %s
bits : 32 - 64 (33 bit)

ch3_abort : Abort request channel %s
bits : 32 - 64 (33 bit)

ch4_abort : Abort request channel %s
bits : 32 - 64 (33 bit)

ch5_abort : Abort request channel %s
bits : 32 - 64 (33 bit)

ch6_abort : Abort request channel %s
bits : 32 - 64 (33 bit)

ch1_abort_we : Enable write to ch%s_abort bit
bits : 40 - 80 (41 bit)

ch2_abort_we : Enable write to ch%s_abort bit
bits : 40 - 80 (41 bit)

ch3_abort_we : Enable write to ch%s_abort bit
bits : 40 - 80 (41 bit)

ch4_abort_we : Enable write to ch%s_abort bit
bits : 40 - 80 (41 bit)

ch5_abort_we : Enable write to ch%s_abort bit
bits : 40 - 80 (41 bit)

ch6_abort_we : Enable write to ch%s_abort bit
bits : 40 - 80 (41 bit)


channel[0]-intstatus_en

Interrupt Status Enable Register
address_offset : 0x180 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[0]-intstatus_en channel[0]-intstatus_en read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 block_tfr_done tfr_done src_transcomp dst_transcomp src_dec_err dst_dec_err src_slv_err dst_slv_err lli_rd_dec_err lli_wr_dec_err lli_rd_slv_err lli_wr_slv_err

block_tfr_done : Block transfer done
bits : 0 - 0 (1 bit)

tfr_done : Transfer done
bits : 1 - 2 (2 bit)

src_transcomp : Source transaction complete
bits : 3 - 6 (4 bit)

dst_transcomp : Destination transaction complete
bits : 4 - 8 (5 bit)

src_dec_err : Source Decode Error
bits : 5 - 10 (6 bit)

dst_dec_err : Destination Decode Error
bits : 6 - 12 (7 bit)

src_slv_err : Source Slave Error
bits : 7 - 14 (8 bit)

dst_slv_err : Destination Slave Error
bits : 8 - 16 (9 bit)

lli_rd_dec_err : LLI Read Decode Error Status Enable
bits : 9 - 18 (10 bit)

lli_wr_dec_err : LLI WRITE Decode Error
bits : 10 - 20 (11 bit)

lli_rd_slv_err : LLI Read Slave Error
bits : 11 - 22 (12 bit)

lli_wr_slv_err : LLI WRITE Slave Error
bits : 12 - 24 (13 bit)


channel[0]-intstatus

Channel Interrupt Status Register
address_offset : 0x188 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[0]-intstatus channel[0]-intstatus read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 block_tfr_done tfr_done src_transcomp dst_transcomp src_dec_err dst_dec_err src_slv_err dst_slv_err lli_rd_dec_err lli_wr_dec_err lli_rd_slv_err lli_wr_slv_err

block_tfr_done : Block transfer done
bits : 0 - 0 (1 bit)

tfr_done : Transfer done
bits : 1 - 2 (2 bit)

src_transcomp : Source transaction complete
bits : 3 - 6 (4 bit)

dst_transcomp : Destination transaction complete
bits : 4 - 8 (5 bit)

src_dec_err : Source Decode Error
bits : 5 - 10 (6 bit)

dst_dec_err : Destination Decode Error
bits : 6 - 12 (7 bit)

src_slv_err : Source Slave Error
bits : 7 - 14 (8 bit)

dst_slv_err : Destination Slave Error
bits : 8 - 16 (9 bit)

lli_rd_dec_err : LLI Read Decode Error Status Enable
bits : 9 - 18 (10 bit)

lli_wr_dec_err : LLI WRITE Decode Error
bits : 10 - 20 (11 bit)

lli_rd_slv_err : LLI Read Slave Error
bits : 11 - 22 (12 bit)

lli_wr_slv_err : LLI WRITE Slave Error
bits : 12 - 24 (13 bit)


channel[0]-intsignal_en

Interrupt Signal Enable Register
address_offset : 0x190 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[0]-intsignal_en channel[0]-intsignal_en read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 block_tfr_done tfr_done src_transcomp dst_transcomp src_dec_err dst_dec_err src_slv_err dst_slv_err lli_rd_dec_err lli_wr_dec_err lli_rd_slv_err lli_wr_slv_err

block_tfr_done : Block transfer done
bits : 0 - 0 (1 bit)

tfr_done : Transfer done
bits : 1 - 2 (2 bit)

src_transcomp : Source transaction complete
bits : 3 - 6 (4 bit)

dst_transcomp : Destination transaction complete
bits : 4 - 8 (5 bit)

src_dec_err : Source Decode Error
bits : 5 - 10 (6 bit)

dst_dec_err : Destination Decode Error
bits : 6 - 12 (7 bit)

src_slv_err : Source Slave Error
bits : 7 - 14 (8 bit)

dst_slv_err : Destination Slave Error
bits : 8 - 16 (9 bit)

lli_rd_dec_err : LLI Read Decode Error Status Enable
bits : 9 - 18 (10 bit)

lli_wr_dec_err : LLI WRITE Decode Error
bits : 10 - 20 (11 bit)

lli_rd_slv_err : LLI Read Slave Error
bits : 11 - 22 (12 bit)

lli_wr_slv_err : LLI WRITE Slave Error
bits : 12 - 24 (13 bit)


channel[0]-intclear

Interrupt Clear Register
address_offset : 0x198 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[0]-intclear channel[0]-intclear read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 block_tfr_done tfr_done src_transcomp dst_transcomp src_dec_err dst_dec_err src_slv_err dst_slv_err lli_rd_dec_err lli_wr_dec_err lli_rd_slv_err lli_wr_slv_err

block_tfr_done : Block transfer done
bits : 0 - 0 (1 bit)

tfr_done : Transfer done
bits : 1 - 2 (2 bit)

src_transcomp : Source transaction complete
bits : 3 - 6 (4 bit)

dst_transcomp : Destination transaction complete
bits : 4 - 8 (5 bit)

src_dec_err : Source Decode Error
bits : 5 - 10 (6 bit)

dst_dec_err : Destination Decode Error
bits : 6 - 12 (7 bit)

src_slv_err : Source Slave Error
bits : 7 - 14 (8 bit)

dst_slv_err : Destination Slave Error
bits : 8 - 16 (9 bit)

lli_rd_dec_err : LLI Read Decode Error Status Enable
bits : 9 - 18 (10 bit)

lli_wr_dec_err : LLI WRITE Decode Error
bits : 10 - 20 (11 bit)

lli_rd_slv_err : LLI Read Slave Error
bits : 11 - 22 (12 bit)

lli_wr_slv_err : LLI WRITE Slave Error
bits : 12 - 24 (13 bit)


channel[0]-_reserved

Padding to make structure size 256 bytes so that channels[] is an array
address_offset : 0x1F8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[0]-_reserved channel[0]-_reserved read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

intstatus

Interrupt Status Register
address_offset : 0x30 Bytes (0x0)
size : 64 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

intstatus intstatus read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 Resets to Resets to Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ch1_intstat ch2_intstat ch3_intstat ch4_intstat ch5_intstat ch6_intstat commonreg_intstat

ch1_intstat : Channel %s interrupt bit
bits : 0 - 0 (1 bit)

ch2_intstat : Channel %s interrupt bit
bits : 0 - 0 (1 bit)

ch3_intstat : Channel %s interrupt bit
bits : 0 - 0 (1 bit)

ch4_intstat : Channel %s interrupt bit
bits : 0 - 0 (1 bit)

ch5_intstat : Channel %s interrupt bit
bits : 0 - 0 (1 bit)

ch6_intstat : Channel %s interrupt bit
bits : 0 - 0 (1 bit)

commonreg_intstat : Common register status bit
bits : 16 - 32 (17 bit)


channel[1]-channel[0]-sar

SAR Address Register
address_offset : 0x300 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[1]-channel[0]-sar channel[1]-channel[0]-sar read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

channel[1]-channel[0]-dar

DAR Address Register
address_offset : 0x308 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[1]-channel[0]-dar channel[1]-channel[0]-dar read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

channel[1]-channel[0]-block_ts

Block Transfer Size Register
address_offset : 0x310 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[1]-channel[0]-block_ts channel[1]-channel[0]-block_ts read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 block_ts

block_ts : Block transfer size
bits : 0 - 21 (22 bit)


channel[1]-channel[0]-ctl

Control Register
address_offset : 0x318 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[1]-channel[0]-ctl channel[1]-channel[0]-ctl read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sms dms sinc dinc src_tr_width dst_tr_width src_msize dst_msize nonposted_lastwrite_en arlen_en arlen awlen_en awlen src_stat_en dst_stat_en ioc_blktfr shadowreg_or_lli_last shadowreg_or_lli_valid

sms : Source master select
bits : 0 - 0 (1 bit)

Enumeration: MASTER_SELECT

0 : axi_master_1

AXI master 1

1 : axi_master_2

AXI master 2

End of enumeration elements list.

dms : Destination master select
bits : 2 - 4 (3 bit)

Enumeration:

End of enumeration elements list.

sinc : Source address increment
bits : 4 - 8 (5 bit)

Enumeration: INCREMENT

0 : increment

Increment address

1 : nochange

Don't increment address

End of enumeration elements list.

dinc : Destination address increment
bits : 6 - 12 (7 bit)

Enumeration:

End of enumeration elements list.

src_tr_width : Source transfer width
bits : 8 - 18 (11 bit)

Enumeration: TRANSFER_WIDTH

0 : width_8

8 bits

1 : width_16

16 bits

2 : width_32

32 bits

3 : width_64

64 bits

4 : width_128

128 bits

5 : width_256

256 bits

6 : width_512

512 bits

End of enumeration elements list.

dst_tr_width : Destination transfer width
bits : 11 - 24 (14 bit)

Enumeration:

End of enumeration elements list.

src_msize : Source burst transaction length
bits : 14 - 31 (18 bit)

Enumeration: BURST_LENGTH

0 : length_1

1 data item

1 : length_4

4 data items

2 : length_8

8 data items

3 : length_16

16 data items

4 : length_32

32 data items

5 : length_64

64 data items

6 : length_128

128 data items

7 : length_256

256 data items

8 : length_512

512 data items

9 : length_1024

1024 data items

End of enumeration elements list.

dst_msize : Destination burst transaction length
bits : 18 - 39 (22 bit)

Enumeration:

End of enumeration elements list.

nonposted_lastwrite_en : Non Posted Last Write Enable (posted writes may be used till the end of the block)
bits : 30 - 60 (31 bit)

arlen_en : Source burst length enable
bits : 38 - 76 (39 bit)

arlen : Source burst length
bits : 39 - 85 (47 bit)

awlen_en : Destination burst length enable
bits : 47 - 94 (48 bit)

awlen : Destination burst length
bits : 48 - 103 (56 bit)

src_stat_en : Source status enable
bits : 56 - 112 (57 bit)

dst_stat_en : Destination status enable
bits : 57 - 114 (58 bit)

ioc_blktfr : Interrupt completion of block transfer
bits : 58 - 116 (59 bit)

shadowreg_or_lli_last : Last shadow linked list item (indicates shadowreg/LLI content is the last one)
bits : 62 - 124 (63 bit)

shadowreg_or_lli_valid : last shadow linked list item valid (indicate shadowreg/LLI content is valid)
bits : 63 - 126 (64 bit)


channel[1]-channel[0]-cfg

Configure Register
address_offset : 0x320 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[1]-channel[0]-cfg channel[1]-channel[0]-cfg read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 src_multblk_type dst_multblk_type tt_fc hs_sel_src hs_sel_dst src_hwhs_pol dst_hwhs_pol src_per dst_per ch_prior lock_ch lock_ch_l src_osr_lmt dst_osr_lmt

src_multblk_type : Source multi-block transfer type
bits : 0 - 1 (2 bit)

Enumeration: MULTIBLK_TRANSFER_TYPE

0 : contiguous

Continuous multi-block type

1 : reload

Reload multi-block type

2 : shadow_register

Shadow register based multi-block type

3 : linked_list

Linked list based multi-block type

End of enumeration elements list.

dst_multblk_type : Destination multi-block transfer type
bits : 2 - 5 (4 bit)

Enumeration:

End of enumeration elements list.

tt_fc : Transfer type and flow control
bits : 32 - 66 (35 bit)

Enumeration:

0 : mem2mem_dma

Transfer memory to memory and flow controller is DMAC

1 : mem2prf_dma

Transfer memory to peripheral and flow controller is DMAC

2 : prf2mem_dma

Transfer peripheral to memory and flow controller is DMAC

3 : prf2prf_dma

Transfer peripheral to peripheral and flow controller is DMAC

4 : prf2mem_prf

Transfer peripheral to memory and flow controller is source peripheral

5 : prf2prf_srcprf

Transfer peripheral to peripheral and flow controller is source peripheral

6 : mem2prf_prf

Transfer memory to peripheral and flow controller is destination peripheral

7 : prf2prf_dstprf

Transfer peripheral to peripheral and flow controller is destination peripheral

End of enumeration elements list.

hs_sel_src : Source software or hardware handshaking select
bits : 35 - 70 (36 bit)

Enumeration: HANDSHAKING

0 : hardware

Hardware handshaking is used

1 : software

Software handshaking is used

End of enumeration elements list.

hs_sel_dst : Destination software or hardware handshaking select
bits : 36 - 72 (37 bit)

Enumeration:

End of enumeration elements list.

src_hwhs_pol : Source hardware handshaking interface polarity
bits : 37 - 74 (38 bit)

Enumeration: POLARITY

0 : active_high

Active high

1 : active_low

Active low

End of enumeration elements list.

dst_hwhs_pol : Destination hardware handshaking interface polarity
bits : 38 - 76 (39 bit)

Enumeration:

End of enumeration elements list.

src_per : Assign a hardware handshaking interface to source of channel
bits : 39 - 81 (43 bit)

dst_per : Assign a hardware handshaking interface to destination of channel
bits : 44 - 91 (48 bit)

ch_prior : Channel priority (7 is highest, 0 is lowest)
bits : 49 - 100 (52 bit)

lock_ch : Channel lock bit
bits : 52 - 104 (53 bit)

lock_ch_l : Channel lock level
bits : 53 - 107 (55 bit)

Enumeration:

0 : dma_transfer

Duration of channel is locked for entire DMA transfer

1 : block_transfer

Duration of channel is locked for current block transfer

2 : transaction

Duration of channel is locked for current transaction

End of enumeration elements list.

src_osr_lmt : Source outstanding request limit
bits : 55 - 113 (59 bit)

dst_osr_lmt : Destination outstanding request limit
bits : 59 - 121 (63 bit)


channel[1]-channel[0]-llp

Linked List Pointer register
address_offset : 0x328 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[1]-channel[0]-llp channel[1]-channel[0]-llp read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 lms loc

lms : LLI master select
bits : 0 - 0 (1 bit)

Enumeration:

End of enumeration elements list.

loc : Starting address memeory of LLI block
bits : 6 - 69 (64 bit)


channel[1]-channel[0]-status

Channel Status Register
address_offset : 0x330 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[1]-channel[0]-status channel[1]-channel[0]-status read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cmpltd_blk_size

cmpltd_blk_size : Completed block transfer size
bits : 0 - 21 (22 bit)


channel[1]-channel[0]-swhssrc

Channel Software handshake Source Register
address_offset : 0x338 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[1]-channel[0]-swhssrc channel[1]-channel[0]-swhssrc read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 req req_we sglreq sglreq_we lst lst_we

req : Software handshake request for channel source
bits : 0 - 0 (1 bit)

req_we : Write enable bit for software handshake request
bits : 1 - 2 (2 bit)

sglreq : Software handshake single request for channel source
bits : 2 - 4 (3 bit)

sglreq_we : Write enable bit for software handshake
bits : 3 - 6 (4 bit)

lst : Software handshake last request for channel source
bits : 4 - 8 (5 bit)

lst_we : Write enable bit for software handshake last request
bits : 5 - 10 (6 bit)


channel[1]-channel[0]-swhsdst

Channel Software handshake Destination Register
address_offset : 0x340 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[1]-channel[0]-swhsdst channel[1]-channel[0]-swhsdst read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 req req_we sglreq sglreq_we lst lst_we

req : Software handshake request for channel destination
bits : 0 - 0 (1 bit)

req_we : Write enable bit for software handshake request
bits : 1 - 2 (2 bit)

sglreq : Software handshake single request for channel destination
bits : 2 - 4 (3 bit)

sglreq_we : Write enable bit for software handshake
bits : 3 - 6 (4 bit)

lst : Software handshake last request for channel destination
bits : 4 - 8 (5 bit)

lst_we : Write enable bit for software handshake last request
bits : 5 - 10 (6 bit)


channel[1]-channel[0]-blk_tfr

Channel Block Transfer Resume Request Register
address_offset : 0x348 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[1]-channel[0]-blk_tfr channel[1]-channel[0]-blk_tfr read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 resumereq

resumereq : Block transfer resume request
bits : 0 - 0 (1 bit)


channel[1]-channel[0]-axi_id

Channel AXI ID Register
address_offset : 0x350 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[1]-channel[0]-axi_id channel[1]-channel[0]-axi_id read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

channel[1]-channel[0]-axi_qos

AXI QOS Register
address_offset : 0x358 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[1]-channel[0]-axi_qos channel[1]-channel[0]-axi_qos read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

com_intclear

Common Interrupt Clear Register
address_offset : 0x38 Bytes (0x0)
size : 64 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

com_intclear com_intclear read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 Resets to Resets to Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 slvif_dec_err slvif_wr2ro_err slvif_rd2wo_err slvif_wronhold_err slvif_undefinedreg_dec_err

slvif_dec_err : Clear slvif_dec_err interrupt in com_intstatus
bits : 0 - 0 (1 bit)

slvif_wr2ro_err : Clear slvif_wr2ro_err interrupt in com_intstatus
bits : 1 - 2 (2 bit)

slvif_rd2wo_err : Clear slvif_rd2wo_err interrupt in com_intstatus
bits : 2 - 4 (3 bit)

slvif_wronhold_err : Clear slvif_wronhold_err interrupt in com_intstatus
bits : 3 - 6 (4 bit)

slvif_undefinedreg_dec_err : Clear slvif_undefinedreg_dec_err in com_intstatus
bits : 8 - 16 (9 bit)


channel[1]-channel[0]-intstatus_en

Interrupt Status Enable Register
address_offset : 0x380 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[1]-channel[0]-intstatus_en channel[1]-channel[0]-intstatus_en read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 block_tfr_done tfr_done src_transcomp dst_transcomp src_dec_err dst_dec_err src_slv_err dst_slv_err lli_rd_dec_err lli_wr_dec_err lli_rd_slv_err lli_wr_slv_err

block_tfr_done : Block transfer done
bits : 0 - 0 (1 bit)

tfr_done : Transfer done
bits : 1 - 2 (2 bit)

src_transcomp : Source transaction complete
bits : 3 - 6 (4 bit)

dst_transcomp : Destination transaction complete
bits : 4 - 8 (5 bit)

src_dec_err : Source Decode Error
bits : 5 - 10 (6 bit)

dst_dec_err : Destination Decode Error
bits : 6 - 12 (7 bit)

src_slv_err : Source Slave Error
bits : 7 - 14 (8 bit)

dst_slv_err : Destination Slave Error
bits : 8 - 16 (9 bit)

lli_rd_dec_err : LLI Read Decode Error Status Enable
bits : 9 - 18 (10 bit)

lli_wr_dec_err : LLI WRITE Decode Error
bits : 10 - 20 (11 bit)

lli_rd_slv_err : LLI Read Slave Error
bits : 11 - 22 (12 bit)

lli_wr_slv_err : LLI WRITE Slave Error
bits : 12 - 24 (13 bit)


channel[1]-channel[0]-intstatus

Channel Interrupt Status Register
address_offset : 0x388 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[1]-channel[0]-intstatus channel[1]-channel[0]-intstatus read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 block_tfr_done tfr_done src_transcomp dst_transcomp src_dec_err dst_dec_err src_slv_err dst_slv_err lli_rd_dec_err lli_wr_dec_err lli_rd_slv_err lli_wr_slv_err

block_tfr_done : Block transfer done
bits : 0 - 0 (1 bit)

tfr_done : Transfer done
bits : 1 - 2 (2 bit)

src_transcomp : Source transaction complete
bits : 3 - 6 (4 bit)

dst_transcomp : Destination transaction complete
bits : 4 - 8 (5 bit)

src_dec_err : Source Decode Error
bits : 5 - 10 (6 bit)

dst_dec_err : Destination Decode Error
bits : 6 - 12 (7 bit)

src_slv_err : Source Slave Error
bits : 7 - 14 (8 bit)

dst_slv_err : Destination Slave Error
bits : 8 - 16 (9 bit)

lli_rd_dec_err : LLI Read Decode Error Status Enable
bits : 9 - 18 (10 bit)

lli_wr_dec_err : LLI WRITE Decode Error
bits : 10 - 20 (11 bit)

lli_rd_slv_err : LLI Read Slave Error
bits : 11 - 22 (12 bit)

lli_wr_slv_err : LLI WRITE Slave Error
bits : 12 - 24 (13 bit)


channel[1]-channel[0]-intsignal_en

Interrupt Signal Enable Register
address_offset : 0x390 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[1]-channel[0]-intsignal_en channel[1]-channel[0]-intsignal_en read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 block_tfr_done tfr_done src_transcomp dst_transcomp src_dec_err dst_dec_err src_slv_err dst_slv_err lli_rd_dec_err lli_wr_dec_err lli_rd_slv_err lli_wr_slv_err

block_tfr_done : Block transfer done
bits : 0 - 0 (1 bit)

tfr_done : Transfer done
bits : 1 - 2 (2 bit)

src_transcomp : Source transaction complete
bits : 3 - 6 (4 bit)

dst_transcomp : Destination transaction complete
bits : 4 - 8 (5 bit)

src_dec_err : Source Decode Error
bits : 5 - 10 (6 bit)

dst_dec_err : Destination Decode Error
bits : 6 - 12 (7 bit)

src_slv_err : Source Slave Error
bits : 7 - 14 (8 bit)

dst_slv_err : Destination Slave Error
bits : 8 - 16 (9 bit)

lli_rd_dec_err : LLI Read Decode Error Status Enable
bits : 9 - 18 (10 bit)

lli_wr_dec_err : LLI WRITE Decode Error
bits : 10 - 20 (11 bit)

lli_rd_slv_err : LLI Read Slave Error
bits : 11 - 22 (12 bit)

lli_wr_slv_err : LLI WRITE Slave Error
bits : 12 - 24 (13 bit)


channel[1]-channel[0]-intclear

Interrupt Clear Register
address_offset : 0x398 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[1]-channel[0]-intclear channel[1]-channel[0]-intclear read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 block_tfr_done tfr_done src_transcomp dst_transcomp src_dec_err dst_dec_err src_slv_err dst_slv_err lli_rd_dec_err lli_wr_dec_err lli_rd_slv_err lli_wr_slv_err

block_tfr_done : Block transfer done
bits : 0 - 0 (1 bit)

tfr_done : Transfer done
bits : 1 - 2 (2 bit)

src_transcomp : Source transaction complete
bits : 3 - 6 (4 bit)

dst_transcomp : Destination transaction complete
bits : 4 - 8 (5 bit)

src_dec_err : Source Decode Error
bits : 5 - 10 (6 bit)

dst_dec_err : Destination Decode Error
bits : 6 - 12 (7 bit)

src_slv_err : Source Slave Error
bits : 7 - 14 (8 bit)

dst_slv_err : Destination Slave Error
bits : 8 - 16 (9 bit)

lli_rd_dec_err : LLI Read Decode Error Status Enable
bits : 9 - 18 (10 bit)

lli_wr_dec_err : LLI WRITE Decode Error
bits : 10 - 20 (11 bit)

lli_rd_slv_err : LLI Read Slave Error
bits : 11 - 22 (12 bit)

lli_wr_slv_err : LLI WRITE Slave Error
bits : 12 - 24 (13 bit)


channel[1]-channel[0]-_reserved

Padding to make structure size 256 bytes so that channels[] is an array
address_offset : 0x3F8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[1]-channel[0]-_reserved channel[1]-channel[0]-_reserved read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

com_intstatus_en

Common Interrupt Status Enable Register
address_offset : 0x40 Bytes (0x0)
size : 64 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

com_intstatus_en com_intstatus_en read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 Resets to Resets to Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 slvif_dec_err slvif_wr2ro_err slvif_rd2wo_err slvif_wronhold_err slvif_undefinedreg_dec_err

slvif_dec_err : Slave Interface Common Register Decode Error
bits : 0 - 0 (1 bit)

slvif_wr2ro_err : Slave Interface Common Register Write to Read only Error
bits : 1 - 2 (2 bit)

slvif_rd2wo_err : Slave Interface Common Register Read to Write-only Error
bits : 2 - 4 (3 bit)

slvif_wronhold_err : Slave Interface Common Register Write On Hold Error
bits : 3 - 6 (4 bit)

slvif_undefinedreg_dec_err : Slave Interface Undefined Register Decode Error
bits : 8 - 16 (9 bit)


com_intsignal_en

Common Interrupt Signal Enable Register
address_offset : 0x48 Bytes (0x0)
size : 64 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

com_intsignal_en com_intsignal_en read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 Resets to Resets to Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 slvif_dec_err slvif_wr2ro_err slvif_rd2wo_err slvif_wronhold_err slvif_undefinedreg_dec_err

slvif_dec_err : Slave Interface Common Register Decode Error
bits : 0 - 0 (1 bit)

slvif_wr2ro_err : Slave Interface Common Register Write to Read only Error
bits : 1 - 2 (2 bit)

slvif_rd2wo_err : Slave Interface Common Register Read to Write-only Error
bits : 2 - 4 (3 bit)

slvif_wronhold_err : Slave Interface Common Register Write On Hold Error
bits : 3 - 6 (4 bit)

slvif_undefinedreg_dec_err : Slave Interface Undefined Register Decode Error
bits : 8 - 16 (9 bit)


com_intstatus

Common Interrupt Status
address_offset : 0x50 Bytes (0x0)
size : 64 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

com_intstatus com_intstatus read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 Resets to Resets to Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 slvif_dec_err slvif_wr2ro_err slvif_rd2wo_err slvif_wronhold_err slvif_undefinedreg_dec_err

slvif_dec_err : Slave Interface Common Register Decode Error
bits : 0 - 0 (1 bit)

slvif_wr2ro_err : Slave Interface Common Register Write to Read only Error
bits : 1 - 2 (2 bit)

slvif_rd2wo_err : Slave Interface Common Register Read to Write-only Error
bits : 2 - 4 (3 bit)

slvif_wronhold_err : Slave Interface Common Register Write On Hold Error
bits : 3 - 6 (4 bit)

slvif_undefinedreg_dec_err : Slave Interface Undefined Register Decode Error
bits : 8 - 16 (9 bit)


reset

Reset register
address_offset : 0x58 Bytes (0x0)
size : 64 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

reset reset read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 Resets to Resets to Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rst

rst : DMAC reset request bit
bits : 0 - 0 (1 bit)


channel[2]-channel[1]-channel[0]-sar

SAR Address Register
address_offset : 0x600 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[2]-channel[1]-channel[0]-sar channel[2]-channel[1]-channel[0]-sar read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

channel[2]-channel[1]-channel[0]-dar

DAR Address Register
address_offset : 0x608 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[2]-channel[1]-channel[0]-dar channel[2]-channel[1]-channel[0]-dar read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

channel[2]-channel[1]-channel[0]-block_ts

Block Transfer Size Register
address_offset : 0x610 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[2]-channel[1]-channel[0]-block_ts channel[2]-channel[1]-channel[0]-block_ts read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 block_ts

block_ts : Block transfer size
bits : 0 - 21 (22 bit)


channel[2]-channel[1]-channel[0]-ctl

Control Register
address_offset : 0x618 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[2]-channel[1]-channel[0]-ctl channel[2]-channel[1]-channel[0]-ctl read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sms dms sinc dinc src_tr_width dst_tr_width src_msize dst_msize nonposted_lastwrite_en arlen_en arlen awlen_en awlen src_stat_en dst_stat_en ioc_blktfr shadowreg_or_lli_last shadowreg_or_lli_valid

sms : Source master select
bits : 0 - 0 (1 bit)

Enumeration: MASTER_SELECT

0 : axi_master_1

AXI master 1

1 : axi_master_2

AXI master 2

End of enumeration elements list.

dms : Destination master select
bits : 2 - 4 (3 bit)

Enumeration:

End of enumeration elements list.

sinc : Source address increment
bits : 4 - 8 (5 bit)

Enumeration: INCREMENT

0 : increment

Increment address

1 : nochange

Don't increment address

End of enumeration elements list.

dinc : Destination address increment
bits : 6 - 12 (7 bit)

Enumeration:

End of enumeration elements list.

src_tr_width : Source transfer width
bits : 8 - 18 (11 bit)

Enumeration: TRANSFER_WIDTH

0 : width_8

8 bits

1 : width_16

16 bits

2 : width_32

32 bits

3 : width_64

64 bits

4 : width_128

128 bits

5 : width_256

256 bits

6 : width_512

512 bits

End of enumeration elements list.

dst_tr_width : Destination transfer width
bits : 11 - 24 (14 bit)

Enumeration:

End of enumeration elements list.

src_msize : Source burst transaction length
bits : 14 - 31 (18 bit)

Enumeration: BURST_LENGTH

0 : length_1

1 data item

1 : length_4

4 data items

2 : length_8

8 data items

3 : length_16

16 data items

4 : length_32

32 data items

5 : length_64

64 data items

6 : length_128

128 data items

7 : length_256

256 data items

8 : length_512

512 data items

9 : length_1024

1024 data items

End of enumeration elements list.

dst_msize : Destination burst transaction length
bits : 18 - 39 (22 bit)

Enumeration:

End of enumeration elements list.

nonposted_lastwrite_en : Non Posted Last Write Enable (posted writes may be used till the end of the block)
bits : 30 - 60 (31 bit)

arlen_en : Source burst length enable
bits : 38 - 76 (39 bit)

arlen : Source burst length
bits : 39 - 85 (47 bit)

awlen_en : Destination burst length enable
bits : 47 - 94 (48 bit)

awlen : Destination burst length
bits : 48 - 103 (56 bit)

src_stat_en : Source status enable
bits : 56 - 112 (57 bit)

dst_stat_en : Destination status enable
bits : 57 - 114 (58 bit)

ioc_blktfr : Interrupt completion of block transfer
bits : 58 - 116 (59 bit)

shadowreg_or_lli_last : Last shadow linked list item (indicates shadowreg/LLI content is the last one)
bits : 62 - 124 (63 bit)

shadowreg_or_lli_valid : last shadow linked list item valid (indicate shadowreg/LLI content is valid)
bits : 63 - 126 (64 bit)


channel[2]-channel[1]-channel[0]-cfg

Configure Register
address_offset : 0x620 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[2]-channel[1]-channel[0]-cfg channel[2]-channel[1]-channel[0]-cfg read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 src_multblk_type dst_multblk_type tt_fc hs_sel_src hs_sel_dst src_hwhs_pol dst_hwhs_pol src_per dst_per ch_prior lock_ch lock_ch_l src_osr_lmt dst_osr_lmt

src_multblk_type : Source multi-block transfer type
bits : 0 - 1 (2 bit)

Enumeration: MULTIBLK_TRANSFER_TYPE

0 : contiguous

Continuous multi-block type

1 : reload

Reload multi-block type

2 : shadow_register

Shadow register based multi-block type

3 : linked_list

Linked list based multi-block type

End of enumeration elements list.

dst_multblk_type : Destination multi-block transfer type
bits : 2 - 5 (4 bit)

Enumeration:

End of enumeration elements list.

tt_fc : Transfer type and flow control
bits : 32 - 66 (35 bit)

Enumeration:

0 : mem2mem_dma

Transfer memory to memory and flow controller is DMAC

1 : mem2prf_dma

Transfer memory to peripheral and flow controller is DMAC

2 : prf2mem_dma

Transfer peripheral to memory and flow controller is DMAC

3 : prf2prf_dma

Transfer peripheral to peripheral and flow controller is DMAC

4 : prf2mem_prf

Transfer peripheral to memory and flow controller is source peripheral

5 : prf2prf_srcprf

Transfer peripheral to peripheral and flow controller is source peripheral

6 : mem2prf_prf

Transfer memory to peripheral and flow controller is destination peripheral

7 : prf2prf_dstprf

Transfer peripheral to peripheral and flow controller is destination peripheral

End of enumeration elements list.

hs_sel_src : Source software or hardware handshaking select
bits : 35 - 70 (36 bit)

Enumeration: HANDSHAKING

0 : hardware

Hardware handshaking is used

1 : software

Software handshaking is used

End of enumeration elements list.

hs_sel_dst : Destination software or hardware handshaking select
bits : 36 - 72 (37 bit)

Enumeration:

End of enumeration elements list.

src_hwhs_pol : Source hardware handshaking interface polarity
bits : 37 - 74 (38 bit)

Enumeration: POLARITY

0 : active_high

Active high

1 : active_low

Active low

End of enumeration elements list.

dst_hwhs_pol : Destination hardware handshaking interface polarity
bits : 38 - 76 (39 bit)

Enumeration:

End of enumeration elements list.

src_per : Assign a hardware handshaking interface to source of channel
bits : 39 - 81 (43 bit)

dst_per : Assign a hardware handshaking interface to destination of channel
bits : 44 - 91 (48 bit)

ch_prior : Channel priority (7 is highest, 0 is lowest)
bits : 49 - 100 (52 bit)

lock_ch : Channel lock bit
bits : 52 - 104 (53 bit)

lock_ch_l : Channel lock level
bits : 53 - 107 (55 bit)

Enumeration:

0 : dma_transfer

Duration of channel is locked for entire DMA transfer

1 : block_transfer

Duration of channel is locked for current block transfer

2 : transaction

Duration of channel is locked for current transaction

End of enumeration elements list.

src_osr_lmt : Source outstanding request limit
bits : 55 - 113 (59 bit)

dst_osr_lmt : Destination outstanding request limit
bits : 59 - 121 (63 bit)


channel[2]-channel[1]-channel[0]-llp

Linked List Pointer register
address_offset : 0x628 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[2]-channel[1]-channel[0]-llp channel[2]-channel[1]-channel[0]-llp read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 lms loc

lms : LLI master select
bits : 0 - 0 (1 bit)

Enumeration:

End of enumeration elements list.

loc : Starting address memeory of LLI block
bits : 6 - 69 (64 bit)


channel[2]-channel[1]-channel[0]-status

Channel Status Register
address_offset : 0x630 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[2]-channel[1]-channel[0]-status channel[2]-channel[1]-channel[0]-status read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cmpltd_blk_size

cmpltd_blk_size : Completed block transfer size
bits : 0 - 21 (22 bit)


channel[2]-channel[1]-channel[0]-swhssrc

Channel Software handshake Source Register
address_offset : 0x638 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[2]-channel[1]-channel[0]-swhssrc channel[2]-channel[1]-channel[0]-swhssrc read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 req req_we sglreq sglreq_we lst lst_we

req : Software handshake request for channel source
bits : 0 - 0 (1 bit)

req_we : Write enable bit for software handshake request
bits : 1 - 2 (2 bit)

sglreq : Software handshake single request for channel source
bits : 2 - 4 (3 bit)

sglreq_we : Write enable bit for software handshake
bits : 3 - 6 (4 bit)

lst : Software handshake last request for channel source
bits : 4 - 8 (5 bit)

lst_we : Write enable bit for software handshake last request
bits : 5 - 10 (6 bit)


channel[2]-channel[1]-channel[0]-swhsdst

Channel Software handshake Destination Register
address_offset : 0x640 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[2]-channel[1]-channel[0]-swhsdst channel[2]-channel[1]-channel[0]-swhsdst read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 req req_we sglreq sglreq_we lst lst_we

req : Software handshake request for channel destination
bits : 0 - 0 (1 bit)

req_we : Write enable bit for software handshake request
bits : 1 - 2 (2 bit)

sglreq : Software handshake single request for channel destination
bits : 2 - 4 (3 bit)

sglreq_we : Write enable bit for software handshake
bits : 3 - 6 (4 bit)

lst : Software handshake last request for channel destination
bits : 4 - 8 (5 bit)

lst_we : Write enable bit for software handshake last request
bits : 5 - 10 (6 bit)


channel[2]-channel[1]-channel[0]-blk_tfr

Channel Block Transfer Resume Request Register
address_offset : 0x648 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[2]-channel[1]-channel[0]-blk_tfr channel[2]-channel[1]-channel[0]-blk_tfr read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 resumereq

resumereq : Block transfer resume request
bits : 0 - 0 (1 bit)


channel[2]-channel[1]-channel[0]-axi_id

Channel AXI ID Register
address_offset : 0x650 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[2]-channel[1]-channel[0]-axi_id channel[2]-channel[1]-channel[0]-axi_id read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

channel[2]-channel[1]-channel[0]-axi_qos

AXI QOS Register
address_offset : 0x658 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[2]-channel[1]-channel[0]-axi_qos channel[2]-channel[1]-channel[0]-axi_qos read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

channel[2]-channel[1]-channel[0]-intstatus_en

Interrupt Status Enable Register
address_offset : 0x680 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[2]-channel[1]-channel[0]-intstatus_en channel[2]-channel[1]-channel[0]-intstatus_en read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 block_tfr_done tfr_done src_transcomp dst_transcomp src_dec_err dst_dec_err src_slv_err dst_slv_err lli_rd_dec_err lli_wr_dec_err lli_rd_slv_err lli_wr_slv_err

block_tfr_done : Block transfer done
bits : 0 - 0 (1 bit)

tfr_done : Transfer done
bits : 1 - 2 (2 bit)

src_transcomp : Source transaction complete
bits : 3 - 6 (4 bit)

dst_transcomp : Destination transaction complete
bits : 4 - 8 (5 bit)

src_dec_err : Source Decode Error
bits : 5 - 10 (6 bit)

dst_dec_err : Destination Decode Error
bits : 6 - 12 (7 bit)

src_slv_err : Source Slave Error
bits : 7 - 14 (8 bit)

dst_slv_err : Destination Slave Error
bits : 8 - 16 (9 bit)

lli_rd_dec_err : LLI Read Decode Error Status Enable
bits : 9 - 18 (10 bit)

lli_wr_dec_err : LLI WRITE Decode Error
bits : 10 - 20 (11 bit)

lli_rd_slv_err : LLI Read Slave Error
bits : 11 - 22 (12 bit)

lli_wr_slv_err : LLI WRITE Slave Error
bits : 12 - 24 (13 bit)


channel[2]-channel[1]-channel[0]-intstatus

Channel Interrupt Status Register
address_offset : 0x688 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[2]-channel[1]-channel[0]-intstatus channel[2]-channel[1]-channel[0]-intstatus read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 block_tfr_done tfr_done src_transcomp dst_transcomp src_dec_err dst_dec_err src_slv_err dst_slv_err lli_rd_dec_err lli_wr_dec_err lli_rd_slv_err lli_wr_slv_err

block_tfr_done : Block transfer done
bits : 0 - 0 (1 bit)

tfr_done : Transfer done
bits : 1 - 2 (2 bit)

src_transcomp : Source transaction complete
bits : 3 - 6 (4 bit)

dst_transcomp : Destination transaction complete
bits : 4 - 8 (5 bit)

src_dec_err : Source Decode Error
bits : 5 - 10 (6 bit)

dst_dec_err : Destination Decode Error
bits : 6 - 12 (7 bit)

src_slv_err : Source Slave Error
bits : 7 - 14 (8 bit)

dst_slv_err : Destination Slave Error
bits : 8 - 16 (9 bit)

lli_rd_dec_err : LLI Read Decode Error Status Enable
bits : 9 - 18 (10 bit)

lli_wr_dec_err : LLI WRITE Decode Error
bits : 10 - 20 (11 bit)

lli_rd_slv_err : LLI Read Slave Error
bits : 11 - 22 (12 bit)

lli_wr_slv_err : LLI WRITE Slave Error
bits : 12 - 24 (13 bit)


channel[2]-channel[1]-channel[0]-intsignal_en

Interrupt Signal Enable Register
address_offset : 0x690 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[2]-channel[1]-channel[0]-intsignal_en channel[2]-channel[1]-channel[0]-intsignal_en read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 block_tfr_done tfr_done src_transcomp dst_transcomp src_dec_err dst_dec_err src_slv_err dst_slv_err lli_rd_dec_err lli_wr_dec_err lli_rd_slv_err lli_wr_slv_err

block_tfr_done : Block transfer done
bits : 0 - 0 (1 bit)

tfr_done : Transfer done
bits : 1 - 2 (2 bit)

src_transcomp : Source transaction complete
bits : 3 - 6 (4 bit)

dst_transcomp : Destination transaction complete
bits : 4 - 8 (5 bit)

src_dec_err : Source Decode Error
bits : 5 - 10 (6 bit)

dst_dec_err : Destination Decode Error
bits : 6 - 12 (7 bit)

src_slv_err : Source Slave Error
bits : 7 - 14 (8 bit)

dst_slv_err : Destination Slave Error
bits : 8 - 16 (9 bit)

lli_rd_dec_err : LLI Read Decode Error Status Enable
bits : 9 - 18 (10 bit)

lli_wr_dec_err : LLI WRITE Decode Error
bits : 10 - 20 (11 bit)

lli_rd_slv_err : LLI Read Slave Error
bits : 11 - 22 (12 bit)

lli_wr_slv_err : LLI WRITE Slave Error
bits : 12 - 24 (13 bit)


channel[2]-channel[1]-channel[0]-intclear

Interrupt Clear Register
address_offset : 0x698 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[2]-channel[1]-channel[0]-intclear channel[2]-channel[1]-channel[0]-intclear read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 block_tfr_done tfr_done src_transcomp dst_transcomp src_dec_err dst_dec_err src_slv_err dst_slv_err lli_rd_dec_err lli_wr_dec_err lli_rd_slv_err lli_wr_slv_err

block_tfr_done : Block transfer done
bits : 0 - 0 (1 bit)

tfr_done : Transfer done
bits : 1 - 2 (2 bit)

src_transcomp : Source transaction complete
bits : 3 - 6 (4 bit)

dst_transcomp : Destination transaction complete
bits : 4 - 8 (5 bit)

src_dec_err : Source Decode Error
bits : 5 - 10 (6 bit)

dst_dec_err : Destination Decode Error
bits : 6 - 12 (7 bit)

src_slv_err : Source Slave Error
bits : 7 - 14 (8 bit)

dst_slv_err : Destination Slave Error
bits : 8 - 16 (9 bit)

lli_rd_dec_err : LLI Read Decode Error Status Enable
bits : 9 - 18 (10 bit)

lli_wr_dec_err : LLI WRITE Decode Error
bits : 10 - 20 (11 bit)

lli_rd_slv_err : LLI Read Slave Error
bits : 11 - 22 (12 bit)

lli_wr_slv_err : LLI WRITE Slave Error
bits : 12 - 24 (13 bit)


channel[2]-channel[1]-channel[0]-_reserved

Padding to make structure size 256 bytes so that channels[] is an array
address_offset : 0x6F8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[2]-channel[1]-channel[0]-_reserved channel[2]-channel[1]-channel[0]-_reserved read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

compver

COMPVER Register
address_offset : 0x8 Bytes (0x0)
size : 64 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

compver compver read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 Resets to Resets to Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

channel[3]-channel[2]-channel[1]-channel[0]-sar

SAR Address Register
address_offset : 0xA00 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[3]-channel[2]-channel[1]-channel[0]-sar channel[3]-channel[2]-channel[1]-channel[0]-sar read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

channel[3]-channel[2]-channel[1]-channel[0]-dar

DAR Address Register
address_offset : 0xA08 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[3]-channel[2]-channel[1]-channel[0]-dar channel[3]-channel[2]-channel[1]-channel[0]-dar read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

channel[3]-channel[2]-channel[1]-channel[0]-block_ts

Block Transfer Size Register
address_offset : 0xA10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[3]-channel[2]-channel[1]-channel[0]-block_ts channel[3]-channel[2]-channel[1]-channel[0]-block_ts read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 block_ts

block_ts : Block transfer size
bits : 0 - 21 (22 bit)


channel[3]-channel[2]-channel[1]-channel[0]-ctl

Control Register
address_offset : 0xA18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[3]-channel[2]-channel[1]-channel[0]-ctl channel[3]-channel[2]-channel[1]-channel[0]-ctl read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sms dms sinc dinc src_tr_width dst_tr_width src_msize dst_msize nonposted_lastwrite_en arlen_en arlen awlen_en awlen src_stat_en dst_stat_en ioc_blktfr shadowreg_or_lli_last shadowreg_or_lli_valid

sms : Source master select
bits : 0 - 0 (1 bit)

Enumeration: MASTER_SELECT

0 : axi_master_1

AXI master 1

1 : axi_master_2

AXI master 2

End of enumeration elements list.

dms : Destination master select
bits : 2 - 4 (3 bit)

Enumeration:

End of enumeration elements list.

sinc : Source address increment
bits : 4 - 8 (5 bit)

Enumeration: INCREMENT

0 : increment

Increment address

1 : nochange

Don't increment address

End of enumeration elements list.

dinc : Destination address increment
bits : 6 - 12 (7 bit)

Enumeration:

End of enumeration elements list.

src_tr_width : Source transfer width
bits : 8 - 18 (11 bit)

Enumeration: TRANSFER_WIDTH

0 : width_8

8 bits

1 : width_16

16 bits

2 : width_32

32 bits

3 : width_64

64 bits

4 : width_128

128 bits

5 : width_256

256 bits

6 : width_512

512 bits

End of enumeration elements list.

dst_tr_width : Destination transfer width
bits : 11 - 24 (14 bit)

Enumeration:

End of enumeration elements list.

src_msize : Source burst transaction length
bits : 14 - 31 (18 bit)

Enumeration: BURST_LENGTH

0 : length_1

1 data item

1 : length_4

4 data items

2 : length_8

8 data items

3 : length_16

16 data items

4 : length_32

32 data items

5 : length_64

64 data items

6 : length_128

128 data items

7 : length_256

256 data items

8 : length_512

512 data items

9 : length_1024

1024 data items

End of enumeration elements list.

dst_msize : Destination burst transaction length
bits : 18 - 39 (22 bit)

Enumeration:

End of enumeration elements list.

nonposted_lastwrite_en : Non Posted Last Write Enable (posted writes may be used till the end of the block)
bits : 30 - 60 (31 bit)

arlen_en : Source burst length enable
bits : 38 - 76 (39 bit)

arlen : Source burst length
bits : 39 - 85 (47 bit)

awlen_en : Destination burst length enable
bits : 47 - 94 (48 bit)

awlen : Destination burst length
bits : 48 - 103 (56 bit)

src_stat_en : Source status enable
bits : 56 - 112 (57 bit)

dst_stat_en : Destination status enable
bits : 57 - 114 (58 bit)

ioc_blktfr : Interrupt completion of block transfer
bits : 58 - 116 (59 bit)

shadowreg_or_lli_last : Last shadow linked list item (indicates shadowreg/LLI content is the last one)
bits : 62 - 124 (63 bit)

shadowreg_or_lli_valid : last shadow linked list item valid (indicate shadowreg/LLI content is valid)
bits : 63 - 126 (64 bit)


channel[3]-channel[2]-channel[1]-channel[0]-cfg

Configure Register
address_offset : 0xA20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[3]-channel[2]-channel[1]-channel[0]-cfg channel[3]-channel[2]-channel[1]-channel[0]-cfg read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 src_multblk_type dst_multblk_type tt_fc hs_sel_src hs_sel_dst src_hwhs_pol dst_hwhs_pol src_per dst_per ch_prior lock_ch lock_ch_l src_osr_lmt dst_osr_lmt

src_multblk_type : Source multi-block transfer type
bits : 0 - 1 (2 bit)

Enumeration: MULTIBLK_TRANSFER_TYPE

0 : contiguous

Continuous multi-block type

1 : reload

Reload multi-block type

2 : shadow_register

Shadow register based multi-block type

3 : linked_list

Linked list based multi-block type

End of enumeration elements list.

dst_multblk_type : Destination multi-block transfer type
bits : 2 - 5 (4 bit)

Enumeration:

End of enumeration elements list.

tt_fc : Transfer type and flow control
bits : 32 - 66 (35 bit)

Enumeration:

0 : mem2mem_dma

Transfer memory to memory and flow controller is DMAC

1 : mem2prf_dma

Transfer memory to peripheral and flow controller is DMAC

2 : prf2mem_dma

Transfer peripheral to memory and flow controller is DMAC

3 : prf2prf_dma

Transfer peripheral to peripheral and flow controller is DMAC

4 : prf2mem_prf

Transfer peripheral to memory and flow controller is source peripheral

5 : prf2prf_srcprf

Transfer peripheral to peripheral and flow controller is source peripheral

6 : mem2prf_prf

Transfer memory to peripheral and flow controller is destination peripheral

7 : prf2prf_dstprf

Transfer peripheral to peripheral and flow controller is destination peripheral

End of enumeration elements list.

hs_sel_src : Source software or hardware handshaking select
bits : 35 - 70 (36 bit)

Enumeration: HANDSHAKING

0 : hardware

Hardware handshaking is used

1 : software

Software handshaking is used

End of enumeration elements list.

hs_sel_dst : Destination software or hardware handshaking select
bits : 36 - 72 (37 bit)

Enumeration:

End of enumeration elements list.

src_hwhs_pol : Source hardware handshaking interface polarity
bits : 37 - 74 (38 bit)

Enumeration: POLARITY

0 : active_high

Active high

1 : active_low

Active low

End of enumeration elements list.

dst_hwhs_pol : Destination hardware handshaking interface polarity
bits : 38 - 76 (39 bit)

Enumeration:

End of enumeration elements list.

src_per : Assign a hardware handshaking interface to source of channel
bits : 39 - 81 (43 bit)

dst_per : Assign a hardware handshaking interface to destination of channel
bits : 44 - 91 (48 bit)

ch_prior : Channel priority (7 is highest, 0 is lowest)
bits : 49 - 100 (52 bit)

lock_ch : Channel lock bit
bits : 52 - 104 (53 bit)

lock_ch_l : Channel lock level
bits : 53 - 107 (55 bit)

Enumeration:

0 : dma_transfer

Duration of channel is locked for entire DMA transfer

1 : block_transfer

Duration of channel is locked for current block transfer

2 : transaction

Duration of channel is locked for current transaction

End of enumeration elements list.

src_osr_lmt : Source outstanding request limit
bits : 55 - 113 (59 bit)

dst_osr_lmt : Destination outstanding request limit
bits : 59 - 121 (63 bit)


channel[3]-channel[2]-channel[1]-channel[0]-llp

Linked List Pointer register
address_offset : 0xA28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[3]-channel[2]-channel[1]-channel[0]-llp channel[3]-channel[2]-channel[1]-channel[0]-llp read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 lms loc

lms : LLI master select
bits : 0 - 0 (1 bit)

Enumeration:

End of enumeration elements list.

loc : Starting address memeory of LLI block
bits : 6 - 69 (64 bit)


channel[3]-channel[2]-channel[1]-channel[0]-status

Channel Status Register
address_offset : 0xA30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[3]-channel[2]-channel[1]-channel[0]-status channel[3]-channel[2]-channel[1]-channel[0]-status read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cmpltd_blk_size

cmpltd_blk_size : Completed block transfer size
bits : 0 - 21 (22 bit)


channel[3]-channel[2]-channel[1]-channel[0]-swhssrc

Channel Software handshake Source Register
address_offset : 0xA38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[3]-channel[2]-channel[1]-channel[0]-swhssrc channel[3]-channel[2]-channel[1]-channel[0]-swhssrc read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 req req_we sglreq sglreq_we lst lst_we

req : Software handshake request for channel source
bits : 0 - 0 (1 bit)

req_we : Write enable bit for software handshake request
bits : 1 - 2 (2 bit)

sglreq : Software handshake single request for channel source
bits : 2 - 4 (3 bit)

sglreq_we : Write enable bit for software handshake
bits : 3 - 6 (4 bit)

lst : Software handshake last request for channel source
bits : 4 - 8 (5 bit)

lst_we : Write enable bit for software handshake last request
bits : 5 - 10 (6 bit)


channel[3]-channel[2]-channel[1]-channel[0]-swhsdst

Channel Software handshake Destination Register
address_offset : 0xA40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[3]-channel[2]-channel[1]-channel[0]-swhsdst channel[3]-channel[2]-channel[1]-channel[0]-swhsdst read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 req req_we sglreq sglreq_we lst lst_we

req : Software handshake request for channel destination
bits : 0 - 0 (1 bit)

req_we : Write enable bit for software handshake request
bits : 1 - 2 (2 bit)

sglreq : Software handshake single request for channel destination
bits : 2 - 4 (3 bit)

sglreq_we : Write enable bit for software handshake
bits : 3 - 6 (4 bit)

lst : Software handshake last request for channel destination
bits : 4 - 8 (5 bit)

lst_we : Write enable bit for software handshake last request
bits : 5 - 10 (6 bit)


channel[3]-channel[2]-channel[1]-channel[0]-blk_tfr

Channel Block Transfer Resume Request Register
address_offset : 0xA48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[3]-channel[2]-channel[1]-channel[0]-blk_tfr channel[3]-channel[2]-channel[1]-channel[0]-blk_tfr read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 resumereq

resumereq : Block transfer resume request
bits : 0 - 0 (1 bit)


channel[3]-channel[2]-channel[1]-channel[0]-axi_id

Channel AXI ID Register
address_offset : 0xA50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[3]-channel[2]-channel[1]-channel[0]-axi_id channel[3]-channel[2]-channel[1]-channel[0]-axi_id read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

channel[3]-channel[2]-channel[1]-channel[0]-axi_qos

AXI QOS Register
address_offset : 0xA58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[3]-channel[2]-channel[1]-channel[0]-axi_qos channel[3]-channel[2]-channel[1]-channel[0]-axi_qos read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

channel[3]-channel[2]-channel[1]-channel[0]-intstatus_en

Interrupt Status Enable Register
address_offset : 0xA80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[3]-channel[2]-channel[1]-channel[0]-intstatus_en channel[3]-channel[2]-channel[1]-channel[0]-intstatus_en read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 block_tfr_done tfr_done src_transcomp dst_transcomp src_dec_err dst_dec_err src_slv_err dst_slv_err lli_rd_dec_err lli_wr_dec_err lli_rd_slv_err lli_wr_slv_err

block_tfr_done : Block transfer done
bits : 0 - 0 (1 bit)

tfr_done : Transfer done
bits : 1 - 2 (2 bit)

src_transcomp : Source transaction complete
bits : 3 - 6 (4 bit)

dst_transcomp : Destination transaction complete
bits : 4 - 8 (5 bit)

src_dec_err : Source Decode Error
bits : 5 - 10 (6 bit)

dst_dec_err : Destination Decode Error
bits : 6 - 12 (7 bit)

src_slv_err : Source Slave Error
bits : 7 - 14 (8 bit)

dst_slv_err : Destination Slave Error
bits : 8 - 16 (9 bit)

lli_rd_dec_err : LLI Read Decode Error Status Enable
bits : 9 - 18 (10 bit)

lli_wr_dec_err : LLI WRITE Decode Error
bits : 10 - 20 (11 bit)

lli_rd_slv_err : LLI Read Slave Error
bits : 11 - 22 (12 bit)

lli_wr_slv_err : LLI WRITE Slave Error
bits : 12 - 24 (13 bit)


channel[3]-channel[2]-channel[1]-channel[0]-intstatus

Channel Interrupt Status Register
address_offset : 0xA88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[3]-channel[2]-channel[1]-channel[0]-intstatus channel[3]-channel[2]-channel[1]-channel[0]-intstatus read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 block_tfr_done tfr_done src_transcomp dst_transcomp src_dec_err dst_dec_err src_slv_err dst_slv_err lli_rd_dec_err lli_wr_dec_err lli_rd_slv_err lli_wr_slv_err

block_tfr_done : Block transfer done
bits : 0 - 0 (1 bit)

tfr_done : Transfer done
bits : 1 - 2 (2 bit)

src_transcomp : Source transaction complete
bits : 3 - 6 (4 bit)

dst_transcomp : Destination transaction complete
bits : 4 - 8 (5 bit)

src_dec_err : Source Decode Error
bits : 5 - 10 (6 bit)

dst_dec_err : Destination Decode Error
bits : 6 - 12 (7 bit)

src_slv_err : Source Slave Error
bits : 7 - 14 (8 bit)

dst_slv_err : Destination Slave Error
bits : 8 - 16 (9 bit)

lli_rd_dec_err : LLI Read Decode Error Status Enable
bits : 9 - 18 (10 bit)

lli_wr_dec_err : LLI WRITE Decode Error
bits : 10 - 20 (11 bit)

lli_rd_slv_err : LLI Read Slave Error
bits : 11 - 22 (12 bit)

lli_wr_slv_err : LLI WRITE Slave Error
bits : 12 - 24 (13 bit)


channel[3]-channel[2]-channel[1]-channel[0]-intsignal_en

Interrupt Signal Enable Register
address_offset : 0xA90 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[3]-channel[2]-channel[1]-channel[0]-intsignal_en channel[3]-channel[2]-channel[1]-channel[0]-intsignal_en read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 block_tfr_done tfr_done src_transcomp dst_transcomp src_dec_err dst_dec_err src_slv_err dst_slv_err lli_rd_dec_err lli_wr_dec_err lli_rd_slv_err lli_wr_slv_err

block_tfr_done : Block transfer done
bits : 0 - 0 (1 bit)

tfr_done : Transfer done
bits : 1 - 2 (2 bit)

src_transcomp : Source transaction complete
bits : 3 - 6 (4 bit)

dst_transcomp : Destination transaction complete
bits : 4 - 8 (5 bit)

src_dec_err : Source Decode Error
bits : 5 - 10 (6 bit)

dst_dec_err : Destination Decode Error
bits : 6 - 12 (7 bit)

src_slv_err : Source Slave Error
bits : 7 - 14 (8 bit)

dst_slv_err : Destination Slave Error
bits : 8 - 16 (9 bit)

lli_rd_dec_err : LLI Read Decode Error Status Enable
bits : 9 - 18 (10 bit)

lli_wr_dec_err : LLI WRITE Decode Error
bits : 10 - 20 (11 bit)

lli_rd_slv_err : LLI Read Slave Error
bits : 11 - 22 (12 bit)

lli_wr_slv_err : LLI WRITE Slave Error
bits : 12 - 24 (13 bit)


channel[3]-channel[2]-channel[1]-channel[0]-intclear

Interrupt Clear Register
address_offset : 0xA98 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[3]-channel[2]-channel[1]-channel[0]-intclear channel[3]-channel[2]-channel[1]-channel[0]-intclear read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 block_tfr_done tfr_done src_transcomp dst_transcomp src_dec_err dst_dec_err src_slv_err dst_slv_err lli_rd_dec_err lli_wr_dec_err lli_rd_slv_err lli_wr_slv_err

block_tfr_done : Block transfer done
bits : 0 - 0 (1 bit)

tfr_done : Transfer done
bits : 1 - 2 (2 bit)

src_transcomp : Source transaction complete
bits : 3 - 6 (4 bit)

dst_transcomp : Destination transaction complete
bits : 4 - 8 (5 bit)

src_dec_err : Source Decode Error
bits : 5 - 10 (6 bit)

dst_dec_err : Destination Decode Error
bits : 6 - 12 (7 bit)

src_slv_err : Source Slave Error
bits : 7 - 14 (8 bit)

dst_slv_err : Destination Slave Error
bits : 8 - 16 (9 bit)

lli_rd_dec_err : LLI Read Decode Error Status Enable
bits : 9 - 18 (10 bit)

lli_wr_dec_err : LLI WRITE Decode Error
bits : 10 - 20 (11 bit)

lli_rd_slv_err : LLI Read Slave Error
bits : 11 - 22 (12 bit)

lli_wr_slv_err : LLI WRITE Slave Error
bits : 12 - 24 (13 bit)


channel[3]-channel[2]-channel[1]-channel[0]-_reserved

Padding to make structure size 256 bytes so that channels[] is an array
address_offset : 0xAF8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[3]-channel[2]-channel[1]-channel[0]-_reserved channel[3]-channel[2]-channel[1]-channel[0]-_reserved read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-sar

SAR Address Register
address_offset : 0xF00 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-sar channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-sar read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-dar

DAR Address Register
address_offset : 0xF08 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-dar channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-dar read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-block_ts

Block Transfer Size Register
address_offset : 0xF10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-block_ts channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-block_ts read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 block_ts

block_ts : Block transfer size
bits : 0 - 21 (22 bit)


channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-ctl

Control Register
address_offset : 0xF18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-ctl channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-ctl read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sms dms sinc dinc src_tr_width dst_tr_width src_msize dst_msize nonposted_lastwrite_en arlen_en arlen awlen_en awlen src_stat_en dst_stat_en ioc_blktfr shadowreg_or_lli_last shadowreg_or_lli_valid

sms : Source master select
bits : 0 - 0 (1 bit)

Enumeration: MASTER_SELECT

0 : axi_master_1

AXI master 1

1 : axi_master_2

AXI master 2

End of enumeration elements list.

dms : Destination master select
bits : 2 - 4 (3 bit)

Enumeration:

End of enumeration elements list.

sinc : Source address increment
bits : 4 - 8 (5 bit)

Enumeration: INCREMENT

0 : increment

Increment address

1 : nochange

Don't increment address

End of enumeration elements list.

dinc : Destination address increment
bits : 6 - 12 (7 bit)

Enumeration:

End of enumeration elements list.

src_tr_width : Source transfer width
bits : 8 - 18 (11 bit)

Enumeration: TRANSFER_WIDTH

0 : width_8

8 bits

1 : width_16

16 bits

2 : width_32

32 bits

3 : width_64

64 bits

4 : width_128

128 bits

5 : width_256

256 bits

6 : width_512

512 bits

End of enumeration elements list.

dst_tr_width : Destination transfer width
bits : 11 - 24 (14 bit)

Enumeration:

End of enumeration elements list.

src_msize : Source burst transaction length
bits : 14 - 31 (18 bit)

Enumeration: BURST_LENGTH

0 : length_1

1 data item

1 : length_4

4 data items

2 : length_8

8 data items

3 : length_16

16 data items

4 : length_32

32 data items

5 : length_64

64 data items

6 : length_128

128 data items

7 : length_256

256 data items

8 : length_512

512 data items

9 : length_1024

1024 data items

End of enumeration elements list.

dst_msize : Destination burst transaction length
bits : 18 - 39 (22 bit)

Enumeration:

End of enumeration elements list.

nonposted_lastwrite_en : Non Posted Last Write Enable (posted writes may be used till the end of the block)
bits : 30 - 60 (31 bit)

arlen_en : Source burst length enable
bits : 38 - 76 (39 bit)

arlen : Source burst length
bits : 39 - 85 (47 bit)

awlen_en : Destination burst length enable
bits : 47 - 94 (48 bit)

awlen : Destination burst length
bits : 48 - 103 (56 bit)

src_stat_en : Source status enable
bits : 56 - 112 (57 bit)

dst_stat_en : Destination status enable
bits : 57 - 114 (58 bit)

ioc_blktfr : Interrupt completion of block transfer
bits : 58 - 116 (59 bit)

shadowreg_or_lli_last : Last shadow linked list item (indicates shadowreg/LLI content is the last one)
bits : 62 - 124 (63 bit)

shadowreg_or_lli_valid : last shadow linked list item valid (indicate shadowreg/LLI content is valid)
bits : 63 - 126 (64 bit)


channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-cfg

Configure Register
address_offset : 0xF20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-cfg channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-cfg read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 src_multblk_type dst_multblk_type tt_fc hs_sel_src hs_sel_dst src_hwhs_pol dst_hwhs_pol src_per dst_per ch_prior lock_ch lock_ch_l src_osr_lmt dst_osr_lmt

src_multblk_type : Source multi-block transfer type
bits : 0 - 1 (2 bit)

Enumeration: MULTIBLK_TRANSFER_TYPE

0 : contiguous

Continuous multi-block type

1 : reload

Reload multi-block type

2 : shadow_register

Shadow register based multi-block type

3 : linked_list

Linked list based multi-block type

End of enumeration elements list.

dst_multblk_type : Destination multi-block transfer type
bits : 2 - 5 (4 bit)

Enumeration:

End of enumeration elements list.

tt_fc : Transfer type and flow control
bits : 32 - 66 (35 bit)

Enumeration:

0 : mem2mem_dma

Transfer memory to memory and flow controller is DMAC

1 : mem2prf_dma

Transfer memory to peripheral and flow controller is DMAC

2 : prf2mem_dma

Transfer peripheral to memory and flow controller is DMAC

3 : prf2prf_dma

Transfer peripheral to peripheral and flow controller is DMAC

4 : prf2mem_prf

Transfer peripheral to memory and flow controller is source peripheral

5 : prf2prf_srcprf

Transfer peripheral to peripheral and flow controller is source peripheral

6 : mem2prf_prf

Transfer memory to peripheral and flow controller is destination peripheral

7 : prf2prf_dstprf

Transfer peripheral to peripheral and flow controller is destination peripheral

End of enumeration elements list.

hs_sel_src : Source software or hardware handshaking select
bits : 35 - 70 (36 bit)

Enumeration: HANDSHAKING

0 : hardware

Hardware handshaking is used

1 : software

Software handshaking is used

End of enumeration elements list.

hs_sel_dst : Destination software or hardware handshaking select
bits : 36 - 72 (37 bit)

Enumeration:

End of enumeration elements list.

src_hwhs_pol : Source hardware handshaking interface polarity
bits : 37 - 74 (38 bit)

Enumeration: POLARITY

0 : active_high

Active high

1 : active_low

Active low

End of enumeration elements list.

dst_hwhs_pol : Destination hardware handshaking interface polarity
bits : 38 - 76 (39 bit)

Enumeration:

End of enumeration elements list.

src_per : Assign a hardware handshaking interface to source of channel
bits : 39 - 81 (43 bit)

dst_per : Assign a hardware handshaking interface to destination of channel
bits : 44 - 91 (48 bit)

ch_prior : Channel priority (7 is highest, 0 is lowest)
bits : 49 - 100 (52 bit)

lock_ch : Channel lock bit
bits : 52 - 104 (53 bit)

lock_ch_l : Channel lock level
bits : 53 - 107 (55 bit)

Enumeration:

0 : dma_transfer

Duration of channel is locked for entire DMA transfer

1 : block_transfer

Duration of channel is locked for current block transfer

2 : transaction

Duration of channel is locked for current transaction

End of enumeration elements list.

src_osr_lmt : Source outstanding request limit
bits : 55 - 113 (59 bit)

dst_osr_lmt : Destination outstanding request limit
bits : 59 - 121 (63 bit)


channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-llp

Linked List Pointer register
address_offset : 0xF28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-llp channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-llp read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 lms loc

lms : LLI master select
bits : 0 - 0 (1 bit)

Enumeration:

End of enumeration elements list.

loc : Starting address memeory of LLI block
bits : 6 - 69 (64 bit)


channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-status

Channel Status Register
address_offset : 0xF30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-status channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-status read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cmpltd_blk_size

cmpltd_blk_size : Completed block transfer size
bits : 0 - 21 (22 bit)


channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-swhssrc

Channel Software handshake Source Register
address_offset : 0xF38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-swhssrc channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-swhssrc read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 req req_we sglreq sglreq_we lst lst_we

req : Software handshake request for channel source
bits : 0 - 0 (1 bit)

req_we : Write enable bit for software handshake request
bits : 1 - 2 (2 bit)

sglreq : Software handshake single request for channel source
bits : 2 - 4 (3 bit)

sglreq_we : Write enable bit for software handshake
bits : 3 - 6 (4 bit)

lst : Software handshake last request for channel source
bits : 4 - 8 (5 bit)

lst_we : Write enable bit for software handshake last request
bits : 5 - 10 (6 bit)


channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-swhsdst

Channel Software handshake Destination Register
address_offset : 0xF40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-swhsdst channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-swhsdst read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 req req_we sglreq sglreq_we lst lst_we

req : Software handshake request for channel destination
bits : 0 - 0 (1 bit)

req_we : Write enable bit for software handshake request
bits : 1 - 2 (2 bit)

sglreq : Software handshake single request for channel destination
bits : 2 - 4 (3 bit)

sglreq_we : Write enable bit for software handshake
bits : 3 - 6 (4 bit)

lst : Software handshake last request for channel destination
bits : 4 - 8 (5 bit)

lst_we : Write enable bit for software handshake last request
bits : 5 - 10 (6 bit)


channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-blk_tfr

Channel Block Transfer Resume Request Register
address_offset : 0xF48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-blk_tfr channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-blk_tfr read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 resumereq

resumereq : Block transfer resume request
bits : 0 - 0 (1 bit)


channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-axi_id

Channel AXI ID Register
address_offset : 0xF50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-axi_id channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-axi_id read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-axi_qos

AXI QOS Register
address_offset : 0xF58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-axi_qos channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-axi_qos read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-intstatus_en

Interrupt Status Enable Register
address_offset : 0xF80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-intstatus_en channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-intstatus_en read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 block_tfr_done tfr_done src_transcomp dst_transcomp src_dec_err dst_dec_err src_slv_err dst_slv_err lli_rd_dec_err lli_wr_dec_err lli_rd_slv_err lli_wr_slv_err

block_tfr_done : Block transfer done
bits : 0 - 0 (1 bit)

tfr_done : Transfer done
bits : 1 - 2 (2 bit)

src_transcomp : Source transaction complete
bits : 3 - 6 (4 bit)

dst_transcomp : Destination transaction complete
bits : 4 - 8 (5 bit)

src_dec_err : Source Decode Error
bits : 5 - 10 (6 bit)

dst_dec_err : Destination Decode Error
bits : 6 - 12 (7 bit)

src_slv_err : Source Slave Error
bits : 7 - 14 (8 bit)

dst_slv_err : Destination Slave Error
bits : 8 - 16 (9 bit)

lli_rd_dec_err : LLI Read Decode Error Status Enable
bits : 9 - 18 (10 bit)

lli_wr_dec_err : LLI WRITE Decode Error
bits : 10 - 20 (11 bit)

lli_rd_slv_err : LLI Read Slave Error
bits : 11 - 22 (12 bit)

lli_wr_slv_err : LLI WRITE Slave Error
bits : 12 - 24 (13 bit)


channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-intstatus

Channel Interrupt Status Register
address_offset : 0xF88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-intstatus channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-intstatus read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 block_tfr_done tfr_done src_transcomp dst_transcomp src_dec_err dst_dec_err src_slv_err dst_slv_err lli_rd_dec_err lli_wr_dec_err lli_rd_slv_err lli_wr_slv_err

block_tfr_done : Block transfer done
bits : 0 - 0 (1 bit)

tfr_done : Transfer done
bits : 1 - 2 (2 bit)

src_transcomp : Source transaction complete
bits : 3 - 6 (4 bit)

dst_transcomp : Destination transaction complete
bits : 4 - 8 (5 bit)

src_dec_err : Source Decode Error
bits : 5 - 10 (6 bit)

dst_dec_err : Destination Decode Error
bits : 6 - 12 (7 bit)

src_slv_err : Source Slave Error
bits : 7 - 14 (8 bit)

dst_slv_err : Destination Slave Error
bits : 8 - 16 (9 bit)

lli_rd_dec_err : LLI Read Decode Error Status Enable
bits : 9 - 18 (10 bit)

lli_wr_dec_err : LLI WRITE Decode Error
bits : 10 - 20 (11 bit)

lli_rd_slv_err : LLI Read Slave Error
bits : 11 - 22 (12 bit)

lli_wr_slv_err : LLI WRITE Slave Error
bits : 12 - 24 (13 bit)


channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-intsignal_en

Interrupt Signal Enable Register
address_offset : 0xF90 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-intsignal_en channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-intsignal_en read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 block_tfr_done tfr_done src_transcomp dst_transcomp src_dec_err dst_dec_err src_slv_err dst_slv_err lli_rd_dec_err lli_wr_dec_err lli_rd_slv_err lli_wr_slv_err

block_tfr_done : Block transfer done
bits : 0 - 0 (1 bit)

tfr_done : Transfer done
bits : 1 - 2 (2 bit)

src_transcomp : Source transaction complete
bits : 3 - 6 (4 bit)

dst_transcomp : Destination transaction complete
bits : 4 - 8 (5 bit)

src_dec_err : Source Decode Error
bits : 5 - 10 (6 bit)

dst_dec_err : Destination Decode Error
bits : 6 - 12 (7 bit)

src_slv_err : Source Slave Error
bits : 7 - 14 (8 bit)

dst_slv_err : Destination Slave Error
bits : 8 - 16 (9 bit)

lli_rd_dec_err : LLI Read Decode Error Status Enable
bits : 9 - 18 (10 bit)

lli_wr_dec_err : LLI WRITE Decode Error
bits : 10 - 20 (11 bit)

lli_rd_slv_err : LLI Read Slave Error
bits : 11 - 22 (12 bit)

lli_wr_slv_err : LLI WRITE Slave Error
bits : 12 - 24 (13 bit)


channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-intclear

Interrupt Clear Register
address_offset : 0xF98 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-intclear channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-intclear read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 block_tfr_done tfr_done src_transcomp dst_transcomp src_dec_err dst_dec_err src_slv_err dst_slv_err lli_rd_dec_err lli_wr_dec_err lli_rd_slv_err lli_wr_slv_err

block_tfr_done : Block transfer done
bits : 0 - 0 (1 bit)

tfr_done : Transfer done
bits : 1 - 2 (2 bit)

src_transcomp : Source transaction complete
bits : 3 - 6 (4 bit)

dst_transcomp : Destination transaction complete
bits : 4 - 8 (5 bit)

src_dec_err : Source Decode Error
bits : 5 - 10 (6 bit)

dst_dec_err : Destination Decode Error
bits : 6 - 12 (7 bit)

src_slv_err : Source Slave Error
bits : 7 - 14 (8 bit)

dst_slv_err : Destination Slave Error
bits : 8 - 16 (9 bit)

lli_rd_dec_err : LLI Read Decode Error Status Enable
bits : 9 - 18 (10 bit)

lli_wr_dec_err : LLI WRITE Decode Error
bits : 10 - 20 (11 bit)

lli_rd_slv_err : LLI Read Slave Error
bits : 11 - 22 (12 bit)

lli_wr_slv_err : LLI WRITE Slave Error
bits : 12 - 24 (13 bit)


channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-_reserved

Padding to make structure size 256 bytes so that channels[] is an array
address_offset : 0xFF8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-_reserved channel[4]-channel[3]-channel[2]-channel[1]-channel[0]-_reserved read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


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