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Receive Buffer Register / Divisor Latch (Low) / Transmit Holding Register (depending on context and R/W)
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Modem Control Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Shadow Receive Buffer Register / Shadow Transmit Holding Register (depending on R/W)
address_offset : 0x108 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Line Status Register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Shadow Receive Buffer Register / Shadow Transmit Holding Register (depending on R/W)
address_offset : 0x148 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Modem Status Register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Shadow Receive Buffer Register / Shadow Transmit Holding Register (depending on R/W)
address_offset : 0x18C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Scratchpad Register
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Shadow Receive Buffer Register / Shadow Transmit Holding Register (depending on R/W)
address_offset : 0x1D4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Low Power Divisor Latch (Low) Register
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Shadow Receive Buffer Register / Shadow Transmit Holding Register (depending on R/W)
address_offset : 0x220 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Low Power Divisor Latch (High) Register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Shadow Receive Buffer Register / Shadow Transmit Holding Register (depending on R/W)
address_offset : 0x270 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Shadow Receive Buffer Register / Shadow Transmit Holding Register (depending on R/W)
address_offset : 0x2C4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Shadow Receive Buffer Register / Shadow Transmit Holding Register (depending on R/W)
address_offset : 0x31C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Shadow Receive Buffer Register / Shadow Transmit Holding Register (depending on R/W)
address_offset : 0x378 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Shadow Receive Buffer Register / Shadow Transmit Holding Register (depending on R/W)
address_offset : 0x3D8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Divisor Latch (High) / Interrupt Enable Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Shadow Receive Buffer Register / Shadow Transmit Holding Register (depending on R/W)
address_offset : 0x43C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Shadow Receive Buffer Register / Shadow Transmit Holding Register (depending on R/W)
address_offset : 0x4A4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Shadow Receive Buffer Register / Shadow Transmit Holding Register (depending on R/W)
address_offset : 0x510 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Shadow Receive Buffer Register / Shadow Transmit Holding Register (depending on R/W)
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FIFO Access Register
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Transmit FIFO Read Register
address_offset : 0x74 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Receive FIFO Write Register
address_offset : 0x78 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UART Status Register
address_offset : 0x7C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FIFO Control Register / Interrupt Identification Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Transmit FIFO Level
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Receive FIFO Level
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Software Reset Register
address_offset : 0x88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Shadow Request to Send Register
address_offset : 0x8C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Shadow Break Control Register
address_offset : 0x90 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Shadow Receive Buffer Register / Shadow Transmit Holding Register (depending on R/W)
address_offset : 0x94 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Shadow DMA Mode
address_offset : 0x94 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Shadow FIFO Enable
address_offset : 0x98 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Shadow RCVR Trigger Register
address_offset : 0x9C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Shadow TX Empty Trigger Register
address_offset : 0xA0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Halt TX Regster
address_offset : 0xA4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA Software Acknowledge Register
address_offset : 0xA8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Transfer Control Register
address_offset : 0xAC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DE Enable Register
address_offset : 0xB0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RE Enable Register
address_offset : 0xB4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DE Assertion Time Register
address_offset : 0xB8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Turn-Around Time Register
address_offset : 0xBC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Line Control Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Divisor Latch (Fractional) Register
address_offset : 0xC0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Receive-Mode Address Register
address_offset : 0xC4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Transmit-Mode Address Register
address_offset : 0xC8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Shadow Receive Buffer Register / Shadow Transmit Holding Register (depending on R/W)
address_offset : 0xCC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Line Control Register (Extended)
address_offset : 0xCC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Component Parameter Register
address_offset : 0xF4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UART Component Version
address_offset : 0xF8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Component Type Register
address_offset : 0xFC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
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