Registers
ctrlr0
Control Register 0
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data_length : DATA_BIT_LENGTH
bits : 0 - 4 (5 bit)
work_mode : WORK_MODE
bits : 8 - 17 (10 bit)
Enumeration:
0 : mode0
MODE_0
1 : mode1
MODE_1
2 : mode2
MODE_2
3 : mode3
MODE_3
End of enumeration elements list.
tmod : TRANSFER_MODE
bits : 10 - 21 (12 bit)
Enumeration:
0 : trans_recv
TRANS_RECV
1 : trans
TRANS
2 : recv
RECV
3 : eerom
EEROM
End of enumeration elements list.
frame_format : FRAME_FORMAT
bits : 22 - 45 (24 bit)
Enumeration:
0 : standard
STANDARD
1 : dual
DUAL
2 : quad
QUAD
3 : octal
OCTAL
End of enumeration elements list.
ser
Slave Enable Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
xip_incr_inst
XIP INCR transfer opcode
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
xip_wrap_inst
XIP WRAP transfer opcode
address_offset : 0x104 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
xip_ctrl
XIP Control Register
address_offset : 0x108 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
xip_ser
XIP Slave Enable Register
address_offset : 0x10C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
dr27
Data Register
address_offset : 0x10C8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
xrxoicr
XIP Receive FIFO Overflow Interrupt Clear Register
address_offset : 0x110 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
xip_cnt_time_out
XIP time out register for continuous transfers
address_offset : 0x114 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
endian
ENDIAN
address_offset : 0x118 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
dr28
Data Register
address_offset : 0x1198 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
dr1
Data Register
address_offset : 0x124 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
dr29
Data Register
address_offset : 0x126C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
dr30
Data Register
address_offset : 0x1344 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
baudr
Baud Rate Select
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
dr31
Data Register
address_offset : 0x1420 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
dr32
Data Register
address_offset : 0x1500 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
dr33
Data Register
address_offset : 0x15E4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
dr34
Data Register
address_offset : 0x16CC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
dr35
Data Register
address_offset : 0x17B8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
txftlr
Transmit FIFO Threshold Level
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
dr2
Data Register
address_offset : 0x18C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
rxftlr
Receive FIFO Threshold Level
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
dr3
Data Register
address_offset : 0x1F8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
txflr
Transmit FIFO Level Register
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
rxflr
Receive FIFO Level Register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
dr4
Data Register
address_offset : 0x268 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
sr
Status Register
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
imr
Interrupt Mask Register
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
dr5
Data Register
address_offset : 0x2DC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
isr
Interrupt Status Register
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
risr
Raw Interrupt Status Register
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
dr6
Data Register
address_offset : 0x354 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
txoicr
Transmit FIFO Overflow Interrupt Clear Register
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
rxoicr
Receive FIFO Overflow Interrupt Clear Register
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
dr7
Data Register
address_offset : 0x3D0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ctrlr1
Control Register 1
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
rxuicr
Receive FIFO Underflow Interrupt Clear Register
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
msticr
Multi-Master Interrupt Clear Register
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
dr8
Data Register
address_offset : 0x450 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
icr
Interrupt Clear Register
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
dmacr
DMA Control Register
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
dr9
Data Register
address_offset : 0x4D4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
dmatdlr
DMA Transmit Data Level
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
dmardlr
DMA Receive Data Level
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
dr10
Data Register
address_offset : 0x55C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
idr
Identification Register
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ssic_version_id
DWC_ssi component version
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
dr11
Data Register
address_offset : 0x5E8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
dr12
Data Register
address_offset : 0x678 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
dr13
Data Register
address_offset : 0x70C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
dr14
Data Register
address_offset : 0x7A4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ssienr
Enable Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
dr15
Data Register
address_offset : 0x840 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
dr16
Data Register
address_offset : 0x8E0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
dr17
Data Register
address_offset : 0x984 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
dr18
Data Register
address_offset : 0xA2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
dr19
Data Register
address_offset : 0xAD8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
dr20
Data Register
address_offset : 0xB88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
mwcr
Microwire Control Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
dr0
Data Register
address_offset : 0xC0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
dr21
Data Register
address_offset : 0xC3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
dr22
Data Register
address_offset : 0xCF4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
dr23
Data Register
address_offset : 0xDB0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
dr24
Data Register
address_offset : 0xE70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
rx_sample_delay
RX Sample Delay Register
address_offset : 0xF0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
dr25
Data Register
address_offset : 0xF34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
spi_ctrlr0
SPI Control Register
address_offset : 0xF4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
aitm : instruction_address_trans_mode
bits : 0 - 1 (2 bit)
Enumeration:
0 : standard
STANDARD
1 : addr_standard
ADDR_STANDARD
2 : as_frame_format
AS_FRAME_FORMAT
End of enumeration elements list.
addr_length : ADDR_LENGTH
bits : 2 - 7 (6 bit)
inst_length : INSTRUCTION_LENGTH
bits : 8 - 17 (10 bit)
wait_cycles : WAIT_CYCLES
bits : 11 - 26 (16 bit)
xip_mode_bits
XIP Mode bits
address_offset : 0xFC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
dr26
Data Register
address_offset : 0xFFC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
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