\n
channel2-channel1-channel0-left_rxtx
channel2-channel1-channel0-right_rxtx
channel2-channel1-channel0-rer
channel2-channel1-channel0-ter
channel2-channel1-channel0-rcr
channel2-channel1-channel0-tcr
channel2-channel1-channel0-isr
channel2-channel1-channel0-imr
channel2-channel1-channel0-ror
channel2-channel1-channel0-tor
channel2-channel1-channel0-rfcr
channel2-channel1-channel0-tfcr
channel2-channel1-channel0-rff
channel2-channel1-channel0-tff
channel3-channel2-channel1-channel0-left_rxtx
channel3-channel2-channel1-channel0-right_rxtx
channel3-channel2-channel1-channel0-rer
channel2-channel1-channel0-_reserved1
channel3-channel2-channel1-channel0-ter
channel3-channel2-channel1-channel0-rcr
channel3-channel2-channel1-channel0-tcr
channel3-channel2-channel1-channel0-isr
channel3-channel2-channel1-channel0-imr
channel3-channel2-channel1-channel0-ror
channel3-channel2-channel1-channel0-tor
channel3-channel2-channel1-channel0-rfcr
channel3-channel2-channel1-channel0-tfcr
channel3-channel2-channel1-channel0-rff
channel3-channel2-channel1-channel0-tff
channel3-channel2-channel1-channel0-_reserved1
Enable Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ien : I2S Enable
bits : 0 - 0 (1 bit)
Clock Configuration Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
clk_gate : Gating of sclk
bits : 0 - 2 (3 bit)
Enumeration:
0 : no
Clock gating is disabled
1 : cycles12
Gating after 12 sclk cycles
2 : cycles16
Gating after 16 sclk cycles
3 : cycles20
Gating after 20 sclk cycles
4 : cycles24
Gating after 24 sclk cycles
End of enumeration elements list.
clk_word_size : The number of sclk cycles for which the word select line stayd in the left aligned or right aligned mode
bits : 3 - 7 (5 bit)
Enumeration:
0 : cycles16
16 sclk cycles
1 : cycles24
24 sclk cycles
2 : cycles32
32 sclk cycles
End of enumeration elements list.
align_mode : Alignment mode setting
bits : 5 - 12 (8 bit)
Enumeration:
1 : standard
Standard I2S format
2 : right
Right aligned format
4 : left
Left aligned format
End of enumeration elements list.
dma_tx_en : DMA transmit enable control
bits : 8 - 16 (9 bit)
dma_rx_en : DMA receive enable control
bits : 9 - 18 (10 bit)
dma_divide_16 : Split 32bit data to two 16 bit data and filled in left and right channel. Used with dma_tx_en or dma_rx_en
bits : 10 - 20 (11 bit)
sign_expand_en : SIGN_EXPAND_EN
bits : 11 - 22 (12 bit)
_RESERVED0
address_offset : 0x10C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Left Receive or Left Transmit Register
address_offset : 0x120 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Right Receive or Right Transmit Register
address_offset : 0x124 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Receive Enable Register
address_offset : 0x128 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
rxchenx : Receive channel enable/disable
bits : 0 - 0 (1 bit)
Transmit Enable Register
address_offset : 0x12C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
txchenx : Transmit channel enable/disable
bits : 0 - 0 (1 bit)
Receive Configuration Register
address_offset : 0x130 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
wlen : Desired data resolution of receiver
bits : 0 - 2 (3 bit)
Enumeration: WLEN
0 : ignore
Ignore the word length
1 : resolution12
12-bit data resolution of the receiver
2 : resolution16
16-bit data resolution of the receiver
3 : resolution20
20-bit data resolution of the receiver
4 : resolution24
24-bit data resolution of the receiver
5 : resolution32
32-bit data resolution of the receiver
End of enumeration elements list.
Transmit Configuration Register
address_offset : 0x134 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
wlen : Desired data resolution of transmitter
bits : 0 - 2 (3 bit)
Enumeration:
End of enumeration elements list.
Interrupt Status Register
address_offset : 0x138 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
rxda : Status of receiver data avaliable interrupt
bits : 0 - 0 (1 bit)
rxfo : Status of data overrun interrupt for RX channel
bits : 1 - 2 (2 bit)
txfe : Status of transmit empty triger interrupt
bits : 4 - 8 (5 bit)
txfo : Status of data overrun interrupt for the TX channel
bits : 5 - 10 (6 bit)
Interrupt Mask Register
address_offset : 0x13C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
rxdam : Mask RX FIFO data avaliable interrupt
bits : 0 - 0 (1 bit)
rxfom : Mask RX FIFO overrun interrupt
bits : 1 - 2 (2 bit)
txfem : Mask TX FIFO empty interrupt
bits : 4 - 8 (5 bit)
txfom : Mask TX FIFO overrun interrupt
bits : 5 - 10 (6 bit)
Receiver Block FIFO Reset Register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
rxffr : Receiver FIFO reset
bits : 0 - 0 (1 bit)
Enumeration: FLUSH
0 : not_flush
Not flush FIFO
1 : flush
Flush FIFO
End of enumeration elements list.
Receive Overrun Register
address_offset : 0x140 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
rxcho : Read this bit to clear RX FIFO data overrun interrupt. 0x0 for RX FIFO write valid, 0x1 for RX FIFO write overrun
bits : 0 - 0 (1 bit)
Transmit Overrun Register
address_offset : 0x144 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
txcho : Read this bit to clear TX FIFO data overrun interrupt. 0x0 for TX FIFO write valid, 0x1 for TX FIFO write overrun
bits : 0 - 0 (1 bit)
Receive FIFO Configuration Register
address_offset : 0x148 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
rxchdt : Trigger level in the RX FIFO at which the receiver data available interrupt generate
bits : 0 - 3 (4 bit)
Enumeration: LEVEL
0 : level1
Interrupt trigger when FIFO level is 1
1 : level2
Interrupt trigger when FIFO level is 2
2 : level3
Interrupt trigger when FIFO level is 3
3 : level4
Interrupt trigger when FIFO level is 4
4 : level5
Interrupt trigger when FIFO level is 5
5 : level6
Interrupt trigger when FIFO level is 6
6 : level7
Interrupt trigger when FIFO level is 7
7 : level8
Interrupt trigger when FIFO level is 8
8 : level9
Interrupt trigger when FIFO level is 9
9 : level10
Interrupt trigger when FIFO level is 10
10 : level11
Interrupt trigger when FIFO level is 11
11 : level12
Interrupt trigger when FIFO level is 12
12 : level13
Interrupt trigger when FIFO level is 13
13 : level14
Interrupt trigger when FIFO level is 14
14 : level15
Interrupt trigger when FIFO level is 15
15 : level16
Interrupt trigger when FIFO level is 16
End of enumeration elements list.
Transmit FIFO Configuration Register
address_offset : 0x14C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
txchet : Trigger level in the TX FIFO at which the transmitter data available interrupt generate
bits : 0 - 3 (4 bit)
Enumeration:
End of enumeration elements list.
Receive FIFO Flush Register
address_offset : 0x150 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
rxchfr : Receiver channel FIFO reset
bits : 0 - 0 (1 bit)
Enumeration: FLUSH
0 : not_flush
Not flush an individual FIFO
1 : flush
Flush an indiviadual FIFO
End of enumeration elements list.
Transmit FIFO Flush Register
address_offset : 0x154 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
rtxchfr : Transmit channel FIFO reset
bits : 0 - 0 (1 bit)
Enumeration:
End of enumeration elements list.
_RESERVED0
address_offset : 0x16C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Transmitter Block FIFO Reset Register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
rxffr : Transmitter FIFO reset
bits : 0 - 0 (1 bit)
Enumeration:
End of enumeration elements list.
Receiver Block DMA Register
address_offset : 0x1C0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Reset Receiver Block DMA Register
address_offset : 0x1C4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Transmitter Block DMA Register
address_offset : 0x1C8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Reset Transmitter Block DMA Register
address_offset : 0x1CC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Component Parameter Register 2
address_offset : 0x1F0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Component Parameter Register 1
address_offset : 0x1F4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Component Version Register
address_offset : 0x1F8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Component Type Register
address_offset : 0x1FC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Left Receive or Left Transmit Register
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Left Receive or Left Transmit Register
address_offset : 0x200 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Right Receive or Right Transmit Register
address_offset : 0x204 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Receive Enable Register
address_offset : 0x208 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
rxchenx : Receive channel enable/disable
bits : 0 - 0 (1 bit)
_RESERVED0
address_offset : 0x20C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Transmit Enable Register
address_offset : 0x20C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
txchenx : Transmit channel enable/disable
bits : 0 - 0 (1 bit)
Receive Configuration Register
address_offset : 0x210 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
wlen : Desired data resolution of receiver
bits : 0 - 2 (3 bit)
Enumeration: WLEN
0 : ignore
Ignore the word length
1 : resolution12
12-bit data resolution of the receiver
2 : resolution16
16-bit data resolution of the receiver
3 : resolution20
20-bit data resolution of the receiver
4 : resolution24
24-bit data resolution of the receiver
5 : resolution32
32-bit data resolution of the receiver
End of enumeration elements list.
Transmit Configuration Register
address_offset : 0x214 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
wlen : Desired data resolution of transmitter
bits : 0 - 2 (3 bit)
Enumeration:
End of enumeration elements list.
Interrupt Status Register
address_offset : 0x218 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
rxda : Status of receiver data avaliable interrupt
bits : 0 - 0 (1 bit)
rxfo : Status of data overrun interrupt for RX channel
bits : 1 - 2 (2 bit)
txfe : Status of transmit empty triger interrupt
bits : 4 - 8 (5 bit)
txfo : Status of data overrun interrupt for the TX channel
bits : 5 - 10 (6 bit)
Interrupt Mask Register
address_offset : 0x21C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
rxdam : Mask RX FIFO data avaliable interrupt
bits : 0 - 0 (1 bit)
rxfom : Mask RX FIFO overrun interrupt
bits : 1 - 2 (2 bit)
txfem : Mask TX FIFO empty interrupt
bits : 4 - 8 (5 bit)
txfom : Mask TX FIFO overrun interrupt
bits : 5 - 10 (6 bit)
Receive Overrun Register
address_offset : 0x220 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
rxcho : Read this bit to clear RX FIFO data overrun interrupt. 0x0 for RX FIFO write valid, 0x1 for RX FIFO write overrun
bits : 0 - 0 (1 bit)
Transmit Overrun Register
address_offset : 0x224 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
txcho : Read this bit to clear TX FIFO data overrun interrupt. 0x0 for TX FIFO write valid, 0x1 for TX FIFO write overrun
bits : 0 - 0 (1 bit)
Receive FIFO Configuration Register
address_offset : 0x228 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
rxchdt : Trigger level in the RX FIFO at which the receiver data available interrupt generate
bits : 0 - 3 (4 bit)
Enumeration: LEVEL
0 : level1
Interrupt trigger when FIFO level is 1
1 : level2
Interrupt trigger when FIFO level is 2
2 : level3
Interrupt trigger when FIFO level is 3
3 : level4
Interrupt trigger when FIFO level is 4
4 : level5
Interrupt trigger when FIFO level is 5
5 : level6
Interrupt trigger when FIFO level is 6
6 : level7
Interrupt trigger when FIFO level is 7
7 : level8
Interrupt trigger when FIFO level is 8
8 : level9
Interrupt trigger when FIFO level is 9
9 : level10
Interrupt trigger when FIFO level is 10
10 : level11
Interrupt trigger when FIFO level is 11
11 : level12
Interrupt trigger when FIFO level is 12
12 : level13
Interrupt trigger when FIFO level is 13
13 : level14
Interrupt trigger when FIFO level is 14
14 : level15
Interrupt trigger when FIFO level is 15
15 : level16
Interrupt trigger when FIFO level is 16
End of enumeration elements list.
Transmit FIFO Configuration Register
address_offset : 0x22C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
txchet : Trigger level in the TX FIFO at which the transmitter data available interrupt generate
bits : 0 - 3 (4 bit)
Enumeration:
End of enumeration elements list.
Receive FIFO Flush Register
address_offset : 0x230 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
rxchfr : Receiver channel FIFO reset
bits : 0 - 0 (1 bit)
Enumeration: FLUSH
0 : not_flush
Not flush an individual FIFO
1 : flush
Flush an indiviadual FIFO
End of enumeration elements list.
Transmit FIFO Flush Register
address_offset : 0x234 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
rtxchfr : Transmit channel FIFO reset
bits : 0 - 0 (1 bit)
Enumeration:
End of enumeration elements list.
Right Receive or Right Transmit Register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Receive Enable Register
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
rxchenx : Receive channel enable/disable
bits : 0 - 0 (1 bit)
Transmit Enable Register
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
txchenx : Transmit channel enable/disable
bits : 0 - 0 (1 bit)
_RESERVED0
address_offset : 0x2EC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Receive Configuration Register
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
wlen : Desired data resolution of receiver
bits : 0 - 2 (3 bit)
Enumeration: WLEN
0 : ignore
Ignore the word length
1 : resolution12
12-bit data resolution of the receiver
2 : resolution16
16-bit data resolution of the receiver
3 : resolution20
20-bit data resolution of the receiver
4 : resolution24
24-bit data resolution of the receiver
5 : resolution32
32-bit data resolution of the receiver
End of enumeration elements list.
Transmit Configuration Register
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
wlen : Desired data resolution of transmitter
bits : 0 - 2 (3 bit)
Enumeration:
End of enumeration elements list.
Interrupt Status Register
address_offset : 0x38 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
rxda : Status of receiver data avaliable interrupt
bits : 0 - 0 (1 bit)
rxfo : Status of data overrun interrupt for RX channel
bits : 1 - 2 (2 bit)
txfe : Status of transmit empty triger interrupt
bits : 4 - 8 (5 bit)
txfo : Status of data overrun interrupt for the TX channel
bits : 5 - 10 (6 bit)
Interrupt Mask Register
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
rxdam : Mask RX FIFO data avaliable interrupt
bits : 0 - 0 (1 bit)
rxfom : Mask RX FIFO overrun interrupt
bits : 1 - 2 (2 bit)
txfem : Mask TX FIFO empty interrupt
bits : 4 - 8 (5 bit)
txfom : Mask TX FIFO overrun interrupt
bits : 5 - 10 (6 bit)
Receiver Block Enable Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
rxen : Receiver block enable
bits : 0 - 0 (1 bit)
Receive Overrun Register
address_offset : 0x40 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
rxcho : Read this bit to clear RX FIFO data overrun interrupt. 0x0 for RX FIFO write valid, 0x1 for RX FIFO write overrun
bits : 0 - 0 (1 bit)
Transmit Overrun Register
address_offset : 0x44 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
txcho : Read this bit to clear TX FIFO data overrun interrupt. 0x0 for TX FIFO write valid, 0x1 for TX FIFO write overrun
bits : 0 - 0 (1 bit)
Receive FIFO Configuration Register
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
rxchdt : Trigger level in the RX FIFO at which the receiver data available interrupt generate
bits : 0 - 3 (4 bit)
Enumeration: LEVEL
0 : level1
Interrupt trigger when FIFO level is 1
1 : level2
Interrupt trigger when FIFO level is 2
2 : level3
Interrupt trigger when FIFO level is 3
3 : level4
Interrupt trigger when FIFO level is 4
4 : level5
Interrupt trigger when FIFO level is 5
5 : level6
Interrupt trigger when FIFO level is 6
6 : level7
Interrupt trigger when FIFO level is 7
7 : level8
Interrupt trigger when FIFO level is 8
8 : level9
Interrupt trigger when FIFO level is 9
9 : level10
Interrupt trigger when FIFO level is 10
10 : level11
Interrupt trigger when FIFO level is 11
11 : level12
Interrupt trigger when FIFO level is 12
12 : level13
Interrupt trigger when FIFO level is 13
13 : level14
Interrupt trigger when FIFO level is 14
14 : level15
Interrupt trigger when FIFO level is 15
15 : level16
Interrupt trigger when FIFO level is 16
End of enumeration elements list.
Transmit FIFO Configuration Register
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
txchet : Trigger level in the TX FIFO at which the transmitter data available interrupt generate
bits : 0 - 3 (4 bit)
Enumeration:
End of enumeration elements list.
Receive FIFO Flush Register
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
rxchfr : Receiver channel FIFO reset
bits : 0 - 0 (1 bit)
Enumeration: FLUSH
0 : not_flush
Not flush an individual FIFO
1 : flush
Flush an indiviadual FIFO
End of enumeration elements list.
Transmit FIFO Flush Register
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
rtxchfr : Transmit channel FIFO reset
bits : 0 - 0 (1 bit)
Enumeration:
End of enumeration elements list.
Transmitter Block Enable Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
txen : Transmitter block enable
bits : 0 - 0 (1 bit)
Left Receive or Left Transmit Register
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Right Receive or Right Transmit Register
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Receive Enable Register
address_offset : 0x88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
rxchenx : Receive channel enable/disable
bits : 0 - 0 (1 bit)
Transmit Enable Register
address_offset : 0x8C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
txchenx : Transmit channel enable/disable
bits : 0 - 0 (1 bit)
Receive Configuration Register
address_offset : 0x90 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
wlen : Desired data resolution of receiver
bits : 0 - 2 (3 bit)
Enumeration: WLEN
0 : ignore
Ignore the word length
1 : resolution12
12-bit data resolution of the receiver
2 : resolution16
16-bit data resolution of the receiver
3 : resolution20
20-bit data resolution of the receiver
4 : resolution24
24-bit data resolution of the receiver
5 : resolution32
32-bit data resolution of the receiver
End of enumeration elements list.
Transmit Configuration Register
address_offset : 0x94 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
wlen : Desired data resolution of transmitter
bits : 0 - 2 (3 bit)
Enumeration:
End of enumeration elements list.
Interrupt Status Register
address_offset : 0x98 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
rxda : Status of receiver data avaliable interrupt
bits : 0 - 0 (1 bit)
rxfo : Status of data overrun interrupt for RX channel
bits : 1 - 2 (2 bit)
txfe : Status of transmit empty triger interrupt
bits : 4 - 8 (5 bit)
txfo : Status of data overrun interrupt for the TX channel
bits : 5 - 10 (6 bit)
Interrupt Mask Register
address_offset : 0x9C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
rxdam : Mask RX FIFO data avaliable interrupt
bits : 0 - 0 (1 bit)
rxfom : Mask RX FIFO overrun interrupt
bits : 1 - 2 (2 bit)
txfem : Mask TX FIFO empty interrupt
bits : 4 - 8 (5 bit)
txfom : Mask TX FIFO overrun interrupt
bits : 5 - 10 (6 bit)
Receive Overrun Register
address_offset : 0xA0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
rxcho : Read this bit to clear RX FIFO data overrun interrupt. 0x0 for RX FIFO write valid, 0x1 for RX FIFO write overrun
bits : 0 - 0 (1 bit)
Transmit Overrun Register
address_offset : 0xA4 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
txcho : Read this bit to clear TX FIFO data overrun interrupt. 0x0 for TX FIFO write valid, 0x1 for TX FIFO write overrun
bits : 0 - 0 (1 bit)
Receive FIFO Configuration Register
address_offset : 0xA8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
rxchdt : Trigger level in the RX FIFO at which the receiver data available interrupt generate
bits : 0 - 3 (4 bit)
Enumeration: LEVEL
0 : level1
Interrupt trigger when FIFO level is 1
1 : level2
Interrupt trigger when FIFO level is 2
2 : level3
Interrupt trigger when FIFO level is 3
3 : level4
Interrupt trigger when FIFO level is 4
4 : level5
Interrupt trigger when FIFO level is 5
5 : level6
Interrupt trigger when FIFO level is 6
6 : level7
Interrupt trigger when FIFO level is 7
7 : level8
Interrupt trigger when FIFO level is 8
8 : level9
Interrupt trigger when FIFO level is 9
9 : level10
Interrupt trigger when FIFO level is 10
10 : level11
Interrupt trigger when FIFO level is 11
11 : level12
Interrupt trigger when FIFO level is 12
12 : level13
Interrupt trigger when FIFO level is 13
13 : level14
Interrupt trigger when FIFO level is 14
14 : level15
Interrupt trigger when FIFO level is 15
15 : level16
Interrupt trigger when FIFO level is 16
End of enumeration elements list.
Transmit FIFO Configuration Register
address_offset : 0xAC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
txchet : Trigger level in the TX FIFO at which the transmitter data available interrupt generate
bits : 0 - 3 (4 bit)
Enumeration:
End of enumeration elements list.
_RESERVED0
address_offset : 0xB0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Receive FIFO Flush Register
address_offset : 0xB0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
rxchfr : Receiver channel FIFO reset
bits : 0 - 0 (1 bit)
Enumeration: FLUSH
0 : not_flush
Not flush an individual FIFO
1 : flush
Flush an indiviadual FIFO
End of enumeration elements list.
Transmit FIFO Flush Register
address_offset : 0xB4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
rtxchfr : Transmit channel FIFO reset
bits : 0 - 0 (1 bit)
Enumeration:
End of enumeration elements list.
Clock Generation enable
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
clken : Transmitter block enable
bits : 0 - 0 (1 bit)
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