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APU

Peripheral Memory Blocks

Registers

ch_cfg

dir_bidx[0]

dir_bidx[9]

pre_fir0_coef[0]

dwsz_cfg

fft_cfg

sobuf_dma_rdata

vobuf_dma_rdata

int_stat

int_mask

sat_counter

sat_limits

dir_bidx[10]

post_fir0_coef[0]

dir_bidx[11]

pre_fir0_coef[1]

pre_fir1_coef[0]

dir_bidx[12]

dir_bidx[1]

dir_bidx[13]

post_fir1_coef[0]

post_fir0_coef[1]

dir_bidx[14]

pre_fir0_coef[2]

dir_bidx[15]

pre_fir1_coef[1]

dir_bidx[16]

post_fir0_coef[2]

dir_bidx[2]

pre_fir0_coef[3]

post_fir1_coef[1]

dir_bidx[17]

dir_bidx[18]

pre_fir1_coef[2]

pre_fir0_coef[4]

post_fir0_coef[3]

dir_bidx[19]

post_fir1_coef[2]

pre_fir0_coef[5]

dir_bidx[20]

ctl

dir_bidx[3]

pre_fir1_coef[3]

post_fir0_coef[4]

dir_bidx[21]

pre_fir0_coef[6]

dir_bidx[22]

post_fir1_coef[3]

post_fir0_coef[5]

pre_fir1_coef[4]

dir_bidx[23]

pre_fir0_coef[7]

dir_bidx[4]

dir_bidx[24]

post_fir0_coef[6]

pre_fir0_coef[8]

post_fir1_coef[4]

dir_bidx[25]

pre_fir1_coef[5]

dir_bidx[26]

post_fir0_coef[7]

dir_bidx[27]

pre_fir1_coef[6]

post_fir1_coef[5]

dir_bidx[5]

dir_bidx[28]

post_fir0_coef[8]

pre_fir1_coef[7]

dir_bidx[29]

post_fir1_coef[6]

dir_bidx[30]

pre_fir1_coef[8]

dir_bidx[31]

post_fir1_coef[7]

dir_bidx[6]

post_fir1_coef[8]

dir_bidx[7]

dir_bidx[8]


ch_cfg

Channel Config Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ch_cfg ch_cfg read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sound_ch_en target_dir audio_gain data_src_mode we_sound_ch_en we_target_dir we_audio_gain we_data_src_mode

sound_ch_en : BF unit sound channel enable control bits
bits : 0 - 7 (8 bit)

target_dir : Target direction select for valid voice output
bits : 8 - 19 (12 bit)

audio_gain : Audio sample gain factor
bits : 12 - 34 (23 bit)

data_src_mode : Audio data source configure parameter
bits : 24 - 48 (25 bit)

we_sound_ch_en : Write enable for sound_ch_en parameter
bits : 28 - 56 (29 bit)
access : write-only

we_target_dir : Write enable for target_dir parameter
bits : 29 - 58 (30 bit)
access : write-only

we_audio_gain : Write enable for audio_gain parameter
bits : 30 - 60 (31 bit)
access : write-only

we_data_src_mode : Write enable for data_out_mode parameter
bits : 31 - 62 (32 bit)
access : write-only


dir_bidx[0]

Direction Sample Buffer Read Index Configure Register (16 directions * 2 values * 4 indices)
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

dir_bidx[0] dir_bidx[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rd_idx0 rd_idx8 rd_idx16 rd_idx24

rd_idx0 : rd_idx%s
bits : 0 - 5 (6 bit)

rd_idx8 : rd_idx%s
bits : 0 - 5 (6 bit)

rd_idx16 : rd_idx%s
bits : 0 - 5 (6 bit)

rd_idx24 : rd_idx%s
bits : 0 - 5 (6 bit)


dir_bidx[9]

Direction Sample Buffer Read Index Configure Register (16 directions * 2 values * 4 indices)
address_offset : 0x10C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

dir_bidx[9] dir_bidx[9] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rd_idx24

rd_idx24 : rd_idx%s
bits : 0 - 5 (6 bit)


pre_fir0_coef[0]

FIR0 pre-filter coefficients
address_offset : 0x110 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

pre_fir0_coef[0] pre_fir0_coef[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tap0 tap1

tap0 : Tap 0
bits : 0 - 15 (16 bit)

tap1 : Tap 1
bits : 16 - 47 (32 bit)


dwsz_cfg

Downsize Config Register
address_offset : 0x118 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

dwsz_cfg dwsz_cfg read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dir_dwn_siz_rate voc_dwn_siz_rate smpl_shift_bits

dir_dwn_siz_rate : Down-sizing ratio used for direction searching
bits : 0 - 3 (4 bit)

voc_dwn_siz_rate : Down-sizing ratio used for voice stream generation
bits : 4 - 11 (8 bit)

smpl_shift_bits : Sample precision reduction when the source sound sample precision is 20/24/32 bits
bits : 8 - 20 (13 bit)


fft_cfg

FFT Config Register
address_offset : 0x11C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

fft_cfg fft_cfg read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 fft_shift_factor fft_enable

fft_shift_factor : FFT shift factor
bits : 0 - 8 (9 bit)

fft_enable : FFT enable
bits : 12 - 24 (13 bit)


sobuf_dma_rdata

Read register for DMA to sample-out buffers
address_offset : 0x120 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

sobuf_dma_rdata sobuf_dma_rdata read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

vobuf_dma_rdata

Read register for DMA to voice-out buffers
address_offset : 0x124 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

vobuf_dma_rdata vobuf_dma_rdata read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

int_stat

Interrupt Status Register
address_offset : 0x128 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

int_stat int_stat read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dir_search_data_rdy voc_buf_data_rdy

dir_search_data_rdy : Sound direction searching data ready interrupt event
bits : 0 - 0 (1 bit)

voc_buf_data_rdy : Voice output stream buffer data ready interrupt event
bits : 1 - 2 (2 bit)


int_mask

Interrupt Mask Register
address_offset : 0x12C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

int_mask int_mask read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dir_search_data_rdy voc_buf_data_rdy

dir_search_data_rdy : Sound direction searching data ready interrupt event
bits : 0 - 0 (1 bit)

voc_buf_data_rdy : Voice output stream buffer data ready interrupt event
bits : 1 - 2 (2 bit)


sat_counter

Saturation Counter
address_offset : 0x130 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

sat_counter sat_counter read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 counter total

counter : Counter
bits : 0 - 15 (16 bit)

total : Total
bits : 16 - 47 (32 bit)


sat_limits

Saturation Limits
address_offset : 0x134 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

sat_limits sat_limits read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 upper bottom

upper : Upper limit
bits : 0 - 15 (16 bit)

bottom : Bottom limit
bits : 16 - 47 (32 bit)


dir_bidx[10]

Direction Sample Buffer Read Index Configure Register (16 directions * 2 values * 4 indices)
address_offset : 0x13C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

dir_bidx[10] dir_bidx[10] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rd_idx24

rd_idx24 : rd_idx%s
bits : 0 - 5 (6 bit)


post_fir0_coef[0]

FIR0 post-filter coefficients
address_offset : 0x158 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

post_fir0_coef[0] post_fir0_coef[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tap0 tap1

tap0 : Tap 0
bits : 0 - 15 (16 bit)

tap1 : Tap 1
bits : 16 - 47 (32 bit)


dir_bidx[11]

Direction Sample Buffer Read Index Configure Register (16 directions * 2 values * 4 indices)
address_offset : 0x170 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

dir_bidx[11] dir_bidx[11] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rd_idx24

rd_idx24 : rd_idx%s
bits : 0 - 5 (6 bit)


pre_fir0_coef[1]

FIR0 pre-filter coefficients
address_offset : 0x19C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

pre_fir0_coef[1] pre_fir0_coef[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tap0 tap1

tap0 : Tap 0
bits : 0 - 15 (16 bit)

tap1 : Tap 1
bits : 16 - 47 (32 bit)


pre_fir1_coef[0]

FIR1 pre-filter coeffecients
address_offset : 0x1A0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

pre_fir1_coef[0] pre_fir1_coef[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tap0 tap1

tap0 : Tap 0
bits : 0 - 15 (16 bit)

tap1 : Tap 1
bits : 16 - 47 (32 bit)


dir_bidx[12]

Direction Sample Buffer Read Index Configure Register (16 directions * 2 values * 4 indices)
address_offset : 0x1A8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

dir_bidx[12] dir_bidx[12] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rd_idx24

rd_idx24 : rd_idx%s
bits : 0 - 5 (6 bit)


dir_bidx[1]

Direction Sample Buffer Read Index Configure Register (16 directions * 2 values * 4 indices)
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

dir_bidx[1] dir_bidx[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rd_idx24

rd_idx24 : rd_idx%s
bits : 0 - 5 (6 bit)


dir_bidx[13]

Direction Sample Buffer Read Index Configure Register (16 directions * 2 values * 4 indices)
address_offset : 0x1E4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

dir_bidx[13] dir_bidx[13] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rd_idx24

rd_idx24 : rd_idx%s
bits : 0 - 5 (6 bit)


post_fir1_coef[0]

FIR1 post-filter coefficients
address_offset : 0x1E8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

post_fir1_coef[0] post_fir1_coef[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tap0 tap1

tap0 : Tap 0
bits : 0 - 15 (16 bit)

tap1 : Tap 1
bits : 16 - 47 (32 bit)


post_fir0_coef[1]

FIR0 post-filter coefficients
address_offset : 0x208 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

post_fir0_coef[1] post_fir0_coef[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tap0 tap1

tap0 : Tap 0
bits : 0 - 15 (16 bit)

tap1 : Tap 1
bits : 16 - 47 (32 bit)


dir_bidx[14]

Direction Sample Buffer Read Index Configure Register (16 directions * 2 values * 4 indices)
address_offset : 0x224 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

dir_bidx[14] dir_bidx[14] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rd_idx24

rd_idx24 : rd_idx%s
bits : 0 - 5 (6 bit)


pre_fir0_coef[2]

FIR0 pre-filter coefficients
address_offset : 0x22C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

pre_fir0_coef[2] pre_fir0_coef[2] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tap0 tap1

tap0 : Tap 0
bits : 0 - 15 (16 bit)

tap1 : Tap 1
bits : 16 - 47 (32 bit)


dir_bidx[15]

Direction Sample Buffer Read Index Configure Register (16 directions * 2 values * 4 indices)
address_offset : 0x268 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

dir_bidx[15] dir_bidx[15] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rd_idx24

rd_idx24 : rd_idx%s
bits : 0 - 5 (6 bit)


pre_fir1_coef[1]

FIR1 pre-filter coeffecients
address_offset : 0x274 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

pre_fir1_coef[1] pre_fir1_coef[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tap0 tap1

tap0 : Tap 0
bits : 0 - 15 (16 bit)

tap1 : Tap 1
bits : 16 - 47 (32 bit)


dir_bidx[16]

Direction Sample Buffer Read Index Configure Register (16 directions * 2 values * 4 indices)
address_offset : 0x2B0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

dir_bidx[16] dir_bidx[16] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rd_idx24

rd_idx24 : rd_idx%s
bits : 0 - 5 (6 bit)


post_fir0_coef[2]

FIR0 post-filter coefficients
address_offset : 0x2BC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

post_fir0_coef[2] post_fir0_coef[2] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tap0 tap1

tap0 : Tap 0
bits : 0 - 15 (16 bit)

tap1 : Tap 1
bits : 16 - 47 (32 bit)


dir_bidx[2]

Direction Sample Buffer Read Index Configure Register (16 directions * 2 values * 4 indices)
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

dir_bidx[2] dir_bidx[2] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rd_idx24

rd_idx24 : rd_idx%s
bits : 0 - 5 (6 bit)


pre_fir0_coef[3]

FIR0 pre-filter coefficients
address_offset : 0x2C0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

pre_fir0_coef[3] pre_fir0_coef[3] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tap0 tap1

tap0 : Tap 0
bits : 0 - 15 (16 bit)

tap1 : Tap 1
bits : 16 - 47 (32 bit)


post_fir1_coef[1]

FIR1 post-filter coefficients
address_offset : 0x2E0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

post_fir1_coef[1] post_fir1_coef[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tap0 tap1

tap0 : Tap 0
bits : 0 - 15 (16 bit)

tap1 : Tap 1
bits : 16 - 47 (32 bit)


dir_bidx[17]

Direction Sample Buffer Read Index Configure Register (16 directions * 2 values * 4 indices)
address_offset : 0x2FC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

dir_bidx[17] dir_bidx[17] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rd_idx24

rd_idx24 : rd_idx%s
bits : 0 - 5 (6 bit)


dir_bidx[18]

Direction Sample Buffer Read Index Configure Register (16 directions * 2 values * 4 indices)
address_offset : 0x34C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

dir_bidx[18] dir_bidx[18] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rd_idx24

rd_idx24 : rd_idx%s
bits : 0 - 5 (6 bit)


pre_fir1_coef[2]

FIR1 pre-filter coeffecients
address_offset : 0x34C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

pre_fir1_coef[2] pre_fir1_coef[2] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tap0 tap1

tap0 : Tap 0
bits : 0 - 15 (16 bit)

tap1 : Tap 1
bits : 16 - 47 (32 bit)


pre_fir0_coef[4]

FIR0 pre-filter coefficients
address_offset : 0x358 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

pre_fir0_coef[4] pre_fir0_coef[4] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tap0 tap1

tap0 : Tap 0
bits : 0 - 15 (16 bit)

tap1 : Tap 1
bits : 16 - 47 (32 bit)


post_fir0_coef[3]

FIR0 post-filter coefficients
address_offset : 0x374 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

post_fir0_coef[3] post_fir0_coef[3] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tap0 tap1

tap0 : Tap 0
bits : 0 - 15 (16 bit)

tap1 : Tap 1
bits : 16 - 47 (32 bit)


dir_bidx[19]

Direction Sample Buffer Read Index Configure Register (16 directions * 2 values * 4 indices)
address_offset : 0x3A0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

dir_bidx[19] dir_bidx[19] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rd_idx24

rd_idx24 : rd_idx%s
bits : 0 - 5 (6 bit)


post_fir1_coef[2]

FIR1 post-filter coefficients
address_offset : 0x3DC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

post_fir1_coef[2] post_fir1_coef[2] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tap0 tap1

tap0 : Tap 0
bits : 0 - 15 (16 bit)

tap1 : Tap 1
bits : 16 - 47 (32 bit)


pre_fir0_coef[5]

FIR0 pre-filter coefficients
address_offset : 0x3F4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

pre_fir0_coef[5] pre_fir0_coef[5] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tap0 tap1

tap0 : Tap 0
bits : 0 - 15 (16 bit)

tap1 : Tap 1
bits : 16 - 47 (32 bit)


dir_bidx[20]

Direction Sample Buffer Read Index Configure Register (16 directions * 2 values * 4 indices)
address_offset : 0x3F8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

dir_bidx[20] dir_bidx[20] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rd_idx24

rd_idx24 : rd_idx%s
bits : 0 - 5 (6 bit)


ctl

Control Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ctl ctl read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dir_search_en search_path_reset stream_gen_en voice_gen_path_reset update_voice_dir we_dir_search_en we_search_path_rst we_stream_gen we_voice_gen_path_rst we_update_voice_dir

dir_search_en : Sound direction searching enable bit
bits : 0 - 0 (1 bit)

search_path_reset : Reset all control logic on direction search processing path
bits : 1 - 2 (2 bit)

stream_gen_en : Valid voice sample stream generation enable bit
bits : 4 - 8 (5 bit)

voice_gen_path_reset : Reset all control logic on voice stream generating path
bits : 5 - 10 (6 bit)

update_voice_dir : Switch to a new voice source direction
bits : 6 - 12 (7 bit)

we_dir_search_en : Write enable for we_dir_search_en parameter
bits : 8 - 16 (9 bit)
access : write-only

we_search_path_rst : Write enable for we_search_path_rst parameter
bits : 9 - 18 (10 bit)
access : write-only

we_stream_gen : Write enable for we_stream_gen parameter
bits : 10 - 20 (11 bit)
access : write-only

we_voice_gen_path_rst : Write enable for we_voice_gen_path_rst parameter
bits : 11 - 22 (12 bit)
access : write-only

we_update_voice_dir : Write enable for we_update_voice_dir parameter
bits : 12 - 24 (13 bit)
access : write-only


dir_bidx[3]

Direction Sample Buffer Read Index Configure Register (16 directions * 2 values * 4 indices)
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

dir_bidx[3] dir_bidx[3] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rd_idx24

rd_idx24 : rd_idx%s
bits : 0 - 5 (6 bit)


pre_fir1_coef[3]

FIR1 pre-filter coeffecients
address_offset : 0x428 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

pre_fir1_coef[3] pre_fir1_coef[3] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tap0 tap1

tap0 : Tap 0
bits : 0 - 15 (16 bit)

tap1 : Tap 1
bits : 16 - 47 (32 bit)


post_fir0_coef[4]

FIR0 post-filter coefficients
address_offset : 0x430 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

post_fir0_coef[4] post_fir0_coef[4] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tap0 tap1

tap0 : Tap 0
bits : 0 - 15 (16 bit)

tap1 : Tap 1
bits : 16 - 47 (32 bit)


dir_bidx[21]

Direction Sample Buffer Read Index Configure Register (16 directions * 2 values * 4 indices)
address_offset : 0x454 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

dir_bidx[21] dir_bidx[21] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rd_idx24

rd_idx24 : rd_idx%s
bits : 0 - 5 (6 bit)


pre_fir0_coef[6]

FIR0 pre-filter coefficients
address_offset : 0x494 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

pre_fir0_coef[6] pre_fir0_coef[6] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tap0 tap1

tap0 : Tap 0
bits : 0 - 15 (16 bit)

tap1 : Tap 1
bits : 16 - 47 (32 bit)


dir_bidx[22]

Direction Sample Buffer Read Index Configure Register (16 directions * 2 values * 4 indices)
address_offset : 0x4B4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

dir_bidx[22] dir_bidx[22] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rd_idx24

rd_idx24 : rd_idx%s
bits : 0 - 5 (6 bit)


post_fir1_coef[3]

FIR1 post-filter coefficients
address_offset : 0x4DC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

post_fir1_coef[3] post_fir1_coef[3] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tap0 tap1

tap0 : Tap 0
bits : 0 - 15 (16 bit)

tap1 : Tap 1
bits : 16 - 47 (32 bit)


post_fir0_coef[5]

FIR0 post-filter coefficients
address_offset : 0x4F0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

post_fir0_coef[5] post_fir0_coef[5] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tap0 tap1

tap0 : Tap 0
bits : 0 - 15 (16 bit)

tap1 : Tap 1
bits : 16 - 47 (32 bit)


pre_fir1_coef[4]

FIR1 pre-filter coeffecients
address_offset : 0x508 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

pre_fir1_coef[4] pre_fir1_coef[4] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tap0 tap1

tap0 : Tap 0
bits : 0 - 15 (16 bit)

tap1 : Tap 1
bits : 16 - 47 (32 bit)


dir_bidx[23]

Direction Sample Buffer Read Index Configure Register (16 directions * 2 values * 4 indices)
address_offset : 0x518 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

dir_bidx[23] dir_bidx[23] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rd_idx24

rd_idx24 : rd_idx%s
bits : 0 - 5 (6 bit)


pre_fir0_coef[7]

FIR0 pre-filter coefficients
address_offset : 0x538 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

pre_fir0_coef[7] pre_fir0_coef[7] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tap0 tap1

tap0 : Tap 0
bits : 0 - 15 (16 bit)

tap1 : Tap 1
bits : 16 - 47 (32 bit)


dir_bidx[4]

Direction Sample Buffer Read Index Configure Register (16 directions * 2 values * 4 indices)
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

dir_bidx[4] dir_bidx[4] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rd_idx24

rd_idx24 : rd_idx%s
bits : 0 - 5 (6 bit)


dir_bidx[24]

Direction Sample Buffer Read Index Configure Register (16 directions * 2 values * 4 indices)
address_offset : 0x580 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

dir_bidx[24] dir_bidx[24] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rd_idx24

rd_idx24 : rd_idx%s
bits : 0 - 5 (6 bit)


post_fir0_coef[6]

FIR0 post-filter coefficients
address_offset : 0x5B4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

post_fir0_coef[6] post_fir0_coef[6] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tap0 tap1

tap0 : Tap 0
bits : 0 - 15 (16 bit)

tap1 : Tap 1
bits : 16 - 47 (32 bit)


pre_fir0_coef[8]

FIR0 pre-filter coefficients
address_offset : 0x5E0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

pre_fir0_coef[8] pre_fir0_coef[8] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tap0 tap1

tap0 : Tap 0
bits : 0 - 15 (16 bit)

tap1 : Tap 1
bits : 16 - 47 (32 bit)


post_fir1_coef[4]

FIR1 post-filter coefficients
address_offset : 0x5E0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

post_fir1_coef[4] post_fir1_coef[4] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tap0 tap1

tap0 : Tap 0
bits : 0 - 15 (16 bit)

tap1 : Tap 1
bits : 16 - 47 (32 bit)


dir_bidx[25]

Direction Sample Buffer Read Index Configure Register (16 directions * 2 values * 4 indices)
address_offset : 0x5EC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

dir_bidx[25] dir_bidx[25] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rd_idx24

rd_idx24 : rd_idx%s
bits : 0 - 5 (6 bit)


pre_fir1_coef[5]

FIR1 pre-filter coeffecients
address_offset : 0x5EC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

pre_fir1_coef[5] pre_fir1_coef[5] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tap0 tap1

tap0 : Tap 0
bits : 0 - 15 (16 bit)

tap1 : Tap 1
bits : 16 - 47 (32 bit)


dir_bidx[26]

Direction Sample Buffer Read Index Configure Register (16 directions * 2 values * 4 indices)
address_offset : 0x65C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

dir_bidx[26] dir_bidx[26] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rd_idx24

rd_idx24 : rd_idx%s
bits : 0 - 5 (6 bit)


post_fir0_coef[7]

FIR0 post-filter coefficients
address_offset : 0x67C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

post_fir0_coef[7] post_fir0_coef[7] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tap0 tap1

tap0 : Tap 0
bits : 0 - 15 (16 bit)

tap1 : Tap 1
bits : 16 - 47 (32 bit)


dir_bidx[27]

Direction Sample Buffer Read Index Configure Register (16 directions * 2 values * 4 indices)
address_offset : 0x6D0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

dir_bidx[27] dir_bidx[27] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rd_idx24

rd_idx24 : rd_idx%s
bits : 0 - 5 (6 bit)


pre_fir1_coef[6]

FIR1 pre-filter coeffecients
address_offset : 0x6D4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

pre_fir1_coef[6] pre_fir1_coef[6] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tap0 tap1

tap0 : Tap 0
bits : 0 - 15 (16 bit)

tap1 : Tap 1
bits : 16 - 47 (32 bit)


post_fir1_coef[5]

FIR1 post-filter coefficients
address_offset : 0x6E8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

post_fir1_coef[5] post_fir1_coef[5] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tap0 tap1

tap0 : Tap 0
bits : 0 - 15 (16 bit)

tap1 : Tap 1
bits : 16 - 47 (32 bit)


dir_bidx[5]

Direction Sample Buffer Read Index Configure Register (16 directions * 2 values * 4 indices)
address_offset : 0x74 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

dir_bidx[5] dir_bidx[5] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rd_idx24

rd_idx24 : rd_idx%s
bits : 0 - 5 (6 bit)


dir_bidx[28]

Direction Sample Buffer Read Index Configure Register (16 directions * 2 values * 4 indices)
address_offset : 0x748 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

dir_bidx[28] dir_bidx[28] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rd_idx24

rd_idx24 : rd_idx%s
bits : 0 - 5 (6 bit)


post_fir0_coef[8]

FIR0 post-filter coefficients
address_offset : 0x748 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

post_fir0_coef[8] post_fir0_coef[8] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tap0 tap1

tap0 : Tap 0
bits : 0 - 15 (16 bit)

tap1 : Tap 1
bits : 16 - 47 (32 bit)


pre_fir1_coef[7]

FIR1 pre-filter coeffecients
address_offset : 0x7C0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

pre_fir1_coef[7] pre_fir1_coef[7] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tap0 tap1

tap0 : Tap 0
bits : 0 - 15 (16 bit)

tap1 : Tap 1
bits : 16 - 47 (32 bit)


dir_bidx[29]

Direction Sample Buffer Read Index Configure Register (16 directions * 2 values * 4 indices)
address_offset : 0x7C4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

dir_bidx[29] dir_bidx[29] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rd_idx24

rd_idx24 : rd_idx%s
bits : 0 - 5 (6 bit)


post_fir1_coef[6]

FIR1 post-filter coefficients
address_offset : 0x7F4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

post_fir1_coef[6] post_fir1_coef[6] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tap0 tap1

tap0 : Tap 0
bits : 0 - 15 (16 bit)

tap1 : Tap 1
bits : 16 - 47 (32 bit)


dir_bidx[30]

Direction Sample Buffer Read Index Configure Register (16 directions * 2 values * 4 indices)
address_offset : 0x844 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

dir_bidx[30] dir_bidx[30] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rd_idx24

rd_idx24 : rd_idx%s
bits : 0 - 5 (6 bit)


pre_fir1_coef[8]

FIR1 pre-filter coeffecients
address_offset : 0x8B0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

pre_fir1_coef[8] pre_fir1_coef[8] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tap0 tap1

tap0 : Tap 0
bits : 0 - 15 (16 bit)

tap1 : Tap 1
bits : 16 - 47 (32 bit)


dir_bidx[31]

Direction Sample Buffer Read Index Configure Register (16 directions * 2 values * 4 indices)
address_offset : 0x8C8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

dir_bidx[31] dir_bidx[31] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rd_idx24

rd_idx24 : rd_idx%s
bits : 0 - 5 (6 bit)


post_fir1_coef[7]

FIR1 post-filter coefficients
address_offset : 0x904 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

post_fir1_coef[7] post_fir1_coef[7] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tap0 tap1

tap0 : Tap 0
bits : 0 - 15 (16 bit)

tap1 : Tap 1
bits : 16 - 47 (32 bit)


dir_bidx[6]

Direction Sample Buffer Read Index Configure Register (16 directions * 2 values * 4 indices)
address_offset : 0x94 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

dir_bidx[6] dir_bidx[6] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rd_idx24

rd_idx24 : rd_idx%s
bits : 0 - 5 (6 bit)


post_fir1_coef[8]

FIR1 post-filter coefficients
address_offset : 0xA18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

post_fir1_coef[8] post_fir1_coef[8] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tap0 tap1

tap0 : Tap 0
bits : 0 - 15 (16 bit)

tap1 : Tap 1
bits : 16 - 47 (32 bit)


dir_bidx[7]

Direction Sample Buffer Read Index Configure Register (16 directions * 2 values * 4 indices)
address_offset : 0xB8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

dir_bidx[7] dir_bidx[7] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rd_idx24

rd_idx24 : rd_idx%s
bits : 0 - 5 (6 bit)


dir_bidx[8]

Direction Sample Buffer Read Index Configure Register (16 directions * 2 values * 4 indices)
address_offset : 0xE0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

dir_bidx[8] dir_bidx[8] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rd_idx24

rd_idx24 : rd_idx%s
bits : 0 - 5 (6 bit)



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