\n
Channel Config Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
sound_ch_en : BF unit sound channel enable control bits
bits : 0 - 7 (8 bit)
target_dir : Target direction select for valid voice output
bits : 8 - 19 (12 bit)
audio_gain : Audio sample gain factor
bits : 12 - 34 (23 bit)
data_src_mode : Audio data source configure parameter
bits : 24 - 48 (25 bit)
we_sound_ch_en : Write enable for sound_ch_en parameter
bits : 28 - 56 (29 bit)
access : write-only
we_target_dir : Write enable for target_dir parameter
bits : 29 - 58 (30 bit)
access : write-only
we_audio_gain : Write enable for audio_gain parameter
bits : 30 - 60 (31 bit)
access : write-only
we_data_src_mode : Write enable for data_out_mode parameter
bits : 31 - 62 (32 bit)
access : write-only
Direction Sample Buffer Read Index Configure Register (16 directions * 2 values * 4 indices)
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
rd_idx0 : rd_idx%s
bits : 0 - 5 (6 bit)
rd_idx8 : rd_idx%s
bits : 0 - 5 (6 bit)
rd_idx16 : rd_idx%s
bits : 0 - 5 (6 bit)
rd_idx24 : rd_idx%s
bits : 0 - 5 (6 bit)
Direction Sample Buffer Read Index Configure Register (16 directions * 2 values * 4 indices)
address_offset : 0x10C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
rd_idx24 : rd_idx%s
bits : 0 - 5 (6 bit)
FIR0 pre-filter coefficients
address_offset : 0x110 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
tap0 : Tap 0
bits : 0 - 15 (16 bit)
tap1 : Tap 1
bits : 16 - 47 (32 bit)
Downsize Config Register
address_offset : 0x118 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
dir_dwn_siz_rate : Down-sizing ratio used for direction searching
bits : 0 - 3 (4 bit)
voc_dwn_siz_rate : Down-sizing ratio used for voice stream generation
bits : 4 - 11 (8 bit)
smpl_shift_bits : Sample precision reduction when the source sound sample precision is 20/24/32 bits
bits : 8 - 20 (13 bit)
FFT Config Register
address_offset : 0x11C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
fft_shift_factor : FFT shift factor
bits : 0 - 8 (9 bit)
fft_enable : FFT enable
bits : 12 - 24 (13 bit)
Read register for DMA to sample-out buffers
address_offset : 0x120 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Read register for DMA to voice-out buffers
address_offset : 0x124 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Interrupt Status Register
address_offset : 0x128 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
dir_search_data_rdy : Sound direction searching data ready interrupt event
bits : 0 - 0 (1 bit)
voc_buf_data_rdy : Voice output stream buffer data ready interrupt event
bits : 1 - 2 (2 bit)
Interrupt Mask Register
address_offset : 0x12C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
dir_search_data_rdy : Sound direction searching data ready interrupt event
bits : 0 - 0 (1 bit)
voc_buf_data_rdy : Voice output stream buffer data ready interrupt event
bits : 1 - 2 (2 bit)
Saturation Counter
address_offset : 0x130 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
counter : Counter
bits : 0 - 15 (16 bit)
total : Total
bits : 16 - 47 (32 bit)
Saturation Limits
address_offset : 0x134 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
upper : Upper limit
bits : 0 - 15 (16 bit)
bottom : Bottom limit
bits : 16 - 47 (32 bit)
Direction Sample Buffer Read Index Configure Register (16 directions * 2 values * 4 indices)
address_offset : 0x13C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
rd_idx24 : rd_idx%s
bits : 0 - 5 (6 bit)
FIR0 post-filter coefficients
address_offset : 0x158 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
tap0 : Tap 0
bits : 0 - 15 (16 bit)
tap1 : Tap 1
bits : 16 - 47 (32 bit)
Direction Sample Buffer Read Index Configure Register (16 directions * 2 values * 4 indices)
address_offset : 0x170 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
rd_idx24 : rd_idx%s
bits : 0 - 5 (6 bit)
FIR0 pre-filter coefficients
address_offset : 0x19C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
tap0 : Tap 0
bits : 0 - 15 (16 bit)
tap1 : Tap 1
bits : 16 - 47 (32 bit)
FIR1 pre-filter coeffecients
address_offset : 0x1A0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
tap0 : Tap 0
bits : 0 - 15 (16 bit)
tap1 : Tap 1
bits : 16 - 47 (32 bit)
Direction Sample Buffer Read Index Configure Register (16 directions * 2 values * 4 indices)
address_offset : 0x1A8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
rd_idx24 : rd_idx%s
bits : 0 - 5 (6 bit)
Direction Sample Buffer Read Index Configure Register (16 directions * 2 values * 4 indices)
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
rd_idx24 : rd_idx%s
bits : 0 - 5 (6 bit)
Direction Sample Buffer Read Index Configure Register (16 directions * 2 values * 4 indices)
address_offset : 0x1E4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
rd_idx24 : rd_idx%s
bits : 0 - 5 (6 bit)
FIR1 post-filter coefficients
address_offset : 0x1E8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
tap0 : Tap 0
bits : 0 - 15 (16 bit)
tap1 : Tap 1
bits : 16 - 47 (32 bit)
FIR0 post-filter coefficients
address_offset : 0x208 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
tap0 : Tap 0
bits : 0 - 15 (16 bit)
tap1 : Tap 1
bits : 16 - 47 (32 bit)
Direction Sample Buffer Read Index Configure Register (16 directions * 2 values * 4 indices)
address_offset : 0x224 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
rd_idx24 : rd_idx%s
bits : 0 - 5 (6 bit)
FIR0 pre-filter coefficients
address_offset : 0x22C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
tap0 : Tap 0
bits : 0 - 15 (16 bit)
tap1 : Tap 1
bits : 16 - 47 (32 bit)
Direction Sample Buffer Read Index Configure Register (16 directions * 2 values * 4 indices)
address_offset : 0x268 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
rd_idx24 : rd_idx%s
bits : 0 - 5 (6 bit)
FIR1 pre-filter coeffecients
address_offset : 0x274 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
tap0 : Tap 0
bits : 0 - 15 (16 bit)
tap1 : Tap 1
bits : 16 - 47 (32 bit)
Direction Sample Buffer Read Index Configure Register (16 directions * 2 values * 4 indices)
address_offset : 0x2B0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
rd_idx24 : rd_idx%s
bits : 0 - 5 (6 bit)
FIR0 post-filter coefficients
address_offset : 0x2BC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
tap0 : Tap 0
bits : 0 - 15 (16 bit)
tap1 : Tap 1
bits : 16 - 47 (32 bit)
Direction Sample Buffer Read Index Configure Register (16 directions * 2 values * 4 indices)
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
rd_idx24 : rd_idx%s
bits : 0 - 5 (6 bit)
FIR0 pre-filter coefficients
address_offset : 0x2C0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
tap0 : Tap 0
bits : 0 - 15 (16 bit)
tap1 : Tap 1
bits : 16 - 47 (32 bit)
FIR1 post-filter coefficients
address_offset : 0x2E0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
tap0 : Tap 0
bits : 0 - 15 (16 bit)
tap1 : Tap 1
bits : 16 - 47 (32 bit)
Direction Sample Buffer Read Index Configure Register (16 directions * 2 values * 4 indices)
address_offset : 0x2FC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
rd_idx24 : rd_idx%s
bits : 0 - 5 (6 bit)
Direction Sample Buffer Read Index Configure Register (16 directions * 2 values * 4 indices)
address_offset : 0x34C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
rd_idx24 : rd_idx%s
bits : 0 - 5 (6 bit)
FIR1 pre-filter coeffecients
address_offset : 0x34C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
tap0 : Tap 0
bits : 0 - 15 (16 bit)
tap1 : Tap 1
bits : 16 - 47 (32 bit)
FIR0 pre-filter coefficients
address_offset : 0x358 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
tap0 : Tap 0
bits : 0 - 15 (16 bit)
tap1 : Tap 1
bits : 16 - 47 (32 bit)
FIR0 post-filter coefficients
address_offset : 0x374 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
tap0 : Tap 0
bits : 0 - 15 (16 bit)
tap1 : Tap 1
bits : 16 - 47 (32 bit)
Direction Sample Buffer Read Index Configure Register (16 directions * 2 values * 4 indices)
address_offset : 0x3A0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
rd_idx24 : rd_idx%s
bits : 0 - 5 (6 bit)
FIR1 post-filter coefficients
address_offset : 0x3DC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
tap0 : Tap 0
bits : 0 - 15 (16 bit)
tap1 : Tap 1
bits : 16 - 47 (32 bit)
FIR0 pre-filter coefficients
address_offset : 0x3F4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
tap0 : Tap 0
bits : 0 - 15 (16 bit)
tap1 : Tap 1
bits : 16 - 47 (32 bit)
Direction Sample Buffer Read Index Configure Register (16 directions * 2 values * 4 indices)
address_offset : 0x3F8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
rd_idx24 : rd_idx%s
bits : 0 - 5 (6 bit)
Control Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
dir_search_en : Sound direction searching enable bit
bits : 0 - 0 (1 bit)
search_path_reset : Reset all control logic on direction search processing path
bits : 1 - 2 (2 bit)
stream_gen_en : Valid voice sample stream generation enable bit
bits : 4 - 8 (5 bit)
voice_gen_path_reset : Reset all control logic on voice stream generating path
bits : 5 - 10 (6 bit)
update_voice_dir : Switch to a new voice source direction
bits : 6 - 12 (7 bit)
we_dir_search_en : Write enable for we_dir_search_en parameter
bits : 8 - 16 (9 bit)
access : write-only
we_search_path_rst : Write enable for we_search_path_rst parameter
bits : 9 - 18 (10 bit)
access : write-only
we_stream_gen : Write enable for we_stream_gen parameter
bits : 10 - 20 (11 bit)
access : write-only
we_voice_gen_path_rst : Write enable for we_voice_gen_path_rst parameter
bits : 11 - 22 (12 bit)
access : write-only
we_update_voice_dir : Write enable for we_update_voice_dir parameter
bits : 12 - 24 (13 bit)
access : write-only
Direction Sample Buffer Read Index Configure Register (16 directions * 2 values * 4 indices)
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
rd_idx24 : rd_idx%s
bits : 0 - 5 (6 bit)
FIR1 pre-filter coeffecients
address_offset : 0x428 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
tap0 : Tap 0
bits : 0 - 15 (16 bit)
tap1 : Tap 1
bits : 16 - 47 (32 bit)
FIR0 post-filter coefficients
address_offset : 0x430 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
tap0 : Tap 0
bits : 0 - 15 (16 bit)
tap1 : Tap 1
bits : 16 - 47 (32 bit)
Direction Sample Buffer Read Index Configure Register (16 directions * 2 values * 4 indices)
address_offset : 0x454 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
rd_idx24 : rd_idx%s
bits : 0 - 5 (6 bit)
FIR0 pre-filter coefficients
address_offset : 0x494 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
tap0 : Tap 0
bits : 0 - 15 (16 bit)
tap1 : Tap 1
bits : 16 - 47 (32 bit)
Direction Sample Buffer Read Index Configure Register (16 directions * 2 values * 4 indices)
address_offset : 0x4B4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
rd_idx24 : rd_idx%s
bits : 0 - 5 (6 bit)
FIR1 post-filter coefficients
address_offset : 0x4DC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
tap0 : Tap 0
bits : 0 - 15 (16 bit)
tap1 : Tap 1
bits : 16 - 47 (32 bit)
FIR0 post-filter coefficients
address_offset : 0x4F0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
tap0 : Tap 0
bits : 0 - 15 (16 bit)
tap1 : Tap 1
bits : 16 - 47 (32 bit)
FIR1 pre-filter coeffecients
address_offset : 0x508 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
tap0 : Tap 0
bits : 0 - 15 (16 bit)
tap1 : Tap 1
bits : 16 - 47 (32 bit)
Direction Sample Buffer Read Index Configure Register (16 directions * 2 values * 4 indices)
address_offset : 0x518 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
rd_idx24 : rd_idx%s
bits : 0 - 5 (6 bit)
FIR0 pre-filter coefficients
address_offset : 0x538 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
tap0 : Tap 0
bits : 0 - 15 (16 bit)
tap1 : Tap 1
bits : 16 - 47 (32 bit)
Direction Sample Buffer Read Index Configure Register (16 directions * 2 values * 4 indices)
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
rd_idx24 : rd_idx%s
bits : 0 - 5 (6 bit)
Direction Sample Buffer Read Index Configure Register (16 directions * 2 values * 4 indices)
address_offset : 0x580 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
rd_idx24 : rd_idx%s
bits : 0 - 5 (6 bit)
FIR0 post-filter coefficients
address_offset : 0x5B4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
tap0 : Tap 0
bits : 0 - 15 (16 bit)
tap1 : Tap 1
bits : 16 - 47 (32 bit)
FIR0 pre-filter coefficients
address_offset : 0x5E0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
tap0 : Tap 0
bits : 0 - 15 (16 bit)
tap1 : Tap 1
bits : 16 - 47 (32 bit)
FIR1 post-filter coefficients
address_offset : 0x5E0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
tap0 : Tap 0
bits : 0 - 15 (16 bit)
tap1 : Tap 1
bits : 16 - 47 (32 bit)
Direction Sample Buffer Read Index Configure Register (16 directions * 2 values * 4 indices)
address_offset : 0x5EC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
rd_idx24 : rd_idx%s
bits : 0 - 5 (6 bit)
FIR1 pre-filter coeffecients
address_offset : 0x5EC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
tap0 : Tap 0
bits : 0 - 15 (16 bit)
tap1 : Tap 1
bits : 16 - 47 (32 bit)
Direction Sample Buffer Read Index Configure Register (16 directions * 2 values * 4 indices)
address_offset : 0x65C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
rd_idx24 : rd_idx%s
bits : 0 - 5 (6 bit)
FIR0 post-filter coefficients
address_offset : 0x67C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
tap0 : Tap 0
bits : 0 - 15 (16 bit)
tap1 : Tap 1
bits : 16 - 47 (32 bit)
Direction Sample Buffer Read Index Configure Register (16 directions * 2 values * 4 indices)
address_offset : 0x6D0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
rd_idx24 : rd_idx%s
bits : 0 - 5 (6 bit)
FIR1 pre-filter coeffecients
address_offset : 0x6D4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
tap0 : Tap 0
bits : 0 - 15 (16 bit)
tap1 : Tap 1
bits : 16 - 47 (32 bit)
FIR1 post-filter coefficients
address_offset : 0x6E8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
tap0 : Tap 0
bits : 0 - 15 (16 bit)
tap1 : Tap 1
bits : 16 - 47 (32 bit)
Direction Sample Buffer Read Index Configure Register (16 directions * 2 values * 4 indices)
address_offset : 0x74 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
rd_idx24 : rd_idx%s
bits : 0 - 5 (6 bit)
Direction Sample Buffer Read Index Configure Register (16 directions * 2 values * 4 indices)
address_offset : 0x748 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
rd_idx24 : rd_idx%s
bits : 0 - 5 (6 bit)
FIR0 post-filter coefficients
address_offset : 0x748 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
tap0 : Tap 0
bits : 0 - 15 (16 bit)
tap1 : Tap 1
bits : 16 - 47 (32 bit)
FIR1 pre-filter coeffecients
address_offset : 0x7C0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
tap0 : Tap 0
bits : 0 - 15 (16 bit)
tap1 : Tap 1
bits : 16 - 47 (32 bit)
Direction Sample Buffer Read Index Configure Register (16 directions * 2 values * 4 indices)
address_offset : 0x7C4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
rd_idx24 : rd_idx%s
bits : 0 - 5 (6 bit)
FIR1 post-filter coefficients
address_offset : 0x7F4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
tap0 : Tap 0
bits : 0 - 15 (16 bit)
tap1 : Tap 1
bits : 16 - 47 (32 bit)
Direction Sample Buffer Read Index Configure Register (16 directions * 2 values * 4 indices)
address_offset : 0x844 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
rd_idx24 : rd_idx%s
bits : 0 - 5 (6 bit)
FIR1 pre-filter coeffecients
address_offset : 0x8B0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
tap0 : Tap 0
bits : 0 - 15 (16 bit)
tap1 : Tap 1
bits : 16 - 47 (32 bit)
Direction Sample Buffer Read Index Configure Register (16 directions * 2 values * 4 indices)
address_offset : 0x8C8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
rd_idx24 : rd_idx%s
bits : 0 - 5 (6 bit)
FIR1 post-filter coefficients
address_offset : 0x904 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
tap0 : Tap 0
bits : 0 - 15 (16 bit)
tap1 : Tap 1
bits : 16 - 47 (32 bit)
Direction Sample Buffer Read Index Configure Register (16 directions * 2 values * 4 indices)
address_offset : 0x94 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
rd_idx24 : rd_idx%s
bits : 0 - 5 (6 bit)
FIR1 post-filter coefficients
address_offset : 0xA18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
tap0 : Tap 0
bits : 0 - 15 (16 bit)
tap1 : Tap 1
bits : 16 - 47 (32 bit)
Direction Sample Buffer Read Index Configure Register (16 directions * 2 values * 4 indices)
address_offset : 0xB8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
rd_idx24 : rd_idx%s
bits : 0 - 5 (6 bit)
Direction Sample Buffer Read Index Configure Register (16 directions * 2 values * 4 indices)
address_offset : 0xE0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
rd_idx24 : rd_idx%s
bits : 0 - 5 (6 bit)
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