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I2C

Peripheral Memory Blocks

Registers

con

data_cmd

ss_scl_hcnt

ss_scl_lcnt

intr_stat

intr_mask

raw_intr_stat

rx_tl

tx_tl

tar

clr_intr

clr_rx_under

clr_rx_over

clr_tx_over

clr_rd_req

clr_tx_abrt

clr_rx_done

clr_activity

clr_stop_det

clr_start_det

clr_gen_call

enable

status

txflr

rxflr

sda_hold

sar

tx_abrt_source

dma_cr

dma_tdlr

dma_rdlr

sda_setup

general_call

enable_status

fs_spklen

comp_param_1

comp_version

comp_type


con

Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

con con read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 master_mode speed addr_slave_width restart_en slave_disable stop_det tx_empty

master_mode : Master Mode
bits : 0 - 0 (1 bit)

speed : Speed
bits : 1 - 3 (3 bit)

Enumeration:

0 : standard

STANDARD

1 : fast

FAST

2 : highspeed

HIGHSPEED

End of enumeration elements list.

addr_slave_width : Slave address width
bits : 3 - 6 (4 bit)

Enumeration:

0 : b7

7-bit address

1 : b10

10-bit address

End of enumeration elements list.

restart_en : Enable Restart
bits : 5 - 10 (6 bit)

slave_disable : Disable Slave
bits : 6 - 12 (7 bit)

stop_det : STOP_DET_IFADDRESSED
bits : 7 - 14 (8 bit)

tx_empty : TX_EMPTY_CTRL
bits : 8 - 16 (9 bit)


data_cmd

Data Buffer and Command Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

data_cmd data_cmd read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data cmd

data : Data
bits : 0 - 7 (8 bit)

cmd : CMD
bits : 8 - 16 (9 bit)


ss_scl_hcnt

Standard Speed Clock SCL High Count Register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ss_scl_hcnt ss_scl_hcnt read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 count

count : COUNT
bits : 0 - 15 (16 bit)


ss_scl_lcnt

Standard Speed Clock SCL Low Count Register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ss_scl_lcnt ss_scl_lcnt read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 count

count : COUNT
bits : 0 - 15 (16 bit)


intr_stat

Interrupt Status Register
address_offset : 0x2C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

intr_stat intr_stat read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rx_under rx_over rx_full tx_over tx_empty rd_req tx_abrt rx_done activity stop_det start_det gen_call

rx_under : RX_UNDER
bits : 0 - 0 (1 bit)

rx_over : RX_OVER
bits : 1 - 2 (2 bit)

rx_full : RX_FULL
bits : 2 - 4 (3 bit)

tx_over : TX_OVER
bits : 3 - 6 (4 bit)

tx_empty : TX_EMPTY
bits : 4 - 8 (5 bit)

rd_req : RD_REQ
bits : 5 - 10 (6 bit)

tx_abrt : TX_ABRT
bits : 6 - 12 (7 bit)

rx_done : RX_DONE
bits : 7 - 14 (8 bit)

activity : ACTIVITY
bits : 8 - 16 (9 bit)

stop_det : STOP_DET
bits : 9 - 18 (10 bit)

start_det : START_DET
bits : 10 - 20 (11 bit)

gen_call : GEN_CALL
bits : 11 - 22 (12 bit)


intr_mask

Interrupt Mask Register
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

intr_mask intr_mask read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rx_under rx_over rx_full tx_over tx_empty rd_req tx_abrt rx_done activity stop_det start_det gen_call

rx_under : RX_UNDER
bits : 0 - 0 (1 bit)

rx_over : RX_OVER
bits : 1 - 2 (2 bit)

rx_full : RX_FULL
bits : 2 - 4 (3 bit)

tx_over : TX_OVER
bits : 3 - 6 (4 bit)

tx_empty : TX_EMPTY
bits : 4 - 8 (5 bit)

rd_req : RD_REQ
bits : 5 - 10 (6 bit)

tx_abrt : TX_ABRT
bits : 6 - 12 (7 bit)

rx_done : RX_DONE
bits : 7 - 14 (8 bit)

activity : ACTIVITY
bits : 8 - 16 (9 bit)

stop_det : STOP_DET
bits : 9 - 18 (10 bit)

start_det : START_DET
bits : 10 - 20 (11 bit)

gen_call : GEN_CALL
bits : 11 - 22 (12 bit)


raw_intr_stat

Raw Interrupt Status Register
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

raw_intr_stat raw_intr_stat read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rx_under rx_over rx_full tx_over tx_empty rd_req tx_abrt rx_done activity stop_det start_det gen_call

rx_under : RX_UNDER
bits : 0 - 0 (1 bit)

rx_over : RX_OVER
bits : 1 - 2 (2 bit)

rx_full : RX_FULL
bits : 2 - 4 (3 bit)

tx_over : TX_OVER
bits : 3 - 6 (4 bit)

tx_empty : TX_EMPTY
bits : 4 - 8 (5 bit)

rd_req : RD_REQ
bits : 5 - 10 (6 bit)

tx_abrt : TX_ABRT
bits : 6 - 12 (7 bit)

rx_done : RX_DONE
bits : 7 - 14 (8 bit)

activity : ACTIVITY
bits : 8 - 16 (9 bit)

stop_det : STOP_DET
bits : 9 - 18 (10 bit)

start_det : START_DET
bits : 10 - 20 (11 bit)

gen_call : GEN_CALL
bits : 11 - 22 (12 bit)


rx_tl

Receive FIFO Threshold Register
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

rx_tl rx_tl read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 value

value : VALUE
bits : 0 - 2 (3 bit)


tx_tl

Transmit FIFO Threshold Register
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

tx_tl tx_tl read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 value

value : VALUE
bits : 0 - 2 (3 bit)


tar

Target Address Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

tar tar read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 address gc special addr_master_width

address : Target Address
bits : 0 - 9 (10 bit)

gc : GC_OR_START
bits : 10 - 20 (11 bit)

special : SPECIAL
bits : 11 - 22 (12 bit)

addr_master_width : Master Address
bits : 12 - 24 (13 bit)

Enumeration:

0 : b7

7-bit address

1 : b10

10-bit address

End of enumeration elements list.


clr_intr

Clear Combined and Individual Interrupt Register
address_offset : 0x40 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

clr_intr clr_intr read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 clr

clr : CLR
bits : 0 - 0 (1 bit)


clr_rx_under

Clear RX_UNDER Interrupt Register
address_offset : 0x44 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

clr_rx_under clr_rx_under read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 clr

clr : CLR
bits : 0 - 0 (1 bit)


clr_rx_over

Clear RX_OVER Interrupt Register
address_offset : 0x48 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

clr_rx_over clr_rx_over read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 clr

clr : CLR
bits : 0 - 0 (1 bit)


clr_tx_over

Clear TX_OVER Interrupt Register
address_offset : 0x4C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

clr_tx_over clr_tx_over read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 clr

clr : CLR
bits : 0 - 0 (1 bit)


clr_rd_req

Clear RD_REQ Interrupt Register
address_offset : 0x50 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

clr_rd_req clr_rd_req read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 clr

clr : CLR
bits : 0 - 0 (1 bit)


clr_tx_abrt

Clear TX_ABRT Interrupt Register
address_offset : 0x54 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

clr_tx_abrt clr_tx_abrt read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 clr

clr : CLR
bits : 0 - 0 (1 bit)


clr_rx_done

Clear RX_DONE Interrupt Register
address_offset : 0x58 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

clr_rx_done clr_rx_done read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 clr

clr : CLR
bits : 0 - 0 (1 bit)


clr_activity

Clear ACTIVITY Interrupt Register
address_offset : 0x5C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

clr_activity clr_activity read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 clr

clr : CLR
bits : 0 - 0 (1 bit)


clr_stop_det

Clear STOP_DET Interrupt Register
address_offset : 0x60 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

clr_stop_det clr_stop_det read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 clr

clr : CLR
bits : 0 - 0 (1 bit)


clr_start_det

Clear START_DET Interrupt Register
address_offset : 0x64 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

clr_start_det clr_start_det read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 clr

clr : CLR
bits : 0 - 0 (1 bit)


clr_gen_call

I2C Clear GEN_CALL Interrupt Register
address_offset : 0x68 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

clr_gen_call clr_gen_call read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 clr

clr : CLR
bits : 0 - 0 (1 bit)


enable

Enable Register
address_offset : 0x6C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

enable enable read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 enable abort tx_cmd_block

enable : ENABLE
bits : 0 - 0 (1 bit)

abort : ABORT
bits : 1 - 2 (2 bit)

tx_cmd_block : TX_CMD_BLOCK
bits : 2 - 4 (3 bit)


status

Status Register
address_offset : 0x70 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

status status read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 activity tfnf tfe rfne rff mst_activity slv_activity

activity : ACTIVITY
bits : 0 - 0 (1 bit)

tfnf : TFNF
bits : 1 - 2 (2 bit)

tfe : TFE
bits : 2 - 4 (3 bit)

rfne : RFNE
bits : 3 - 6 (4 bit)

rff : RFF
bits : 4 - 8 (5 bit)

mst_activity : MST_ACTIVITY
bits : 5 - 10 (6 bit)

slv_activity : SLV_ACTIVITY
bits : 6 - 12 (7 bit)


txflr

Transmit FIFO Level Register
address_offset : 0x74 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

txflr txflr read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 value

value : VALUE
bits : 0 - 2 (3 bit)


rxflr

Receive FIFO Level Register
address_offset : 0x78 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

rxflr rxflr read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 value

value : VALUE
bits : 0 - 2 (3 bit)


sda_hold

SDA Hold Time Length Register
address_offset : 0x7C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

sda_hold sda_hold read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tx rx

tx : TX
bits : 0 - 15 (16 bit)

rx : RX
bits : 16 - 39 (24 bit)


sar

Slave Address Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

sar sar read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 address

address : Slave Address
bits : 0 - 9 (10 bit)


tx_abrt_source

Transmit Abort Source Register
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

tx_abrt_source tx_abrt_source read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 addr7_noack addr1_10_noack addr2_10_noack txdata_noack gcall_noack gcall_read hs_ackdet sbyte_ackdet hs_norstrt sbyte_norstrt rd_10_norstrt master_dis mst_arblost slvflush_txfifo slv_arblost slvrd_intx user_abrt

addr7_noack : 7B_ADDR_NOACK
bits : 0 - 0 (1 bit)

addr1_10_noack : 10B_ADDR1_NOACK
bits : 1 - 2 (2 bit)

addr2_10_noack : 10B_ADDR2_NOACK
bits : 2 - 4 (3 bit)

txdata_noack : TXDATA_NOACK
bits : 3 - 6 (4 bit)

gcall_noack : GCALL_NOACK
bits : 4 - 8 (5 bit)

gcall_read : GCALL_READ
bits : 5 - 10 (6 bit)

hs_ackdet : HS_ACKDET
bits : 6 - 12 (7 bit)

sbyte_ackdet : SBYTE_ACKDET
bits : 7 - 14 (8 bit)

hs_norstrt : HS_NORSTRT
bits : 8 - 16 (9 bit)

sbyte_norstrt : SBYTE_NORSTRT
bits : 9 - 18 (10 bit)

rd_10_norstrt : 10B_RD_NORSTRT
bits : 10 - 20 (11 bit)

master_dis : MASTER_DIS
bits : 11 - 22 (12 bit)

mst_arblost : MST_ARBLOST
bits : 12 - 24 (13 bit)

slvflush_txfifo : SLVFLUSH_TXFIFO
bits : 13 - 26 (14 bit)

slv_arblost : SLV_ARBLOST
bits : 14 - 28 (15 bit)

slvrd_intx : SLVRD_INTX
bits : 15 - 30 (16 bit)

user_abrt : USER_ABRT
bits : 16 - 32 (17 bit)


dma_cr

I2C DMA Control Register
address_offset : 0x88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

dma_cr dma_cr read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDMAE TDMAE

RDMAE : RDMAE
bits : 0 - 0 (1 bit)

TDMAE : TDMAE
bits : 1 - 2 (2 bit)


dma_tdlr

DMA Transmit Data Level Register
address_offset : 0x8C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

dma_tdlr dma_tdlr read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 value

value : VALUE
bits : 0 - 2 (3 bit)


dma_rdlr

DMA Receive Data Level Register
address_offset : 0x90 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

dma_rdlr dma_rdlr read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 value

value : VALUE
bits : 0 - 2 (3 bit)


sda_setup

SDA Setup Register
address_offset : 0x94 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

sda_setup sda_setup read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 value

value : VALUE
bits : 0 - 7 (8 bit)


general_call

ACK General Call Register
address_offset : 0x98 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

general_call general_call read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 call_enable

call_enable : CALL_ENABLE
bits : 0 - 0 (1 bit)


enable_status

Enable Status Register
address_offset : 0x9C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

enable_status enable_status read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ic_enable slv_dis_busy slv_rx_data_lost

ic_enable : IC_ENABLE
bits : 0 - 0 (1 bit)

slv_dis_busy : SLV_DIS_BUSY
bits : 1 - 2 (2 bit)

slv_rx_data_lost : SLV_RX_DATA_LOST
bits : 2 - 4 (3 bit)


fs_spklen

SS, FS or FM+ spike suppression limit
address_offset : 0xA0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

fs_spklen fs_spklen read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 value

value : VALUE
bits : 0 - 7 (8 bit)


comp_param_1

Component Parameter Register 1
address_offset : 0xF4 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

comp_param_1 comp_param_1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 apb_data_width max_speed_mode hc_count_values intr_io has_dma encoded_params rx_buffer_depth tx_buffer_depth

apb_data_width : APB_DATA_WIDTH
bits : 0 - 1 (2 bit)

max_speed_mode : MAX_SPEED_MODE
bits : 2 - 5 (4 bit)

hc_count_values : HC_COUNT_VALUES
bits : 4 - 8 (5 bit)

intr_io : INTR_IO
bits : 5 - 10 (6 bit)

has_dma : HAS_DMA
bits : 6 - 12 (7 bit)

encoded_params : ENCODED_PARAMS
bits : 7 - 14 (8 bit)

rx_buffer_depth : RX_BUFFER_DEPTH
bits : 8 - 23 (16 bit)

tx_buffer_depth : TX_BUFFER_DEPTH
bits : 16 - 39 (24 bit)


comp_version

Component Version Register
address_offset : 0xF8 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

comp_version comp_version read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 value

value : VALUE
bits : 0 - 31 (32 bit)


comp_type

Component Type Register
address_offset : 0xFC Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

comp_type comp_type read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 value

value : VALUE
bits : 0 - 31 (32 bit)



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