\n
Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
master_mode : Master Mode
bits : 0 - 0 (1 bit)
speed : Speed
bits : 1 - 3 (3 bit)
Enumeration:
0 : standard
STANDARD
1 : fast
FAST
2 : highspeed
HIGHSPEED
End of enumeration elements list.
addr_slave_width : Slave address width
bits : 3 - 6 (4 bit)
Enumeration:
0 : b7
7-bit address
1 : b10
10-bit address
End of enumeration elements list.
restart_en : Enable Restart
bits : 5 - 10 (6 bit)
slave_disable : Disable Slave
bits : 6 - 12 (7 bit)
stop_det : STOP_DET_IFADDRESSED
bits : 7 - 14 (8 bit)
tx_empty : TX_EMPTY_CTRL
bits : 8 - 16 (9 bit)
Data Buffer and Command Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Data
bits : 0 - 7 (8 bit)
cmd : CMD
bits : 8 - 16 (9 bit)
Standard Speed Clock SCL High Count Register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
count : COUNT
bits : 0 - 15 (16 bit)
Standard Speed Clock SCL Low Count Register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
count : COUNT
bits : 0 - 15 (16 bit)
Interrupt Status Register
address_offset : 0x2C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
rx_under : RX_UNDER
bits : 0 - 0 (1 bit)
rx_over : RX_OVER
bits : 1 - 2 (2 bit)
rx_full : RX_FULL
bits : 2 - 4 (3 bit)
tx_over : TX_OVER
bits : 3 - 6 (4 bit)
tx_empty : TX_EMPTY
bits : 4 - 8 (5 bit)
rd_req : RD_REQ
bits : 5 - 10 (6 bit)
tx_abrt : TX_ABRT
bits : 6 - 12 (7 bit)
rx_done : RX_DONE
bits : 7 - 14 (8 bit)
activity : ACTIVITY
bits : 8 - 16 (9 bit)
stop_det : STOP_DET
bits : 9 - 18 (10 bit)
start_det : START_DET
bits : 10 - 20 (11 bit)
gen_call : GEN_CALL
bits : 11 - 22 (12 bit)
Interrupt Mask Register
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
rx_under : RX_UNDER
bits : 0 - 0 (1 bit)
rx_over : RX_OVER
bits : 1 - 2 (2 bit)
rx_full : RX_FULL
bits : 2 - 4 (3 bit)
tx_over : TX_OVER
bits : 3 - 6 (4 bit)
tx_empty : TX_EMPTY
bits : 4 - 8 (5 bit)
rd_req : RD_REQ
bits : 5 - 10 (6 bit)
tx_abrt : TX_ABRT
bits : 6 - 12 (7 bit)
rx_done : RX_DONE
bits : 7 - 14 (8 bit)
activity : ACTIVITY
bits : 8 - 16 (9 bit)
stop_det : STOP_DET
bits : 9 - 18 (10 bit)
start_det : START_DET
bits : 10 - 20 (11 bit)
gen_call : GEN_CALL
bits : 11 - 22 (12 bit)
Raw Interrupt Status Register
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
rx_under : RX_UNDER
bits : 0 - 0 (1 bit)
rx_over : RX_OVER
bits : 1 - 2 (2 bit)
rx_full : RX_FULL
bits : 2 - 4 (3 bit)
tx_over : TX_OVER
bits : 3 - 6 (4 bit)
tx_empty : TX_EMPTY
bits : 4 - 8 (5 bit)
rd_req : RD_REQ
bits : 5 - 10 (6 bit)
tx_abrt : TX_ABRT
bits : 6 - 12 (7 bit)
rx_done : RX_DONE
bits : 7 - 14 (8 bit)
activity : ACTIVITY
bits : 8 - 16 (9 bit)
stop_det : STOP_DET
bits : 9 - 18 (10 bit)
start_det : START_DET
bits : 10 - 20 (11 bit)
gen_call : GEN_CALL
bits : 11 - 22 (12 bit)
Receive FIFO Threshold Register
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
value : VALUE
bits : 0 - 2 (3 bit)
Transmit FIFO Threshold Register
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
value : VALUE
bits : 0 - 2 (3 bit)
Target Address Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
address : Target Address
bits : 0 - 9 (10 bit)
gc : GC_OR_START
bits : 10 - 20 (11 bit)
special : SPECIAL
bits : 11 - 22 (12 bit)
addr_master_width : Master Address
bits : 12 - 24 (13 bit)
Enumeration:
0 : b7
7-bit address
1 : b10
10-bit address
End of enumeration elements list.
Clear Combined and Individual Interrupt Register
address_offset : 0x40 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
clr : CLR
bits : 0 - 0 (1 bit)
Clear RX_UNDER Interrupt Register
address_offset : 0x44 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
clr : CLR
bits : 0 - 0 (1 bit)
Clear RX_OVER Interrupt Register
address_offset : 0x48 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
clr : CLR
bits : 0 - 0 (1 bit)
Clear TX_OVER Interrupt Register
address_offset : 0x4C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
clr : CLR
bits : 0 - 0 (1 bit)
Clear RD_REQ Interrupt Register
address_offset : 0x50 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
clr : CLR
bits : 0 - 0 (1 bit)
Clear TX_ABRT Interrupt Register
address_offset : 0x54 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
clr : CLR
bits : 0 - 0 (1 bit)
Clear RX_DONE Interrupt Register
address_offset : 0x58 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
clr : CLR
bits : 0 - 0 (1 bit)
Clear ACTIVITY Interrupt Register
address_offset : 0x5C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
clr : CLR
bits : 0 - 0 (1 bit)
Clear STOP_DET Interrupt Register
address_offset : 0x60 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
clr : CLR
bits : 0 - 0 (1 bit)
Clear START_DET Interrupt Register
address_offset : 0x64 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
clr : CLR
bits : 0 - 0 (1 bit)
I2C Clear GEN_CALL Interrupt Register
address_offset : 0x68 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
clr : CLR
bits : 0 - 0 (1 bit)
Enable Register
address_offset : 0x6C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
enable : ENABLE
bits : 0 - 0 (1 bit)
abort : ABORT
bits : 1 - 2 (2 bit)
tx_cmd_block : TX_CMD_BLOCK
bits : 2 - 4 (3 bit)
Status Register
address_offset : 0x70 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
activity : ACTIVITY
bits : 0 - 0 (1 bit)
tfnf : TFNF
bits : 1 - 2 (2 bit)
tfe : TFE
bits : 2 - 4 (3 bit)
rfne : RFNE
bits : 3 - 6 (4 bit)
rff : RFF
bits : 4 - 8 (5 bit)
mst_activity : MST_ACTIVITY
bits : 5 - 10 (6 bit)
slv_activity : SLV_ACTIVITY
bits : 6 - 12 (7 bit)
Transmit FIFO Level Register
address_offset : 0x74 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
value : VALUE
bits : 0 - 2 (3 bit)
Receive FIFO Level Register
address_offset : 0x78 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
value : VALUE
bits : 0 - 2 (3 bit)
SDA Hold Time Length Register
address_offset : 0x7C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
tx : TX
bits : 0 - 15 (16 bit)
rx : RX
bits : 16 - 39 (24 bit)
Slave Address Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
address : Slave Address
bits : 0 - 9 (10 bit)
Transmit Abort Source Register
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
addr7_noack : 7B_ADDR_NOACK
bits : 0 - 0 (1 bit)
addr1_10_noack : 10B_ADDR1_NOACK
bits : 1 - 2 (2 bit)
addr2_10_noack : 10B_ADDR2_NOACK
bits : 2 - 4 (3 bit)
txdata_noack : TXDATA_NOACK
bits : 3 - 6 (4 bit)
gcall_noack : GCALL_NOACK
bits : 4 - 8 (5 bit)
gcall_read : GCALL_READ
bits : 5 - 10 (6 bit)
hs_ackdet : HS_ACKDET
bits : 6 - 12 (7 bit)
sbyte_ackdet : SBYTE_ACKDET
bits : 7 - 14 (8 bit)
hs_norstrt : HS_NORSTRT
bits : 8 - 16 (9 bit)
sbyte_norstrt : SBYTE_NORSTRT
bits : 9 - 18 (10 bit)
rd_10_norstrt : 10B_RD_NORSTRT
bits : 10 - 20 (11 bit)
master_dis : MASTER_DIS
bits : 11 - 22 (12 bit)
mst_arblost : MST_ARBLOST
bits : 12 - 24 (13 bit)
slvflush_txfifo : SLVFLUSH_TXFIFO
bits : 13 - 26 (14 bit)
slv_arblost : SLV_ARBLOST
bits : 14 - 28 (15 bit)
slvrd_intx : SLVRD_INTX
bits : 15 - 30 (16 bit)
user_abrt : USER_ABRT
bits : 16 - 32 (17 bit)
I2C DMA Control Register
address_offset : 0x88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDMAE : RDMAE
bits : 0 - 0 (1 bit)
TDMAE : TDMAE
bits : 1 - 2 (2 bit)
DMA Transmit Data Level Register
address_offset : 0x8C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
value : VALUE
bits : 0 - 2 (3 bit)
DMA Receive Data Level Register
address_offset : 0x90 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
value : VALUE
bits : 0 - 2 (3 bit)
SDA Setup Register
address_offset : 0x94 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
value : VALUE
bits : 0 - 7 (8 bit)
ACK General Call Register
address_offset : 0x98 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
call_enable : CALL_ENABLE
bits : 0 - 0 (1 bit)
Enable Status Register
address_offset : 0x9C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ic_enable : IC_ENABLE
bits : 0 - 0 (1 bit)
slv_dis_busy : SLV_DIS_BUSY
bits : 1 - 2 (2 bit)
slv_rx_data_lost : SLV_RX_DATA_LOST
bits : 2 - 4 (3 bit)
SS, FS or FM+ spike suppression limit
address_offset : 0xA0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
value : VALUE
bits : 0 - 7 (8 bit)
Component Parameter Register 1
address_offset : 0xF4 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
apb_data_width : APB_DATA_WIDTH
bits : 0 - 1 (2 bit)
max_speed_mode : MAX_SPEED_MODE
bits : 2 - 5 (4 bit)
hc_count_values : HC_COUNT_VALUES
bits : 4 - 8 (5 bit)
intr_io : INTR_IO
bits : 5 - 10 (6 bit)
has_dma : HAS_DMA
bits : 6 - 12 (7 bit)
encoded_params : ENCODED_PARAMS
bits : 7 - 14 (8 bit)
rx_buffer_depth : RX_BUFFER_DEPTH
bits : 8 - 23 (16 bit)
tx_buffer_depth : TX_BUFFER_DEPTH
bits : 16 - 39 (24 bit)
Component Version Register
address_offset : 0xF8 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
value : VALUE
bits : 0 - 31 (32 bit)
Component Type Register
address_offset : 0xFC Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
value : VALUE
bits : 0 - 31 (32 bit)
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