\n
FPIOA GPIO multiplexer io array
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)
ds : Driving selector
bits : 8 - 19 (12 bit)
oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)
oe_inv : Invert output enable
bits : 13 - 26 (14 bit)
do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)
do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)
pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)
pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)
sl : Slew rate control enable
bits : 19 - 38 (20 bit)
ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)
ie_inv : Invert input enable
bits : 21 - 42 (22 bit)
di_inv : Invert Data input
bits : 22 - 44 (23 bit)
st : Schmitt trigger
bits : 23 - 46 (24 bit)
pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)
FPIOA GPIO multiplexer io array
address_offset : 0x102C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)
ds : Driving selector
bits : 8 - 19 (12 bit)
oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)
oe_inv : Invert output enable
bits : 13 - 26 (14 bit)
do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)
do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)
pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)
pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)
sl : Slew rate control enable
bits : 19 - 38 (20 bit)
ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)
ie_inv : Invert input enable
bits : 21 - 42 (22 bit)
di_inv : Invert Data input
bits : 22 - 44 (23 bit)
st : Schmitt trigger
bits : 23 - 46 (24 bit)
pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)
FPIOA GPIO multiplexer io array
address_offset : 0x108 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)
ds : Driving selector
bits : 8 - 19 (12 bit)
oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)
oe_inv : Invert output enable
bits : 13 - 26 (14 bit)
do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)
do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)
pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)
pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)
sl : Slew rate control enable
bits : 19 - 38 (20 bit)
ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)
ie_inv : Invert input enable
bits : 21 - 42 (22 bit)
di_inv : Invert Data input
bits : 22 - 44 (23 bit)
st : Schmitt trigger
bits : 23 - 46 (24 bit)
pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)
FPIOA GPIO multiplexer io array
address_offset : 0x10E4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)
ds : Driving selector
bits : 8 - 19 (12 bit)
oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)
oe_inv : Invert output enable
bits : 13 - 26 (14 bit)
do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)
do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)
pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)
pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)
sl : Slew rate control enable
bits : 19 - 38 (20 bit)
ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)
ie_inv : Invert input enable
bits : 21 - 42 (22 bit)
di_inv : Invert Data input
bits : 22 - 44 (23 bit)
st : Schmitt trigger
bits : 23 - 46 (24 bit)
pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)
FPIOA GPIO multiplexer io array
address_offset : 0x11A0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)
ds : Driving selector
bits : 8 - 19 (12 bit)
oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)
oe_inv : Invert output enable
bits : 13 - 26 (14 bit)
do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)
do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)
pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)
pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)
sl : Slew rate control enable
bits : 19 - 38 (20 bit)
ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)
ie_inv : Invert input enable
bits : 21 - 42 (22 bit)
di_inv : Invert Data input
bits : 22 - 44 (23 bit)
st : Schmitt trigger
bits : 23 - 46 (24 bit)
pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)
FPIOA GPIO multiplexer io array
address_offset : 0x138 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)
ds : Driving selector
bits : 8 - 19 (12 bit)
oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)
oe_inv : Invert output enable
bits : 13 - 26 (14 bit)
do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)
do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)
pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)
pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)
sl : Slew rate control enable
bits : 19 - 38 (20 bit)
ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)
ie_inv : Invert input enable
bits : 21 - 42 (22 bit)
di_inv : Invert Data input
bits : 22 - 44 (23 bit)
st : Schmitt trigger
bits : 23 - 46 (24 bit)
pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)
FPIOA GPIO multiplexer io array
address_offset : 0x16C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)
ds : Driving selector
bits : 8 - 19 (12 bit)
oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)
oe_inv : Invert output enable
bits : 13 - 26 (14 bit)
do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)
do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)
pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)
pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)
sl : Slew rate control enable
bits : 19 - 38 (20 bit)
ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)
ie_inv : Invert input enable
bits : 21 - 42 (22 bit)
di_inv : Invert Data input
bits : 22 - 44 (23 bit)
st : Schmitt trigger
bits : 23 - 46 (24 bit)
pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)
FPIOA GPIO multiplexer io array
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)
ds : Driving selector
bits : 8 - 19 (12 bit)
oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)
oe_inv : Invert output enable
bits : 13 - 26 (14 bit)
do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)
do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)
pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)
pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)
sl : Slew rate control enable
bits : 19 - 38 (20 bit)
ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)
ie_inv : Invert input enable
bits : 21 - 42 (22 bit)
di_inv : Invert Data input
bits : 22 - 44 (23 bit)
st : Schmitt trigger
bits : 23 - 46 (24 bit)
pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)
FPIOA GPIO multiplexer tie enable array
address_offset : 0x180 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FPIOA GPIO multiplexer io array
address_offset : 0x1A4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)
ds : Driving selector
bits : 8 - 19 (12 bit)
oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)
oe_inv : Invert output enable
bits : 13 - 26 (14 bit)
do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)
do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)
pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)
pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)
sl : Slew rate control enable
bits : 19 - 38 (20 bit)
ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)
ie_inv : Invert input enable
bits : 21 - 42 (22 bit)
di_inv : Invert Data input
bits : 22 - 44 (23 bit)
st : Schmitt trigger
bits : 23 - 46 (24 bit)
pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)
FPIOA GPIO multiplexer tie value array
address_offset : 0x1C0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FPIOA GPIO multiplexer io array
address_offset : 0x1E0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)
ds : Driving selector
bits : 8 - 19 (12 bit)
oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)
oe_inv : Invert output enable
bits : 13 - 26 (14 bit)
do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)
do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)
pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)
pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)
sl : Slew rate control enable
bits : 19 - 38 (20 bit)
ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)
ie_inv : Invert input enable
bits : 21 - 42 (22 bit)
di_inv : Invert Data input
bits : 22 - 44 (23 bit)
st : Schmitt trigger
bits : 23 - 46 (24 bit)
pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)
FPIOA GPIO multiplexer io array
address_offset : 0x220 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)
ds : Driving selector
bits : 8 - 19 (12 bit)
oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)
oe_inv : Invert output enable
bits : 13 - 26 (14 bit)
do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)
do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)
pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)
pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)
sl : Slew rate control enable
bits : 19 - 38 (20 bit)
ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)
ie_inv : Invert input enable
bits : 21 - 42 (22 bit)
di_inv : Invert Data input
bits : 22 - 44 (23 bit)
st : Schmitt trigger
bits : 23 - 46 (24 bit)
pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)
FPIOA GPIO multiplexer tie enable array
address_offset : 0x244 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FPIOA GPIO multiplexer io array
address_offset : 0x264 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)
ds : Driving selector
bits : 8 - 19 (12 bit)
oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)
oe_inv : Invert output enable
bits : 13 - 26 (14 bit)
do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)
do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)
pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)
pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)
sl : Slew rate control enable
bits : 19 - 38 (20 bit)
ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)
ie_inv : Invert input enable
bits : 21 - 42 (22 bit)
di_inv : Invert Data input
bits : 22 - 44 (23 bit)
st : Schmitt trigger
bits : 23 - 46 (24 bit)
pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)
FPIOA GPIO multiplexer io array
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)
ds : Driving selector
bits : 8 - 19 (12 bit)
oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)
oe_inv : Invert output enable
bits : 13 - 26 (14 bit)
do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)
do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)
pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)
pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)
sl : Slew rate control enable
bits : 19 - 38 (20 bit)
ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)
ie_inv : Invert input enable
bits : 21 - 42 (22 bit)
di_inv : Invert Data input
bits : 22 - 44 (23 bit)
st : Schmitt trigger
bits : 23 - 46 (24 bit)
pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)
FPIOA GPIO multiplexer tie value array
address_offset : 0x2A4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FPIOA GPIO multiplexer io array
address_offset : 0x2AC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)
ds : Driving selector
bits : 8 - 19 (12 bit)
oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)
oe_inv : Invert output enable
bits : 13 - 26 (14 bit)
do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)
do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)
pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)
pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)
sl : Slew rate control enable
bits : 19 - 38 (20 bit)
ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)
ie_inv : Invert input enable
bits : 21 - 42 (22 bit)
di_inv : Invert Data input
bits : 22 - 44 (23 bit)
st : Schmitt trigger
bits : 23 - 46 (24 bit)
pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)
FPIOA GPIO multiplexer io array
address_offset : 0x2F8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)
ds : Driving selector
bits : 8 - 19 (12 bit)
oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)
oe_inv : Invert output enable
bits : 13 - 26 (14 bit)
do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)
do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)
pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)
pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)
sl : Slew rate control enable
bits : 19 - 38 (20 bit)
ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)
ie_inv : Invert input enable
bits : 21 - 42 (22 bit)
di_inv : Invert Data input
bits : 22 - 44 (23 bit)
st : Schmitt trigger
bits : 23 - 46 (24 bit)
pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)
FPIOA GPIO multiplexer tie enable array
address_offset : 0x30C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FPIOA GPIO multiplexer io array
address_offset : 0x348 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)
ds : Driving selector
bits : 8 - 19 (12 bit)
oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)
oe_inv : Invert output enable
bits : 13 - 26 (14 bit)
do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)
do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)
pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)
pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)
sl : Slew rate control enable
bits : 19 - 38 (20 bit)
ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)
ie_inv : Invert input enable
bits : 21 - 42 (22 bit)
di_inv : Invert Data input
bits : 22 - 44 (23 bit)
st : Schmitt trigger
bits : 23 - 46 (24 bit)
pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)
FPIOA GPIO multiplexer tie value array
address_offset : 0x38C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FPIOA GPIO multiplexer io array
address_offset : 0x39C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)
ds : Driving selector
bits : 8 - 19 (12 bit)
oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)
oe_inv : Invert output enable
bits : 13 - 26 (14 bit)
do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)
do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)
pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)
pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)
sl : Slew rate control enable
bits : 19 - 38 (20 bit)
ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)
ie_inv : Invert input enable
bits : 21 - 42 (22 bit)
di_inv : Invert Data input
bits : 22 - 44 (23 bit)
st : Schmitt trigger
bits : 23 - 46 (24 bit)
pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)
FPIOA GPIO multiplexer io array
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)
ds : Driving selector
bits : 8 - 19 (12 bit)
oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)
oe_inv : Invert output enable
bits : 13 - 26 (14 bit)
do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)
do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)
pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)
pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)
sl : Slew rate control enable
bits : 19 - 38 (20 bit)
ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)
ie_inv : Invert input enable
bits : 21 - 42 (22 bit)
di_inv : Invert Data input
bits : 22 - 44 (23 bit)
st : Schmitt trigger
bits : 23 - 46 (24 bit)
pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)
FPIOA GPIO multiplexer tie enable array
address_offset : 0x3D8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FPIOA GPIO multiplexer io array
address_offset : 0x3F4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)
ds : Driving selector
bits : 8 - 19 (12 bit)
oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)
oe_inv : Invert output enable
bits : 13 - 26 (14 bit)
do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)
do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)
pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)
pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)
sl : Slew rate control enable
bits : 19 - 38 (20 bit)
ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)
ie_inv : Invert input enable
bits : 21 - 42 (22 bit)
di_inv : Invert Data input
bits : 22 - 44 (23 bit)
st : Schmitt trigger
bits : 23 - 46 (24 bit)
pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)
FPIOA GPIO multiplexer io array
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)
ds : Driving selector
bits : 8 - 19 (12 bit)
oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)
oe_inv : Invert output enable
bits : 13 - 26 (14 bit)
do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)
do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)
pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)
pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)
sl : Slew rate control enable
bits : 19 - 38 (20 bit)
ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)
ie_inv : Invert input enable
bits : 21 - 42 (22 bit)
di_inv : Invert Data input
bits : 22 - 44 (23 bit)
st : Schmitt trigger
bits : 23 - 46 (24 bit)
pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)
FPIOA GPIO multiplexer io array
address_offset : 0x450 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)
ds : Driving selector
bits : 8 - 19 (12 bit)
oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)
oe_inv : Invert output enable
bits : 13 - 26 (14 bit)
do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)
do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)
pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)
pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)
sl : Slew rate control enable
bits : 19 - 38 (20 bit)
ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)
ie_inv : Invert input enable
bits : 21 - 42 (22 bit)
di_inv : Invert Data input
bits : 22 - 44 (23 bit)
st : Schmitt trigger
bits : 23 - 46 (24 bit)
pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)
FPIOA GPIO multiplexer tie value array
address_offset : 0x478 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FPIOA GPIO multiplexer tie enable array
address_offset : 0x4A8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FPIOA GPIO multiplexer io array
address_offset : 0x4B0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)
ds : Driving selector
bits : 8 - 19 (12 bit)
oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)
oe_inv : Invert output enable
bits : 13 - 26 (14 bit)
do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)
do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)
pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)
pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)
sl : Slew rate control enable
bits : 19 - 38 (20 bit)
ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)
ie_inv : Invert input enable
bits : 21 - 42 (22 bit)
di_inv : Invert Data input
bits : 22 - 44 (23 bit)
st : Schmitt trigger
bits : 23 - 46 (24 bit)
pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)
FPIOA GPIO multiplexer io array
address_offset : 0x514 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)
ds : Driving selector
bits : 8 - 19 (12 bit)
oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)
oe_inv : Invert output enable
bits : 13 - 26 (14 bit)
do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)
do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)
pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)
pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)
sl : Slew rate control enable
bits : 19 - 38 (20 bit)
ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)
ie_inv : Invert input enable
bits : 21 - 42 (22 bit)
di_inv : Invert Data input
bits : 22 - 44 (23 bit)
st : Schmitt trigger
bits : 23 - 46 (24 bit)
pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)
FPIOA GPIO multiplexer io array
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)
ds : Driving selector
bits : 8 - 19 (12 bit)
oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)
oe_inv : Invert output enable
bits : 13 - 26 (14 bit)
do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)
do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)
pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)
pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)
sl : Slew rate control enable
bits : 19 - 38 (20 bit)
ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)
ie_inv : Invert input enable
bits : 21 - 42 (22 bit)
di_inv : Invert Data input
bits : 22 - 44 (23 bit)
st : Schmitt trigger
bits : 23 - 46 (24 bit)
pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)
FPIOA GPIO multiplexer tie value array
address_offset : 0x568 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FPIOA GPIO multiplexer io array
address_offset : 0x57C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)
ds : Driving selector
bits : 8 - 19 (12 bit)
oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)
oe_inv : Invert output enable
bits : 13 - 26 (14 bit)
do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)
do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)
pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)
pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)
sl : Slew rate control enable
bits : 19 - 38 (20 bit)
ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)
ie_inv : Invert input enable
bits : 21 - 42 (22 bit)
di_inv : Invert Data input
bits : 22 - 44 (23 bit)
st : Schmitt trigger
bits : 23 - 46 (24 bit)
pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)
FPIOA GPIO multiplexer tie enable array
address_offset : 0x57C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FPIOA GPIO multiplexer io array
address_offset : 0x5E8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)
ds : Driving selector
bits : 8 - 19 (12 bit)
oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)
oe_inv : Invert output enable
bits : 13 - 26 (14 bit)
do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)
do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)
pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)
pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)
sl : Slew rate control enable
bits : 19 - 38 (20 bit)
ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)
ie_inv : Invert input enable
bits : 21 - 42 (22 bit)
di_inv : Invert Data input
bits : 22 - 44 (23 bit)
st : Schmitt trigger
bits : 23 - 46 (24 bit)
pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)
FPIOA GPIO multiplexer tie enable array
address_offset : 0x654 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FPIOA GPIO multiplexer io array
address_offset : 0x658 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)
ds : Driving selector
bits : 8 - 19 (12 bit)
oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)
oe_inv : Invert output enable
bits : 13 - 26 (14 bit)
do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)
do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)
pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)
pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)
sl : Slew rate control enable
bits : 19 - 38 (20 bit)
ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)
ie_inv : Invert input enable
bits : 21 - 42 (22 bit)
di_inv : Invert Data input
bits : 22 - 44 (23 bit)
st : Schmitt trigger
bits : 23 - 46 (24 bit)
pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)
FPIOA GPIO multiplexer tie value array
address_offset : 0x65C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FPIOA GPIO multiplexer io array
address_offset : 0x6CC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)
ds : Driving selector
bits : 8 - 19 (12 bit)
oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)
oe_inv : Invert output enable
bits : 13 - 26 (14 bit)
do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)
do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)
pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)
pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)
sl : Slew rate control enable
bits : 19 - 38 (20 bit)
ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)
ie_inv : Invert input enable
bits : 21 - 42 (22 bit)
di_inv : Invert Data input
bits : 22 - 44 (23 bit)
st : Schmitt trigger
bits : 23 - 46 (24 bit)
pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)
FPIOA GPIO multiplexer io array
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)
ds : Driving selector
bits : 8 - 19 (12 bit)
oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)
oe_inv : Invert output enable
bits : 13 - 26 (14 bit)
do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)
do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)
pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)
pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)
sl : Slew rate control enable
bits : 19 - 38 (20 bit)
ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)
ie_inv : Invert input enable
bits : 21 - 42 (22 bit)
di_inv : Invert Data input
bits : 22 - 44 (23 bit)
st : Schmitt trigger
bits : 23 - 46 (24 bit)
pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)
FPIOA GPIO multiplexer tie enable array
address_offset : 0x730 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FPIOA GPIO multiplexer io array
address_offset : 0x744 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)
ds : Driving selector
bits : 8 - 19 (12 bit)
oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)
oe_inv : Invert output enable
bits : 13 - 26 (14 bit)
do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)
do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)
pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)
pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)
sl : Slew rate control enable
bits : 19 - 38 (20 bit)
ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)
ie_inv : Invert input enable
bits : 21 - 42 (22 bit)
di_inv : Invert Data input
bits : 22 - 44 (23 bit)
st : Schmitt trigger
bits : 23 - 46 (24 bit)
pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)
FPIOA GPIO multiplexer tie value array
address_offset : 0x754 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FPIOA GPIO multiplexer io array
address_offset : 0x7C0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)
ds : Driving selector
bits : 8 - 19 (12 bit)
oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)
oe_inv : Invert output enable
bits : 13 - 26 (14 bit)
do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)
do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)
pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)
pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)
sl : Slew rate control enable
bits : 19 - 38 (20 bit)
ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)
ie_inv : Invert input enable
bits : 21 - 42 (22 bit)
di_inv : Invert Data input
bits : 22 - 44 (23 bit)
st : Schmitt trigger
bits : 23 - 46 (24 bit)
pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)
FPIOA GPIO multiplexer io array
address_offset : 0x840 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)
ds : Driving selector
bits : 8 - 19 (12 bit)
oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)
oe_inv : Invert output enable
bits : 13 - 26 (14 bit)
do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)
do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)
pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)
pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)
sl : Slew rate control enable
bits : 19 - 38 (20 bit)
ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)
ie_inv : Invert input enable
bits : 21 - 42 (22 bit)
di_inv : Invert Data input
bits : 22 - 44 (23 bit)
st : Schmitt trigger
bits : 23 - 46 (24 bit)
pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)
FPIOA GPIO multiplexer tie value array
address_offset : 0x850 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FPIOA GPIO multiplexer io array
address_offset : 0x8C4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)
ds : Driving selector
bits : 8 - 19 (12 bit)
oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)
oe_inv : Invert output enable
bits : 13 - 26 (14 bit)
do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)
do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)
pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)
pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)
sl : Slew rate control enable
bits : 19 - 38 (20 bit)
ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)
ie_inv : Invert input enable
bits : 21 - 42 (22 bit)
di_inv : Invert Data input
bits : 22 - 44 (23 bit)
st : Schmitt trigger
bits : 23 - 46 (24 bit)
pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)
FPIOA GPIO multiplexer io array
address_offset : 0x90 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)
ds : Driving selector
bits : 8 - 19 (12 bit)
oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)
oe_inv : Invert output enable
bits : 13 - 26 (14 bit)
do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)
do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)
pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)
pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)
sl : Slew rate control enable
bits : 19 - 38 (20 bit)
ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)
ie_inv : Invert input enable
bits : 21 - 42 (22 bit)
di_inv : Invert Data input
bits : 22 - 44 (23 bit)
st : Schmitt trigger
bits : 23 - 46 (24 bit)
pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)
FPIOA GPIO multiplexer io array
address_offset : 0x94C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)
ds : Driving selector
bits : 8 - 19 (12 bit)
oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)
oe_inv : Invert output enable
bits : 13 - 26 (14 bit)
do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)
do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)
pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)
pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)
sl : Slew rate control enable
bits : 19 - 38 (20 bit)
ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)
ie_inv : Invert input enable
bits : 21 - 42 (22 bit)
di_inv : Invert Data input
bits : 22 - 44 (23 bit)
st : Schmitt trigger
bits : 23 - 46 (24 bit)
pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)
FPIOA GPIO multiplexer io array
address_offset : 0x9D8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)
ds : Driving selector
bits : 8 - 19 (12 bit)
oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)
oe_inv : Invert output enable
bits : 13 - 26 (14 bit)
do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)
do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)
pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)
pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)
sl : Slew rate control enable
bits : 19 - 38 (20 bit)
ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)
ie_inv : Invert input enable
bits : 21 - 42 (22 bit)
di_inv : Invert Data input
bits : 22 - 44 (23 bit)
st : Schmitt trigger
bits : 23 - 46 (24 bit)
pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)
FPIOA GPIO multiplexer io array
address_offset : 0xA68 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)
ds : Driving selector
bits : 8 - 19 (12 bit)
oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)
oe_inv : Invert output enable
bits : 13 - 26 (14 bit)
do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)
do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)
pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)
pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)
sl : Slew rate control enable
bits : 19 - 38 (20 bit)
ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)
ie_inv : Invert input enable
bits : 21 - 42 (22 bit)
di_inv : Invert Data input
bits : 22 - 44 (23 bit)
st : Schmitt trigger
bits : 23 - 46 (24 bit)
pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)
FPIOA GPIO multiplexer io array
address_offset : 0xAFC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)
ds : Driving selector
bits : 8 - 19 (12 bit)
oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)
oe_inv : Invert output enable
bits : 13 - 26 (14 bit)
do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)
do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)
pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)
pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)
sl : Slew rate control enable
bits : 19 - 38 (20 bit)
ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)
ie_inv : Invert input enable
bits : 21 - 42 (22 bit)
di_inv : Invert Data input
bits : 22 - 44 (23 bit)
st : Schmitt trigger
bits : 23 - 46 (24 bit)
pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)
FPIOA GPIO multiplexer io array
address_offset : 0xB4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)
ds : Driving selector
bits : 8 - 19 (12 bit)
oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)
oe_inv : Invert output enable
bits : 13 - 26 (14 bit)
do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)
do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)
pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)
pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)
sl : Slew rate control enable
bits : 19 - 38 (20 bit)
ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)
ie_inv : Invert input enable
bits : 21 - 42 (22 bit)
di_inv : Invert Data input
bits : 22 - 44 (23 bit)
st : Schmitt trigger
bits : 23 - 46 (24 bit)
pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)
FPIOA GPIO multiplexer io array
address_offset : 0xB94 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)
ds : Driving selector
bits : 8 - 19 (12 bit)
oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)
oe_inv : Invert output enable
bits : 13 - 26 (14 bit)
do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)
do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)
pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)
pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)
sl : Slew rate control enable
bits : 19 - 38 (20 bit)
ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)
ie_inv : Invert input enable
bits : 21 - 42 (22 bit)
di_inv : Invert Data input
bits : 22 - 44 (23 bit)
st : Schmitt trigger
bits : 23 - 46 (24 bit)
pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)
FPIOA GPIO multiplexer io array
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)
ds : Driving selector
bits : 8 - 19 (12 bit)
oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)
oe_inv : Invert output enable
bits : 13 - 26 (14 bit)
do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)
do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)
pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)
pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)
sl : Slew rate control enable
bits : 19 - 38 (20 bit)
ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)
ie_inv : Invert input enable
bits : 21 - 42 (22 bit)
di_inv : Invert Data input
bits : 22 - 44 (23 bit)
st : Schmitt trigger
bits : 23 - 46 (24 bit)
pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)
FPIOA GPIO multiplexer io array
address_offset : 0xC30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)
ds : Driving selector
bits : 8 - 19 (12 bit)
oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)
oe_inv : Invert output enable
bits : 13 - 26 (14 bit)
do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)
do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)
pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)
pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)
sl : Slew rate control enable
bits : 19 - 38 (20 bit)
ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)
ie_inv : Invert input enable
bits : 21 - 42 (22 bit)
di_inv : Invert Data input
bits : 22 - 44 (23 bit)
st : Schmitt trigger
bits : 23 - 46 (24 bit)
pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)
FPIOA GPIO multiplexer io array
address_offset : 0xCD0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)
ds : Driving selector
bits : 8 - 19 (12 bit)
oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)
oe_inv : Invert output enable
bits : 13 - 26 (14 bit)
do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)
do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)
pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)
pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)
sl : Slew rate control enable
bits : 19 - 38 (20 bit)
ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)
ie_inv : Invert input enable
bits : 21 - 42 (22 bit)
di_inv : Invert Data input
bits : 22 - 44 (23 bit)
st : Schmitt trigger
bits : 23 - 46 (24 bit)
pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)
FPIOA GPIO multiplexer io array
address_offset : 0xD74 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)
ds : Driving selector
bits : 8 - 19 (12 bit)
oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)
oe_inv : Invert output enable
bits : 13 - 26 (14 bit)
do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)
do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)
pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)
pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)
sl : Slew rate control enable
bits : 19 - 38 (20 bit)
ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)
ie_inv : Invert input enable
bits : 21 - 42 (22 bit)
di_inv : Invert Data input
bits : 22 - 44 (23 bit)
st : Schmitt trigger
bits : 23 - 46 (24 bit)
pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)
FPIOA GPIO multiplexer io array
address_offset : 0xDC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)
ds : Driving selector
bits : 8 - 19 (12 bit)
oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)
oe_inv : Invert output enable
bits : 13 - 26 (14 bit)
do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)
do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)
pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)
pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)
sl : Slew rate control enable
bits : 19 - 38 (20 bit)
ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)
ie_inv : Invert input enable
bits : 21 - 42 (22 bit)
di_inv : Invert Data input
bits : 22 - 44 (23 bit)
st : Schmitt trigger
bits : 23 - 46 (24 bit)
pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)
FPIOA GPIO multiplexer io array
address_offset : 0xE1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)
ds : Driving selector
bits : 8 - 19 (12 bit)
oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)
oe_inv : Invert output enable
bits : 13 - 26 (14 bit)
do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)
do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)
pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)
pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)
sl : Slew rate control enable
bits : 19 - 38 (20 bit)
ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)
ie_inv : Invert input enable
bits : 21 - 42 (22 bit)
di_inv : Invert Data input
bits : 22 - 44 (23 bit)
st : Schmitt trigger
bits : 23 - 46 (24 bit)
pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)
FPIOA GPIO multiplexer io array
address_offset : 0xEC8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)
ds : Driving selector
bits : 8 - 19 (12 bit)
oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)
oe_inv : Invert output enable
bits : 13 - 26 (14 bit)
do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)
do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)
pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)
pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)
sl : Slew rate control enable
bits : 19 - 38 (20 bit)
ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)
ie_inv : Invert input enable
bits : 21 - 42 (22 bit)
di_inv : Invert Data input
bits : 22 - 44 (23 bit)
st : Schmitt trigger
bits : 23 - 46 (24 bit)
pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)
FPIOA GPIO multiplexer io array
address_offset : 0xF78 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)
ds : Driving selector
bits : 8 - 19 (12 bit)
oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)
oe_inv : Invert output enable
bits : 13 - 26 (14 bit)
do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)
do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)
pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)
pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)
sl : Slew rate control enable
bits : 19 - 38 (20 bit)
ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)
ie_inv : Invert input enable
bits : 21 - 42 (22 bit)
di_inv : Invert Data input
bits : 22 - 44 (23 bit)
st : Schmitt trigger
bits : 23 - 46 (24 bit)
pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.