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FPIOA

Peripheral Memory Blocks

Registers

io[0]

io[45]

io[11]

io[46]

io[47]

io[12]

io[13]

io[3]

tie_en[0]

io[14]

tie_val[0]

io[15]

io[16]

tie_en[1]

io[17]

io[4]

tie_val[1]

io[18]

io[19]

tie_en[2]

io[20]

tie_val[2]

io[21]

io[5]

tie_en[3]

io[22]

io[1]

io[23]

tie_val[3]

tie_en[4]

io[24]

io[25]

io[6]

tie_val[4]

io[26]

tie_en[5]

io[27]

tie_en[6]

io[28]

tie_val[5]

io[29]

io[7]

tie_en[7]

io[30]

tie_val[6]

io[31]

io[32]

tie_val[7]

io[33]

io[8]

io[34]

io[35]

io[36]

io[37]

io[9]

io[38]

io[2]

io[39]

io[40]

io[41]

io[10]

io[42]

io[43]

io[44]


io[0]

FPIOA GPIO multiplexer io array
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

io[0] io[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ch_sel ds oe_en oe_inv do_sel do_inv pu pd sl ie_en ie_inv di_inv st pad_di

ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)

ds : Driving selector
bits : 8 - 19 (12 bit)

oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)

oe_inv : Invert output enable
bits : 13 - 26 (14 bit)

do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)

do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)

pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)

pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)

sl : Slew rate control enable
bits : 19 - 38 (20 bit)

ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)

ie_inv : Invert input enable
bits : 21 - 42 (22 bit)

di_inv : Invert Data input
bits : 22 - 44 (23 bit)

st : Schmitt trigger
bits : 23 - 46 (24 bit)

pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)


io[45]

FPIOA GPIO multiplexer io array
address_offset : 0x102C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

io[45] io[45] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ch_sel ds oe_en oe_inv do_sel do_inv pu pd sl ie_en ie_inv di_inv st pad_di

ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)

ds : Driving selector
bits : 8 - 19 (12 bit)

oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)

oe_inv : Invert output enable
bits : 13 - 26 (14 bit)

do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)

do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)

pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)

pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)

sl : Slew rate control enable
bits : 19 - 38 (20 bit)

ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)

ie_inv : Invert input enable
bits : 21 - 42 (22 bit)

di_inv : Invert Data input
bits : 22 - 44 (23 bit)

st : Schmitt trigger
bits : 23 - 46 (24 bit)

pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)


io[11]

FPIOA GPIO multiplexer io array
address_offset : 0x108 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

io[11] io[11] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ch_sel ds oe_en oe_inv do_sel do_inv pu pd sl ie_en ie_inv di_inv st pad_di

ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)

ds : Driving selector
bits : 8 - 19 (12 bit)

oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)

oe_inv : Invert output enable
bits : 13 - 26 (14 bit)

do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)

do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)

pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)

pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)

sl : Slew rate control enable
bits : 19 - 38 (20 bit)

ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)

ie_inv : Invert input enable
bits : 21 - 42 (22 bit)

di_inv : Invert Data input
bits : 22 - 44 (23 bit)

st : Schmitt trigger
bits : 23 - 46 (24 bit)

pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)


io[46]

FPIOA GPIO multiplexer io array
address_offset : 0x10E4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

io[46] io[46] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ch_sel ds oe_en oe_inv do_sel do_inv pu pd sl ie_en ie_inv di_inv st pad_di

ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)

ds : Driving selector
bits : 8 - 19 (12 bit)

oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)

oe_inv : Invert output enable
bits : 13 - 26 (14 bit)

do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)

do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)

pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)

pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)

sl : Slew rate control enable
bits : 19 - 38 (20 bit)

ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)

ie_inv : Invert input enable
bits : 21 - 42 (22 bit)

di_inv : Invert Data input
bits : 22 - 44 (23 bit)

st : Schmitt trigger
bits : 23 - 46 (24 bit)

pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)


io[47]

FPIOA GPIO multiplexer io array
address_offset : 0x11A0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

io[47] io[47] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ch_sel ds oe_en oe_inv do_sel do_inv pu pd sl ie_en ie_inv di_inv st pad_di

ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)

ds : Driving selector
bits : 8 - 19 (12 bit)

oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)

oe_inv : Invert output enable
bits : 13 - 26 (14 bit)

do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)

do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)

pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)

pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)

sl : Slew rate control enable
bits : 19 - 38 (20 bit)

ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)

ie_inv : Invert input enable
bits : 21 - 42 (22 bit)

di_inv : Invert Data input
bits : 22 - 44 (23 bit)

st : Schmitt trigger
bits : 23 - 46 (24 bit)

pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)


io[12]

FPIOA GPIO multiplexer io array
address_offset : 0x138 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

io[12] io[12] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ch_sel ds oe_en oe_inv do_sel do_inv pu pd sl ie_en ie_inv di_inv st pad_di

ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)

ds : Driving selector
bits : 8 - 19 (12 bit)

oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)

oe_inv : Invert output enable
bits : 13 - 26 (14 bit)

do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)

do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)

pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)

pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)

sl : Slew rate control enable
bits : 19 - 38 (20 bit)

ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)

ie_inv : Invert input enable
bits : 21 - 42 (22 bit)

di_inv : Invert Data input
bits : 22 - 44 (23 bit)

st : Schmitt trigger
bits : 23 - 46 (24 bit)

pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)


io[13]

FPIOA GPIO multiplexer io array
address_offset : 0x16C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

io[13] io[13] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ch_sel ds oe_en oe_inv do_sel do_inv pu pd sl ie_en ie_inv di_inv st pad_di

ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)

ds : Driving selector
bits : 8 - 19 (12 bit)

oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)

oe_inv : Invert output enable
bits : 13 - 26 (14 bit)

do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)

do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)

pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)

pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)

sl : Slew rate control enable
bits : 19 - 38 (20 bit)

ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)

ie_inv : Invert input enable
bits : 21 - 42 (22 bit)

di_inv : Invert Data input
bits : 22 - 44 (23 bit)

st : Schmitt trigger
bits : 23 - 46 (24 bit)

pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)


io[3]

FPIOA GPIO multiplexer io array
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

io[3] io[3] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ch_sel ds oe_en oe_inv do_sel do_inv pu pd sl ie_en ie_inv di_inv st pad_di

ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)

ds : Driving selector
bits : 8 - 19 (12 bit)

oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)

oe_inv : Invert output enable
bits : 13 - 26 (14 bit)

do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)

do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)

pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)

pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)

sl : Slew rate control enable
bits : 19 - 38 (20 bit)

ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)

ie_inv : Invert input enable
bits : 21 - 42 (22 bit)

di_inv : Invert Data input
bits : 22 - 44 (23 bit)

st : Schmitt trigger
bits : 23 - 46 (24 bit)

pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)


tie_en[0]

FPIOA GPIO multiplexer tie enable array
address_offset : 0x180 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

tie_en[0] tie_en[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

io[14]

FPIOA GPIO multiplexer io array
address_offset : 0x1A4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

io[14] io[14] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ch_sel ds oe_en oe_inv do_sel do_inv pu pd sl ie_en ie_inv di_inv st pad_di

ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)

ds : Driving selector
bits : 8 - 19 (12 bit)

oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)

oe_inv : Invert output enable
bits : 13 - 26 (14 bit)

do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)

do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)

pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)

pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)

sl : Slew rate control enable
bits : 19 - 38 (20 bit)

ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)

ie_inv : Invert input enable
bits : 21 - 42 (22 bit)

di_inv : Invert Data input
bits : 22 - 44 (23 bit)

st : Schmitt trigger
bits : 23 - 46 (24 bit)

pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)


tie_val[0]

FPIOA GPIO multiplexer tie value array
address_offset : 0x1C0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

tie_val[0] tie_val[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

io[15]

FPIOA GPIO multiplexer io array
address_offset : 0x1E0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

io[15] io[15] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ch_sel ds oe_en oe_inv do_sel do_inv pu pd sl ie_en ie_inv di_inv st pad_di

ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)

ds : Driving selector
bits : 8 - 19 (12 bit)

oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)

oe_inv : Invert output enable
bits : 13 - 26 (14 bit)

do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)

do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)

pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)

pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)

sl : Slew rate control enable
bits : 19 - 38 (20 bit)

ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)

ie_inv : Invert input enable
bits : 21 - 42 (22 bit)

di_inv : Invert Data input
bits : 22 - 44 (23 bit)

st : Schmitt trigger
bits : 23 - 46 (24 bit)

pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)


io[16]

FPIOA GPIO multiplexer io array
address_offset : 0x220 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

io[16] io[16] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ch_sel ds oe_en oe_inv do_sel do_inv pu pd sl ie_en ie_inv di_inv st pad_di

ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)

ds : Driving selector
bits : 8 - 19 (12 bit)

oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)

oe_inv : Invert output enable
bits : 13 - 26 (14 bit)

do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)

do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)

pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)

pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)

sl : Slew rate control enable
bits : 19 - 38 (20 bit)

ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)

ie_inv : Invert input enable
bits : 21 - 42 (22 bit)

di_inv : Invert Data input
bits : 22 - 44 (23 bit)

st : Schmitt trigger
bits : 23 - 46 (24 bit)

pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)


tie_en[1]

FPIOA GPIO multiplexer tie enable array
address_offset : 0x244 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

tie_en[1] tie_en[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

io[17]

FPIOA GPIO multiplexer io array
address_offset : 0x264 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

io[17] io[17] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ch_sel ds oe_en oe_inv do_sel do_inv pu pd sl ie_en ie_inv di_inv st pad_di

ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)

ds : Driving selector
bits : 8 - 19 (12 bit)

oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)

oe_inv : Invert output enable
bits : 13 - 26 (14 bit)

do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)

do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)

pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)

pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)

sl : Slew rate control enable
bits : 19 - 38 (20 bit)

ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)

ie_inv : Invert input enable
bits : 21 - 42 (22 bit)

di_inv : Invert Data input
bits : 22 - 44 (23 bit)

st : Schmitt trigger
bits : 23 - 46 (24 bit)

pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)


io[4]

FPIOA GPIO multiplexer io array
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

io[4] io[4] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ch_sel ds oe_en oe_inv do_sel do_inv pu pd sl ie_en ie_inv di_inv st pad_di

ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)

ds : Driving selector
bits : 8 - 19 (12 bit)

oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)

oe_inv : Invert output enable
bits : 13 - 26 (14 bit)

do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)

do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)

pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)

pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)

sl : Slew rate control enable
bits : 19 - 38 (20 bit)

ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)

ie_inv : Invert input enable
bits : 21 - 42 (22 bit)

di_inv : Invert Data input
bits : 22 - 44 (23 bit)

st : Schmitt trigger
bits : 23 - 46 (24 bit)

pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)


tie_val[1]

FPIOA GPIO multiplexer tie value array
address_offset : 0x2A4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

tie_val[1] tie_val[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

io[18]

FPIOA GPIO multiplexer io array
address_offset : 0x2AC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

io[18] io[18] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ch_sel ds oe_en oe_inv do_sel do_inv pu pd sl ie_en ie_inv di_inv st pad_di

ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)

ds : Driving selector
bits : 8 - 19 (12 bit)

oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)

oe_inv : Invert output enable
bits : 13 - 26 (14 bit)

do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)

do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)

pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)

pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)

sl : Slew rate control enable
bits : 19 - 38 (20 bit)

ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)

ie_inv : Invert input enable
bits : 21 - 42 (22 bit)

di_inv : Invert Data input
bits : 22 - 44 (23 bit)

st : Schmitt trigger
bits : 23 - 46 (24 bit)

pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)


io[19]

FPIOA GPIO multiplexer io array
address_offset : 0x2F8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

io[19] io[19] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ch_sel ds oe_en oe_inv do_sel do_inv pu pd sl ie_en ie_inv di_inv st pad_di

ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)

ds : Driving selector
bits : 8 - 19 (12 bit)

oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)

oe_inv : Invert output enable
bits : 13 - 26 (14 bit)

do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)

do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)

pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)

pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)

sl : Slew rate control enable
bits : 19 - 38 (20 bit)

ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)

ie_inv : Invert input enable
bits : 21 - 42 (22 bit)

di_inv : Invert Data input
bits : 22 - 44 (23 bit)

st : Schmitt trigger
bits : 23 - 46 (24 bit)

pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)


tie_en[2]

FPIOA GPIO multiplexer tie enable array
address_offset : 0x30C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

tie_en[2] tie_en[2] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

io[20]

FPIOA GPIO multiplexer io array
address_offset : 0x348 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

io[20] io[20] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ch_sel ds oe_en oe_inv do_sel do_inv pu pd sl ie_en ie_inv di_inv st pad_di

ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)

ds : Driving selector
bits : 8 - 19 (12 bit)

oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)

oe_inv : Invert output enable
bits : 13 - 26 (14 bit)

do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)

do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)

pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)

pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)

sl : Slew rate control enable
bits : 19 - 38 (20 bit)

ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)

ie_inv : Invert input enable
bits : 21 - 42 (22 bit)

di_inv : Invert Data input
bits : 22 - 44 (23 bit)

st : Schmitt trigger
bits : 23 - 46 (24 bit)

pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)


tie_val[2]

FPIOA GPIO multiplexer tie value array
address_offset : 0x38C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

tie_val[2] tie_val[2] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

io[21]

FPIOA GPIO multiplexer io array
address_offset : 0x39C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

io[21] io[21] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ch_sel ds oe_en oe_inv do_sel do_inv pu pd sl ie_en ie_inv di_inv st pad_di

ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)

ds : Driving selector
bits : 8 - 19 (12 bit)

oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)

oe_inv : Invert output enable
bits : 13 - 26 (14 bit)

do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)

do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)

pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)

pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)

sl : Slew rate control enable
bits : 19 - 38 (20 bit)

ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)

ie_inv : Invert input enable
bits : 21 - 42 (22 bit)

di_inv : Invert Data input
bits : 22 - 44 (23 bit)

st : Schmitt trigger
bits : 23 - 46 (24 bit)

pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)


io[5]

FPIOA GPIO multiplexer io array
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

io[5] io[5] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ch_sel ds oe_en oe_inv do_sel do_inv pu pd sl ie_en ie_inv di_inv st pad_di

ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)

ds : Driving selector
bits : 8 - 19 (12 bit)

oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)

oe_inv : Invert output enable
bits : 13 - 26 (14 bit)

do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)

do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)

pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)

pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)

sl : Slew rate control enable
bits : 19 - 38 (20 bit)

ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)

ie_inv : Invert input enable
bits : 21 - 42 (22 bit)

di_inv : Invert Data input
bits : 22 - 44 (23 bit)

st : Schmitt trigger
bits : 23 - 46 (24 bit)

pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)


tie_en[3]

FPIOA GPIO multiplexer tie enable array
address_offset : 0x3D8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

tie_en[3] tie_en[3] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

io[22]

FPIOA GPIO multiplexer io array
address_offset : 0x3F4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

io[22] io[22] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ch_sel ds oe_en oe_inv do_sel do_inv pu pd sl ie_en ie_inv di_inv st pad_di

ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)

ds : Driving selector
bits : 8 - 19 (12 bit)

oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)

oe_inv : Invert output enable
bits : 13 - 26 (14 bit)

do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)

do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)

pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)

pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)

sl : Slew rate control enable
bits : 19 - 38 (20 bit)

ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)

ie_inv : Invert input enable
bits : 21 - 42 (22 bit)

di_inv : Invert Data input
bits : 22 - 44 (23 bit)

st : Schmitt trigger
bits : 23 - 46 (24 bit)

pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)


io[1]

FPIOA GPIO multiplexer io array
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

io[1] io[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ch_sel ds oe_en oe_inv do_sel do_inv pu pd sl ie_en ie_inv di_inv st pad_di

ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)

ds : Driving selector
bits : 8 - 19 (12 bit)

oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)

oe_inv : Invert output enable
bits : 13 - 26 (14 bit)

do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)

do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)

pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)

pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)

sl : Slew rate control enable
bits : 19 - 38 (20 bit)

ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)

ie_inv : Invert input enable
bits : 21 - 42 (22 bit)

di_inv : Invert Data input
bits : 22 - 44 (23 bit)

st : Schmitt trigger
bits : 23 - 46 (24 bit)

pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)


io[23]

FPIOA GPIO multiplexer io array
address_offset : 0x450 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

io[23] io[23] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ch_sel ds oe_en oe_inv do_sel do_inv pu pd sl ie_en ie_inv di_inv st pad_di

ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)

ds : Driving selector
bits : 8 - 19 (12 bit)

oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)

oe_inv : Invert output enable
bits : 13 - 26 (14 bit)

do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)

do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)

pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)

pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)

sl : Slew rate control enable
bits : 19 - 38 (20 bit)

ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)

ie_inv : Invert input enable
bits : 21 - 42 (22 bit)

di_inv : Invert Data input
bits : 22 - 44 (23 bit)

st : Schmitt trigger
bits : 23 - 46 (24 bit)

pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)


tie_val[3]

FPIOA GPIO multiplexer tie value array
address_offset : 0x478 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

tie_val[3] tie_val[3] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

tie_en[4]

FPIOA GPIO multiplexer tie enable array
address_offset : 0x4A8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

tie_en[4] tie_en[4] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

io[24]

FPIOA GPIO multiplexer io array
address_offset : 0x4B0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

io[24] io[24] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ch_sel ds oe_en oe_inv do_sel do_inv pu pd sl ie_en ie_inv di_inv st pad_di

ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)

ds : Driving selector
bits : 8 - 19 (12 bit)

oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)

oe_inv : Invert output enable
bits : 13 - 26 (14 bit)

do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)

do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)

pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)

pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)

sl : Slew rate control enable
bits : 19 - 38 (20 bit)

ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)

ie_inv : Invert input enable
bits : 21 - 42 (22 bit)

di_inv : Invert Data input
bits : 22 - 44 (23 bit)

st : Schmitt trigger
bits : 23 - 46 (24 bit)

pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)


io[25]

FPIOA GPIO multiplexer io array
address_offset : 0x514 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

io[25] io[25] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ch_sel ds oe_en oe_inv do_sel do_inv pu pd sl ie_en ie_inv di_inv st pad_di

ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)

ds : Driving selector
bits : 8 - 19 (12 bit)

oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)

oe_inv : Invert output enable
bits : 13 - 26 (14 bit)

do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)

do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)

pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)

pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)

sl : Slew rate control enable
bits : 19 - 38 (20 bit)

ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)

ie_inv : Invert input enable
bits : 21 - 42 (22 bit)

di_inv : Invert Data input
bits : 22 - 44 (23 bit)

st : Schmitt trigger
bits : 23 - 46 (24 bit)

pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)


io[6]

FPIOA GPIO multiplexer io array
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

io[6] io[6] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ch_sel ds oe_en oe_inv do_sel do_inv pu pd sl ie_en ie_inv di_inv st pad_di

ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)

ds : Driving selector
bits : 8 - 19 (12 bit)

oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)

oe_inv : Invert output enable
bits : 13 - 26 (14 bit)

do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)

do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)

pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)

pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)

sl : Slew rate control enable
bits : 19 - 38 (20 bit)

ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)

ie_inv : Invert input enable
bits : 21 - 42 (22 bit)

di_inv : Invert Data input
bits : 22 - 44 (23 bit)

st : Schmitt trigger
bits : 23 - 46 (24 bit)

pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)


tie_val[4]

FPIOA GPIO multiplexer tie value array
address_offset : 0x568 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

tie_val[4] tie_val[4] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

io[26]

FPIOA GPIO multiplexer io array
address_offset : 0x57C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

io[26] io[26] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ch_sel ds oe_en oe_inv do_sel do_inv pu pd sl ie_en ie_inv di_inv st pad_di

ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)

ds : Driving selector
bits : 8 - 19 (12 bit)

oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)

oe_inv : Invert output enable
bits : 13 - 26 (14 bit)

do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)

do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)

pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)

pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)

sl : Slew rate control enable
bits : 19 - 38 (20 bit)

ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)

ie_inv : Invert input enable
bits : 21 - 42 (22 bit)

di_inv : Invert Data input
bits : 22 - 44 (23 bit)

st : Schmitt trigger
bits : 23 - 46 (24 bit)

pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)


tie_en[5]

FPIOA GPIO multiplexer tie enable array
address_offset : 0x57C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

tie_en[5] tie_en[5] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

io[27]

FPIOA GPIO multiplexer io array
address_offset : 0x5E8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

io[27] io[27] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ch_sel ds oe_en oe_inv do_sel do_inv pu pd sl ie_en ie_inv di_inv st pad_di

ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)

ds : Driving selector
bits : 8 - 19 (12 bit)

oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)

oe_inv : Invert output enable
bits : 13 - 26 (14 bit)

do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)

do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)

pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)

pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)

sl : Slew rate control enable
bits : 19 - 38 (20 bit)

ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)

ie_inv : Invert input enable
bits : 21 - 42 (22 bit)

di_inv : Invert Data input
bits : 22 - 44 (23 bit)

st : Schmitt trigger
bits : 23 - 46 (24 bit)

pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)


tie_en[6]

FPIOA GPIO multiplexer tie enable array
address_offset : 0x654 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

tie_en[6] tie_en[6] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

io[28]

FPIOA GPIO multiplexer io array
address_offset : 0x658 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

io[28] io[28] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ch_sel ds oe_en oe_inv do_sel do_inv pu pd sl ie_en ie_inv di_inv st pad_di

ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)

ds : Driving selector
bits : 8 - 19 (12 bit)

oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)

oe_inv : Invert output enable
bits : 13 - 26 (14 bit)

do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)

do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)

pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)

pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)

sl : Slew rate control enable
bits : 19 - 38 (20 bit)

ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)

ie_inv : Invert input enable
bits : 21 - 42 (22 bit)

di_inv : Invert Data input
bits : 22 - 44 (23 bit)

st : Schmitt trigger
bits : 23 - 46 (24 bit)

pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)


tie_val[5]

FPIOA GPIO multiplexer tie value array
address_offset : 0x65C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

tie_val[5] tie_val[5] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

io[29]

FPIOA GPIO multiplexer io array
address_offset : 0x6CC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

io[29] io[29] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ch_sel ds oe_en oe_inv do_sel do_inv pu pd sl ie_en ie_inv di_inv st pad_di

ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)

ds : Driving selector
bits : 8 - 19 (12 bit)

oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)

oe_inv : Invert output enable
bits : 13 - 26 (14 bit)

do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)

do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)

pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)

pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)

sl : Slew rate control enable
bits : 19 - 38 (20 bit)

ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)

ie_inv : Invert input enable
bits : 21 - 42 (22 bit)

di_inv : Invert Data input
bits : 22 - 44 (23 bit)

st : Schmitt trigger
bits : 23 - 46 (24 bit)

pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)


io[7]

FPIOA GPIO multiplexer io array
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

io[7] io[7] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ch_sel ds oe_en oe_inv do_sel do_inv pu pd sl ie_en ie_inv di_inv st pad_di

ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)

ds : Driving selector
bits : 8 - 19 (12 bit)

oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)

oe_inv : Invert output enable
bits : 13 - 26 (14 bit)

do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)

do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)

pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)

pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)

sl : Slew rate control enable
bits : 19 - 38 (20 bit)

ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)

ie_inv : Invert input enable
bits : 21 - 42 (22 bit)

di_inv : Invert Data input
bits : 22 - 44 (23 bit)

st : Schmitt trigger
bits : 23 - 46 (24 bit)

pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)


tie_en[7]

FPIOA GPIO multiplexer tie enable array
address_offset : 0x730 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

tie_en[7] tie_en[7] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

io[30]

FPIOA GPIO multiplexer io array
address_offset : 0x744 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

io[30] io[30] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ch_sel ds oe_en oe_inv do_sel do_inv pu pd sl ie_en ie_inv di_inv st pad_di

ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)

ds : Driving selector
bits : 8 - 19 (12 bit)

oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)

oe_inv : Invert output enable
bits : 13 - 26 (14 bit)

do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)

do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)

pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)

pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)

sl : Slew rate control enable
bits : 19 - 38 (20 bit)

ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)

ie_inv : Invert input enable
bits : 21 - 42 (22 bit)

di_inv : Invert Data input
bits : 22 - 44 (23 bit)

st : Schmitt trigger
bits : 23 - 46 (24 bit)

pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)


tie_val[6]

FPIOA GPIO multiplexer tie value array
address_offset : 0x754 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

tie_val[6] tie_val[6] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

io[31]

FPIOA GPIO multiplexer io array
address_offset : 0x7C0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

io[31] io[31] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ch_sel ds oe_en oe_inv do_sel do_inv pu pd sl ie_en ie_inv di_inv st pad_di

ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)

ds : Driving selector
bits : 8 - 19 (12 bit)

oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)

oe_inv : Invert output enable
bits : 13 - 26 (14 bit)

do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)

do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)

pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)

pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)

sl : Slew rate control enable
bits : 19 - 38 (20 bit)

ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)

ie_inv : Invert input enable
bits : 21 - 42 (22 bit)

di_inv : Invert Data input
bits : 22 - 44 (23 bit)

st : Schmitt trigger
bits : 23 - 46 (24 bit)

pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)


io[32]

FPIOA GPIO multiplexer io array
address_offset : 0x840 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

io[32] io[32] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ch_sel ds oe_en oe_inv do_sel do_inv pu pd sl ie_en ie_inv di_inv st pad_di

ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)

ds : Driving selector
bits : 8 - 19 (12 bit)

oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)

oe_inv : Invert output enable
bits : 13 - 26 (14 bit)

do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)

do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)

pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)

pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)

sl : Slew rate control enable
bits : 19 - 38 (20 bit)

ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)

ie_inv : Invert input enable
bits : 21 - 42 (22 bit)

di_inv : Invert Data input
bits : 22 - 44 (23 bit)

st : Schmitt trigger
bits : 23 - 46 (24 bit)

pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)


tie_val[7]

FPIOA GPIO multiplexer tie value array
address_offset : 0x850 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

tie_val[7] tie_val[7] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

io[33]

FPIOA GPIO multiplexer io array
address_offset : 0x8C4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

io[33] io[33] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ch_sel ds oe_en oe_inv do_sel do_inv pu pd sl ie_en ie_inv di_inv st pad_di

ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)

ds : Driving selector
bits : 8 - 19 (12 bit)

oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)

oe_inv : Invert output enable
bits : 13 - 26 (14 bit)

do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)

do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)

pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)

pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)

sl : Slew rate control enable
bits : 19 - 38 (20 bit)

ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)

ie_inv : Invert input enable
bits : 21 - 42 (22 bit)

di_inv : Invert Data input
bits : 22 - 44 (23 bit)

st : Schmitt trigger
bits : 23 - 46 (24 bit)

pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)


io[8]

FPIOA GPIO multiplexer io array
address_offset : 0x90 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

io[8] io[8] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ch_sel ds oe_en oe_inv do_sel do_inv pu pd sl ie_en ie_inv di_inv st pad_di

ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)

ds : Driving selector
bits : 8 - 19 (12 bit)

oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)

oe_inv : Invert output enable
bits : 13 - 26 (14 bit)

do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)

do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)

pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)

pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)

sl : Slew rate control enable
bits : 19 - 38 (20 bit)

ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)

ie_inv : Invert input enable
bits : 21 - 42 (22 bit)

di_inv : Invert Data input
bits : 22 - 44 (23 bit)

st : Schmitt trigger
bits : 23 - 46 (24 bit)

pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)


io[34]

FPIOA GPIO multiplexer io array
address_offset : 0x94C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

io[34] io[34] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ch_sel ds oe_en oe_inv do_sel do_inv pu pd sl ie_en ie_inv di_inv st pad_di

ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)

ds : Driving selector
bits : 8 - 19 (12 bit)

oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)

oe_inv : Invert output enable
bits : 13 - 26 (14 bit)

do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)

do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)

pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)

pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)

sl : Slew rate control enable
bits : 19 - 38 (20 bit)

ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)

ie_inv : Invert input enable
bits : 21 - 42 (22 bit)

di_inv : Invert Data input
bits : 22 - 44 (23 bit)

st : Schmitt trigger
bits : 23 - 46 (24 bit)

pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)


io[35]

FPIOA GPIO multiplexer io array
address_offset : 0x9D8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

io[35] io[35] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ch_sel ds oe_en oe_inv do_sel do_inv pu pd sl ie_en ie_inv di_inv st pad_di

ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)

ds : Driving selector
bits : 8 - 19 (12 bit)

oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)

oe_inv : Invert output enable
bits : 13 - 26 (14 bit)

do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)

do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)

pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)

pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)

sl : Slew rate control enable
bits : 19 - 38 (20 bit)

ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)

ie_inv : Invert input enable
bits : 21 - 42 (22 bit)

di_inv : Invert Data input
bits : 22 - 44 (23 bit)

st : Schmitt trigger
bits : 23 - 46 (24 bit)

pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)


io[36]

FPIOA GPIO multiplexer io array
address_offset : 0xA68 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

io[36] io[36] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ch_sel ds oe_en oe_inv do_sel do_inv pu pd sl ie_en ie_inv di_inv st pad_di

ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)

ds : Driving selector
bits : 8 - 19 (12 bit)

oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)

oe_inv : Invert output enable
bits : 13 - 26 (14 bit)

do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)

do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)

pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)

pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)

sl : Slew rate control enable
bits : 19 - 38 (20 bit)

ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)

ie_inv : Invert input enable
bits : 21 - 42 (22 bit)

di_inv : Invert Data input
bits : 22 - 44 (23 bit)

st : Schmitt trigger
bits : 23 - 46 (24 bit)

pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)


io[37]

FPIOA GPIO multiplexer io array
address_offset : 0xAFC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

io[37] io[37] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ch_sel ds oe_en oe_inv do_sel do_inv pu pd sl ie_en ie_inv di_inv st pad_di

ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)

ds : Driving selector
bits : 8 - 19 (12 bit)

oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)

oe_inv : Invert output enable
bits : 13 - 26 (14 bit)

do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)

do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)

pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)

pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)

sl : Slew rate control enable
bits : 19 - 38 (20 bit)

ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)

ie_inv : Invert input enable
bits : 21 - 42 (22 bit)

di_inv : Invert Data input
bits : 22 - 44 (23 bit)

st : Schmitt trigger
bits : 23 - 46 (24 bit)

pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)


io[9]

FPIOA GPIO multiplexer io array
address_offset : 0xB4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

io[9] io[9] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ch_sel ds oe_en oe_inv do_sel do_inv pu pd sl ie_en ie_inv di_inv st pad_di

ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)

ds : Driving selector
bits : 8 - 19 (12 bit)

oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)

oe_inv : Invert output enable
bits : 13 - 26 (14 bit)

do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)

do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)

pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)

pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)

sl : Slew rate control enable
bits : 19 - 38 (20 bit)

ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)

ie_inv : Invert input enable
bits : 21 - 42 (22 bit)

di_inv : Invert Data input
bits : 22 - 44 (23 bit)

st : Schmitt trigger
bits : 23 - 46 (24 bit)

pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)


io[38]

FPIOA GPIO multiplexer io array
address_offset : 0xB94 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

io[38] io[38] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ch_sel ds oe_en oe_inv do_sel do_inv pu pd sl ie_en ie_inv di_inv st pad_di

ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)

ds : Driving selector
bits : 8 - 19 (12 bit)

oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)

oe_inv : Invert output enable
bits : 13 - 26 (14 bit)

do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)

do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)

pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)

pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)

sl : Slew rate control enable
bits : 19 - 38 (20 bit)

ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)

ie_inv : Invert input enable
bits : 21 - 42 (22 bit)

di_inv : Invert Data input
bits : 22 - 44 (23 bit)

st : Schmitt trigger
bits : 23 - 46 (24 bit)

pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)


io[2]

FPIOA GPIO multiplexer io array
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

io[2] io[2] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ch_sel ds oe_en oe_inv do_sel do_inv pu pd sl ie_en ie_inv di_inv st pad_di

ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)

ds : Driving selector
bits : 8 - 19 (12 bit)

oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)

oe_inv : Invert output enable
bits : 13 - 26 (14 bit)

do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)

do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)

pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)

pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)

sl : Slew rate control enable
bits : 19 - 38 (20 bit)

ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)

ie_inv : Invert input enable
bits : 21 - 42 (22 bit)

di_inv : Invert Data input
bits : 22 - 44 (23 bit)

st : Schmitt trigger
bits : 23 - 46 (24 bit)

pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)


io[39]

FPIOA GPIO multiplexer io array
address_offset : 0xC30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

io[39] io[39] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ch_sel ds oe_en oe_inv do_sel do_inv pu pd sl ie_en ie_inv di_inv st pad_di

ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)

ds : Driving selector
bits : 8 - 19 (12 bit)

oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)

oe_inv : Invert output enable
bits : 13 - 26 (14 bit)

do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)

do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)

pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)

pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)

sl : Slew rate control enable
bits : 19 - 38 (20 bit)

ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)

ie_inv : Invert input enable
bits : 21 - 42 (22 bit)

di_inv : Invert Data input
bits : 22 - 44 (23 bit)

st : Schmitt trigger
bits : 23 - 46 (24 bit)

pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)


io[40]

FPIOA GPIO multiplexer io array
address_offset : 0xCD0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

io[40] io[40] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ch_sel ds oe_en oe_inv do_sel do_inv pu pd sl ie_en ie_inv di_inv st pad_di

ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)

ds : Driving selector
bits : 8 - 19 (12 bit)

oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)

oe_inv : Invert output enable
bits : 13 - 26 (14 bit)

do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)

do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)

pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)

pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)

sl : Slew rate control enable
bits : 19 - 38 (20 bit)

ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)

ie_inv : Invert input enable
bits : 21 - 42 (22 bit)

di_inv : Invert Data input
bits : 22 - 44 (23 bit)

st : Schmitt trigger
bits : 23 - 46 (24 bit)

pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)


io[41]

FPIOA GPIO multiplexer io array
address_offset : 0xD74 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

io[41] io[41] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ch_sel ds oe_en oe_inv do_sel do_inv pu pd sl ie_en ie_inv di_inv st pad_di

ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)

ds : Driving selector
bits : 8 - 19 (12 bit)

oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)

oe_inv : Invert output enable
bits : 13 - 26 (14 bit)

do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)

do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)

pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)

pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)

sl : Slew rate control enable
bits : 19 - 38 (20 bit)

ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)

ie_inv : Invert input enable
bits : 21 - 42 (22 bit)

di_inv : Invert Data input
bits : 22 - 44 (23 bit)

st : Schmitt trigger
bits : 23 - 46 (24 bit)

pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)


io[10]

FPIOA GPIO multiplexer io array
address_offset : 0xDC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

io[10] io[10] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ch_sel ds oe_en oe_inv do_sel do_inv pu pd sl ie_en ie_inv di_inv st pad_di

ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)

ds : Driving selector
bits : 8 - 19 (12 bit)

oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)

oe_inv : Invert output enable
bits : 13 - 26 (14 bit)

do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)

do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)

pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)

pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)

sl : Slew rate control enable
bits : 19 - 38 (20 bit)

ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)

ie_inv : Invert input enable
bits : 21 - 42 (22 bit)

di_inv : Invert Data input
bits : 22 - 44 (23 bit)

st : Schmitt trigger
bits : 23 - 46 (24 bit)

pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)


io[42]

FPIOA GPIO multiplexer io array
address_offset : 0xE1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

io[42] io[42] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ch_sel ds oe_en oe_inv do_sel do_inv pu pd sl ie_en ie_inv di_inv st pad_di

ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)

ds : Driving selector
bits : 8 - 19 (12 bit)

oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)

oe_inv : Invert output enable
bits : 13 - 26 (14 bit)

do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)

do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)

pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)

pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)

sl : Slew rate control enable
bits : 19 - 38 (20 bit)

ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)

ie_inv : Invert input enable
bits : 21 - 42 (22 bit)

di_inv : Invert Data input
bits : 22 - 44 (23 bit)

st : Schmitt trigger
bits : 23 - 46 (24 bit)

pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)


io[43]

FPIOA GPIO multiplexer io array
address_offset : 0xEC8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

io[43] io[43] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ch_sel ds oe_en oe_inv do_sel do_inv pu pd sl ie_en ie_inv di_inv st pad_di

ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)

ds : Driving selector
bits : 8 - 19 (12 bit)

oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)

oe_inv : Invert output enable
bits : 13 - 26 (14 bit)

do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)

do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)

pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)

pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)

sl : Slew rate control enable
bits : 19 - 38 (20 bit)

ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)

ie_inv : Invert input enable
bits : 21 - 42 (22 bit)

di_inv : Invert Data input
bits : 22 - 44 (23 bit)

st : Schmitt trigger
bits : 23 - 46 (24 bit)

pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)


io[44]

FPIOA GPIO multiplexer io array
address_offset : 0xF78 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

io[44] io[44] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ch_sel ds oe_en oe_inv do_sel do_inv pu pd sl ie_en ie_inv di_inv st pad_di

ch_sel : Channel select from 256 input
bits : 0 - 7 (8 bit)

ds : Driving selector
bits : 8 - 19 (12 bit)

oe_en : Static output enable, will AND with OE_INV
bits : 12 - 24 (13 bit)

oe_inv : Invert output enable
bits : 13 - 26 (14 bit)

do_sel : Data output select: 0 for DO, 1 for OE
bits : 14 - 28 (15 bit)

do_inv : Invert the result of data output select (DO_SEL)
bits : 15 - 30 (16 bit)

pu : Pull up enable. 0 for nothing, 1 for pull up
bits : 16 - 32 (17 bit)

pd : Pull down enable. 0 for nothing, 1 for pull down
bits : 17 - 34 (18 bit)

sl : Slew rate control enable
bits : 19 - 38 (20 bit)

ie_en : Static input enable, will AND with IE_INV
bits : 20 - 40 (21 bit)

ie_inv : Invert input enable
bits : 21 - 42 (22 bit)

di_inv : Invert Data input
bits : 22 - 44 (23 bit)

st : Schmitt trigger
bits : 23 - 46 (24 bit)

pad_di : Read current IO's data input
bits : 31 - 62 (32 bit)



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