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channel1-channel0-current_value
channel2-channel1-channel0-load_count
channel2-channel1-channel0-current_value
channel2-channel1-channel0-control
channel2-channel1-channel0-eoi
channel2-channel1-channel0-intr_stat
channel3-channel2-channel1-channel0-load_count
channel3-channel2-channel1-channel0-current_value
channel3-channel2-channel1-channel0-control
channel3-channel2-channel1-channel0-eoi
channel3-channel2-channel1-channel0-intr_stat
Load Count Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Interrupt Status Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Load Count Register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Load Count2 Register
address_offset : 0x160 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Current Value Register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Control Register
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
enable : ENABLE
bits : 0 - 0 (1 bit)
mode : MODE
bits : 1 - 2 (2 bit)
Enumeration:
0 : free
FREE_MODE
1 : user
USER_MODE
End of enumeration elements list.
interrupt : INTERRUPT_MASK
bits : 2 - 4 (3 bit)
pwm_enable : PWM_ENABLE
bits : 3 - 6 (4 bit)
Interrupt Clear Register
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Load Count2 Register
address_offset : 0x214 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Interrupt Status Register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Load Count2 Register
address_offset : 0x2CC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Load Count2 Register
address_offset : 0x388 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Load Count Register
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Current Value Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Current Value Register
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Control Register
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
enable : ENABLE
bits : 0 - 0 (1 bit)
mode : MODE
bits : 1 - 2 (2 bit)
Enumeration:
0 : free
FREE_MODE
1 : user
USER_MODE
End of enumeration elements list.
interrupt : INTERRUPT_MASK
bits : 2 - 4 (3 bit)
pwm_enable : PWM_ENABLE
bits : 3 - 6 (4 bit)
Interrupt Clear Register
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Interrupt Status Register
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Load Count Register
address_offset : 0x78 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Current Value Register
address_offset : 0x7C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Control Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
enable : ENABLE
bits : 0 - 0 (1 bit)
mode : MODE
bits : 1 - 2 (2 bit)
Enumeration:
0 : free
FREE_MODE
1 : user
USER_MODE
End of enumeration elements list.
interrupt : INTERRUPT_MASK
bits : 2 - 4 (3 bit)
pwm_enable : PWM_ENABLE
bits : 3 - 6 (4 bit)
Control Register
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
enable : ENABLE
bits : 0 - 0 (1 bit)
mode : MODE
bits : 1 - 2 (2 bit)
Enumeration:
0 : free
FREE_MODE
1 : user
USER_MODE
End of enumeration elements list.
interrupt : INTERRUPT_MASK
bits : 2 - 4 (3 bit)
pwm_enable : PWM_ENABLE
bits : 3 - 6 (4 bit)
Interrupt Clear Register
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Interrupt Status Register
address_offset : 0x88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Interrupt Status Register
address_offset : 0xA0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Interrupt Clear Register
address_offset : 0xA4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Raw Interrupt Status Register
address_offset : 0xA8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Component Version Register
address_offset : 0xAC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Interrupt Clear Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
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