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TIMER

Peripheral Memory Blocks

Registers

channel0-load_count

channel0-intr_stat

channel1-channel0-load_count

load_count20

channel1-channel0-current_value

channel1-channel0-control

channel1-channel0-eoi

load_count21

channel1-channel0-intr_stat

load_count22

load_count23

channel2-channel1-channel0-load_count

channel0-current_value

channel2-channel1-channel0-current_value

channel2-channel1-channel0-control

channel2-channel1-channel0-eoi

channel2-channel1-channel0-intr_stat

channel3-channel2-channel1-channel0-load_count

channel3-channel2-channel1-channel0-current_value

channel0-control

channel3-channel2-channel1-channel0-control

channel3-channel2-channel1-channel0-eoi

channel3-channel2-channel1-channel0-intr_stat

intr_stat

eoi

raw_intr_stat

comp_version

channel0-eoi


channel0-load_count

Load Count Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel0-load_count channel0-load_count read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

channel0-intr_stat

Interrupt Status Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel0-intr_stat channel0-intr_stat read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

channel1-channel0-load_count

Load Count Register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel1-channel0-load_count channel1-channel0-load_count read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

load_count20

Load Count2 Register
address_offset : 0x160 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

load_count20 load_count20 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

channel1-channel0-current_value

Current Value Register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel1-channel0-current_value channel1-channel0-current_value read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

channel1-channel0-control

Control Register
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel1-channel0-control channel1-channel0-control read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 enable mode interrupt pwm_enable

enable : ENABLE
bits : 0 - 0 (1 bit)

mode : MODE
bits : 1 - 2 (2 bit)

Enumeration:

0 : free

FREE_MODE

1 : user

USER_MODE

End of enumeration elements list.

interrupt : INTERRUPT_MASK
bits : 2 - 4 (3 bit)

pwm_enable : PWM_ENABLE
bits : 3 - 6 (4 bit)


channel1-channel0-eoi

Interrupt Clear Register
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel1-channel0-eoi channel1-channel0-eoi read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

load_count21

Load Count2 Register
address_offset : 0x214 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

load_count21 load_count21 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

channel1-channel0-intr_stat

Interrupt Status Register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel1-channel0-intr_stat channel1-channel0-intr_stat read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

load_count22

Load Count2 Register
address_offset : 0x2CC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

load_count22 load_count22 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

load_count23

Load Count2 Register
address_offset : 0x388 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

load_count23 load_count23 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

channel2-channel1-channel0-load_count

Load Count Register
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel2-channel1-channel0-load_count channel2-channel1-channel0-load_count read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

channel0-current_value

Current Value Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel0-current_value channel0-current_value read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

channel2-channel1-channel0-current_value

Current Value Register
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel2-channel1-channel0-current_value channel2-channel1-channel0-current_value read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

channel2-channel1-channel0-control

Control Register
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel2-channel1-channel0-control channel2-channel1-channel0-control read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 enable mode interrupt pwm_enable

enable : ENABLE
bits : 0 - 0 (1 bit)

mode : MODE
bits : 1 - 2 (2 bit)

Enumeration:

0 : free

FREE_MODE

1 : user

USER_MODE

End of enumeration elements list.

interrupt : INTERRUPT_MASK
bits : 2 - 4 (3 bit)

pwm_enable : PWM_ENABLE
bits : 3 - 6 (4 bit)


channel2-channel1-channel0-eoi

Interrupt Clear Register
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel2-channel1-channel0-eoi channel2-channel1-channel0-eoi read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

channel2-channel1-channel0-intr_stat

Interrupt Status Register
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel2-channel1-channel0-intr_stat channel2-channel1-channel0-intr_stat read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

channel3-channel2-channel1-channel0-load_count

Load Count Register
address_offset : 0x78 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel3-channel2-channel1-channel0-load_count channel3-channel2-channel1-channel0-load_count read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

channel3-channel2-channel1-channel0-current_value

Current Value Register
address_offset : 0x7C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel3-channel2-channel1-channel0-current_value channel3-channel2-channel1-channel0-current_value read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

channel0-control

Control Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel0-control channel0-control read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 enable mode interrupt pwm_enable

enable : ENABLE
bits : 0 - 0 (1 bit)

mode : MODE
bits : 1 - 2 (2 bit)

Enumeration:

0 : free

FREE_MODE

1 : user

USER_MODE

End of enumeration elements list.

interrupt : INTERRUPT_MASK
bits : 2 - 4 (3 bit)

pwm_enable : PWM_ENABLE
bits : 3 - 6 (4 bit)


channel3-channel2-channel1-channel0-control

Control Register
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel3-channel2-channel1-channel0-control channel3-channel2-channel1-channel0-control read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 enable mode interrupt pwm_enable

enable : ENABLE
bits : 0 - 0 (1 bit)

mode : MODE
bits : 1 - 2 (2 bit)

Enumeration:

0 : free

FREE_MODE

1 : user

USER_MODE

End of enumeration elements list.

interrupt : INTERRUPT_MASK
bits : 2 - 4 (3 bit)

pwm_enable : PWM_ENABLE
bits : 3 - 6 (4 bit)


channel3-channel2-channel1-channel0-eoi

Interrupt Clear Register
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel3-channel2-channel1-channel0-eoi channel3-channel2-channel1-channel0-eoi read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

channel3-channel2-channel1-channel0-intr_stat

Interrupt Status Register
address_offset : 0x88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel3-channel2-channel1-channel0-intr_stat channel3-channel2-channel1-channel0-intr_stat read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

intr_stat

Interrupt Status Register
address_offset : 0xA0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

intr_stat intr_stat read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

eoi

Interrupt Clear Register
address_offset : 0xA4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

eoi eoi read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

raw_intr_stat

Raw Interrupt Status Register
address_offset : 0xA8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

raw_intr_stat raw_intr_stat read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

comp_version

Component Version Register
address_offset : 0xAC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

comp_version comp_version read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

channel0-eoi

Interrupt Clear Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

channel0-eoi channel0-eoi read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


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