\n
Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
enable : enable
bits : 0 - 0 (1 bit)
rmod : rmod
bits : 1 - 2 (2 bit)
Enumeration:
0 : reset
RESET
1 : interrupt
INTERRUPT
End of enumeration elements list.
rpl : rpl
bits : 2 - 6 (5 bit)
Interrupt Status Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
stat : stat
bits : 0 - 0 (1 bit)
Interrupt Clear Register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
eoi : eoi
bits : 0 - 0 (1 bit)
Protection level Register
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
prot_level : prot_level
bits : 0 - 2 (3 bit)
Timeout Range Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
top0 : top (lower half)
bits : 0 - 3 (4 bit)
top1 : top (upper half)
bits : 4 - 11 (8 bit)
Current Counter Value Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Counter Restart Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Component Parameters Register 5
address_offset : 0xE4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
user_top_max : user_top_max
bits : 0 - 31 (32 bit)
Component Parameters Register 4
address_offset : 0xE8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
user_top_init_max : user_top_init_max
bits : 0 - 31 (32 bit)
Component Parameters Register 3
address_offset : 0xEC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
top_rst : top_rst
bits : 0 - 31 (32 bit)
Component Parameters Register 2
address_offset : 0xF0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
cnt_rst : cnt_rst
bits : 0 - 31 (32 bit)
Component Parameters Register 1
address_offset : 0xF4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
always_en : always_en
bits : 0 - 0 (1 bit)
dflt_rmod : dflt_rmod
bits : 1 - 2 (2 bit)
dual_top : dual_top
bits : 2 - 4 (3 bit)
hc_rmod : hc_rmod
bits : 3 - 6 (4 bit)
hc_rpl : hc_rpl
bits : 4 - 8 (5 bit)
hc_top : hc_top
bits : 5 - 10 (6 bit)
use_fix_top : use_fix_top
bits : 6 - 12 (7 bit)
pause : pause
bits : 7 - 14 (8 bit)
apb_data_width : apb_data_width
bits : 8 - 17 (10 bit)
dflt_rpl : dflt_rpl
bits : 10 - 22 (13 bit)
dflt_top : dflt_top
bits : 16 - 35 (20 bit)
dflt_top_init : dflt_top_init
bits : 20 - 43 (24 bit)
cnt_width : cnt_width
bits : 24 - 52 (29 bit)
Component Version Register
address_offset : 0xF8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Component Type Register
address_offset : 0xFC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
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