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WDT

Peripheral Memory Blocks

Registers

cr

stat

eoi

prot_level

torr

ccvr

crr

comp_param_5

comp_param_4

comp_param_3

comp_param_2

comp_param_1

comp_version

comp_type


cr

Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

cr cr read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 enable rmod rpl

enable : enable
bits : 0 - 0 (1 bit)

rmod : rmod
bits : 1 - 2 (2 bit)

Enumeration:

0 : reset

RESET

1 : interrupt

INTERRUPT

End of enumeration elements list.

rpl : rpl
bits : 2 - 6 (5 bit)


stat

Interrupt Status Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

stat stat read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 stat

stat : stat
bits : 0 - 0 (1 bit)


eoi

Interrupt Clear Register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

eoi eoi read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 eoi

eoi : eoi
bits : 0 - 0 (1 bit)


prot_level

Protection level Register
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

prot_level prot_level read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 prot_level

prot_level : prot_level
bits : 0 - 2 (3 bit)


torr

Timeout Range Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

torr torr read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 top0 top1

top0 : top (lower half)
bits : 0 - 3 (4 bit)

top1 : top (upper half)
bits : 4 - 11 (8 bit)


ccvr

Current Counter Value Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ccvr ccvr read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

crr

Counter Restart Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

crr crr read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

comp_param_5

Component Parameters Register 5
address_offset : 0xE4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

comp_param_5 comp_param_5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 user_top_max

user_top_max : user_top_max
bits : 0 - 31 (32 bit)


comp_param_4

Component Parameters Register 4
address_offset : 0xE8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

comp_param_4 comp_param_4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 user_top_init_max

user_top_init_max : user_top_init_max
bits : 0 - 31 (32 bit)


comp_param_3

Component Parameters Register 3
address_offset : 0xEC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

comp_param_3 comp_param_3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 top_rst

top_rst : top_rst
bits : 0 - 31 (32 bit)


comp_param_2

Component Parameters Register 2
address_offset : 0xF0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

comp_param_2 comp_param_2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cnt_rst

cnt_rst : cnt_rst
bits : 0 - 31 (32 bit)


comp_param_1

Component Parameters Register 1
address_offset : 0xF4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

comp_param_1 comp_param_1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 always_en dflt_rmod dual_top hc_rmod hc_rpl hc_top use_fix_top pause apb_data_width dflt_rpl dflt_top dflt_top_init cnt_width

always_en : always_en
bits : 0 - 0 (1 bit)

dflt_rmod : dflt_rmod
bits : 1 - 2 (2 bit)

dual_top : dual_top
bits : 2 - 4 (3 bit)

hc_rmod : hc_rmod
bits : 3 - 6 (4 bit)

hc_rpl : hc_rpl
bits : 4 - 8 (5 bit)

hc_top : hc_top
bits : 5 - 10 (6 bit)

use_fix_top : use_fix_top
bits : 6 - 12 (7 bit)

pause : pause
bits : 7 - 14 (8 bit)

apb_data_width : apb_data_width
bits : 8 - 17 (10 bit)

dflt_rpl : dflt_rpl
bits : 10 - 22 (13 bit)

dflt_top : dflt_top
bits : 16 - 35 (20 bit)

dflt_top_init : dflt_top_init
bits : 20 - 43 (24 bit)

cnt_width : cnt_width
bits : 24 - 52 (29 bit)


comp_version

Component Version Register
address_offset : 0xF8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

comp_version comp_version read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

comp_type

Component Type Register
address_offset : 0xFC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

comp_type comp_type read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


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