\n
Config Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
start_int_enable : START_INT_ENABLE
bits : 0 - 0 (1 bit)
finish_int_enable : FINISH_INT_ENABLE
bits : 1 - 2 (2 bit)
ai_output_enable : AI_OUTPUT_ENABLE
bits : 2 - 4 (3 bit)
display_output_enable : DISPLAY_OUTPUT_ENABLE
bits : 3 - 6 (4 bit)
auto_enable : AUTO_ENABLE
bits : 4 - 8 (5 bit)
burst_size_4beats : BURST_SIZE_4BEATS
bits : 8 - 16 (9 bit)
format : FORMAT
bits : 9 - 19 (11 bit)
Enumeration:
0 : rgb
RGB_FORMAT
1 : yuv
YUV_FORMAT
3 : y
Y_FORMAT
End of enumeration elements list.
href_burst_num : HREF_BURST_NUM
bits : 12 - 31 (20 bit)
line_num : LINE_NUM
bits : 20 - 49 (30 bit)
CMOS Config Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
clk_div : CLK_DIV
bits : 0 - 7 (8 bit)
clk_enable : CLK_ENABLE
bits : 8 - 16 (9 bit)
reset : RESET
bits : 16 - 32 (17 bit)
power_down : POWER_DOWN
bits : 24 - 48 (25 bit)
SCCB Config Register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
byte_num : BYTE_NUM
bits : 0 - 1 (2 bit)
Enumeration:
1 : num2
BYTE_NUM_2
2 : num3
BYTE_NUM_3
3 : num4
BYTE_NUM_4
End of enumeration elements list.
scl_lcnt : SCL_LCNT
bits : 8 - 23 (16 bit)
scl_hcnt : SCL_HCNT
bits : 16 - 39 (24 bit)
rdata : RDATA
bits : 24 - 55 (32 bit)
access : read-only
SCCB Control Register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
device_address : DEVICE_ADDRESS
bits : 0 - 7 (8 bit)
reg_address : REG_ADDRESS
bits : 8 - 23 (16 bit)
wdata_byte0 : WDATA_BYTE0
bits : 16 - 39 (24 bit)
wdata_byte1 : WDATA_BYTE1
bits : 24 - 55 (32 bit)
AXI Register
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
gm_mlen : GM_MLEN
bits : 0 - 7 (8 bit)
Enumeration:
0 : byte1
GM_MLEN_1BYTE
3 : byte4
GM_MLEN_4BYTE
End of enumeration elements list.
STS Register
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
frame_start : FRAME_START
bits : 0 - 0 (1 bit)
frame_start_we : FRAME_START_WE
bits : 1 - 2 (2 bit)
frame_finish : FRAME_FINISH
bits : 8 - 16 (9 bit)
frame_finish_we : FRAME_FINISH_WE
bits : 9 - 18 (10 bit)
dvp_en : DVP_EN
bits : 16 - 32 (17 bit)
dvp_en_we : DVP_EN_WE
bits : 17 - 34 (18 bit)
sccb_en : SCCB_EN
bits : 24 - 48 (25 bit)
sccb_en_we : SCCB_EN_WE
bits : 25 - 50 (26 bit)
REVERSE
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RGB_ADDR
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
R_ADDR
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
G_ADDR
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
B_ADDR
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
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