PWRCON

CLKSEL0

CLKSEL1

CLKDIV

CLKSEL2

PLLCON

FRQDIV

AHBCLK

APBCLK

CLKSTATUS

XTL12M_EN : External Crystal Oscillator Control The bit default value is set by flash controller user configuration register config0 [26:24]. When the default clock source is from external crystal. The bit is auto set to "1" 1 = Crystal oscillation enable 0 = Crystal oscillation disable
bits : 0 - 0 (1 bit)
access : read-write

OSC22M_EN : Internal 22.1184 MHz Oscillator Control 1 = 22.1184 MHz Oscillation enable 0 = 22.1184 MHz Oscillation disable
bits : 2 - 2 (1 bit)
access : read-write

OSC10K_EN : Internal 10KHz Oscillator Control 1 = 10KHz Oscillation enable 0 = 10KHz Oscillation disable
bits : 3 - 3 (1 bit)
access : read-write

PD_WU_DLY : Enable the wake up delay counter. When the chip wakes up from power down mode, the clock control will delay certain clock cycles to wait system clock stable. The delayed clock cycle is 4096 clock cycles when chip work at external crystal (4 ~ 24MHz), and 256 clock cycles when chip work at 22.1184 MHz oscillator. 1 = Enable the clock cycle delay 0 = Disable the clock cycle delay
bits : 4 - 4 (1 bit)
access : read-write

PD_WU_INT_EN : Power down mode wake Up Interrupt Enable 0 = Disable 1 = Enable. The interrupt will occur when Power down mode (Deep Sleep Mode) wakeup.
bits : 5 - 5 (1 bit)
access : read-write

PD_WU_STS : Chip power down wake up status flag Set by "power down wake up", it indicates that resume from power down mode The flag is set if the GPIO(P0~P4), UART wakeup Write 1 to clear the bit Note: This bit is working only if PD_WU_INT_EN (PWRCON[5]) set to 1.
bits : 6 - 6 (1 bit)
access : read-write

PWR_DOWN_EN : System power down enable bit When set this bit "1", the chip power down mode is enabled and the chip power down active is depend on the PD_WAIT_CPU bit (a) if the PD_WAIT_CPU is "0" then the chip power down after the PWR_DOWN_EN bit set. (b) if the PD_WAIT_CPU is "1" then the chip keep active till the CPU sleep mode also active and then the chip power down When chip wake up from power down, this bit is auto cleared, user need to set this bit again for next power down. When in power down mode, external crystal (4~ 24MHz) and the 22.1184 MHz OSC will be disabled in this mode, but the 10 kHz OSC is not controlled by power down mode. When in power down mode, the PLL and system clock are disabled, and ignored the clock source selection. The clocks of peripheral are not controlled by power down mode, if the peripheral clock source is from 10 kHz oscillator. 1 = Chip enter the power down mode instant or wait CPU sleep command WFI 0 = Chip operate in normal mode or CPU in idle mode (sleep mode) because of WFI command
bits : 7 - 7 (1 bit)
access : read-write

PD_WAIT_CPU : This bit control the power down entry condition 1 = Chip entry power down mode when the both PWR_DOWN and CPU run WFI instruction. 0 = Chip entry power down mode when the PWR_DOWN bit is set to 1
bits : 8 - 8 (1 bit)
access : read-write

HCLK_S : HCLK clock source select. Note: Before clock switch the related clock sources (pre-select and new-select) must be turn on The 3-bit default value is reloaded with the value of Config0.CFOSC[26:24] in user configuration register in Flash controller by any reset. Therefore the default value is either 000b or 111b. These bits are protected bit, program this need an open lock sequence, write "59h","16h","88h" to address 0x5000_0100 to un-lock this bit. Reference the register REGWRPROT at address GCR_BA + 0x100 000 = clock source from external crystal clock (4 ~ 24MHz) 010 = clock source from PLL clock 011 = clock source from internal 10KHz oscillator clock 111 = clock source from internal 22.1184 MHz oscillator clock others = Reserved
bits : 0 - 2 (3 bit)
access : read-write

STCLK_S : MCU Cortex_M0 SysTick clock source select. These bits are protected bit, program this need an open lock sequence, write "59h","16h","88h" to address 0x5000_0100 to un-lock this bit. Reference the register REGWRPROT at address GCR_BA + 0x100 000 = Clock source from external crystal clock (4 ~ 24MHz) 010 = Clock source from external crystal clock (4 ~ 24MHz)/2 011 = clock source from HCLK/2 1xx = clock source from internal 22.1184 MHz oscillator clock/2
bits : 3 - 5 (3 bit)
access : read-write

WDT_S : Watchdog Timer clock source select. These bits are protected bit, program this need a open lock sequence, write "59h","16h","88h" to address 0x5000_0100 to un-lock this bit. Reference the register REGWRPROT at address GCR_BA + 0x100 00 = clock source from external crystal clock (4 ~ 24MHz). 10 = clock source from HCLK/2048 clock 11 = clock source from internal 10KHz oscillator clock
bits : 0 - 1 (2 bit)
access : read-write

ADC_S : ADC clock source select. 00 = clock source from external crystal clock (4 ~ 24MHz). 01 = clock source from PLL clock 1x = clock source from internal 22.1184 MHz oscillator clock
bits : 2 - 3 (2 bit)
access : read-write

TMR0_S : TIMER0 clock source select. 000 = clock source from external crystal clock (4 ~ 24MHz) 010 = clock source from HCLK 011 = clock source from external trigger 1xx = clock source from internal 22.1184 MHz oscillator clock
bits : 8 - 10 (3 bit)
access : read-write

TMR1_S : TIMER1 clock source select. 000 = clock source from external crystal clock (4 ~ 24MHz) 010 = clock source from HCLK 011 = clock source from external trigger 1xx = clock source from internal 22.1184 MHz oscillator clock
bits : 12 - 14 (3 bit)
access : read-write

TMR2_S : TIMER2 clock source select. 000 = clock source from external crystal clock (4 ~ 24MHz) 010 = clock source from HCLK 011 = clock source from external trigger 1xx = clock source from internal 22.1184 MHz oscillator clock
bits : 16 - 18 (3 bit)
access : read-write

TMR3_S : TIMER3 clock source select. 000 = clock source from external crystal clock (4 ~ 24MHz) 010 = clock source from HCLK 011 = clock source from external trigger 1xx = clock source from internal 22.1184 MHz oscillator clock
bits : 20 - 22 (3 bit)
access : read-write

UART_S : UART clock source select. 00 = clock source from external crystal clock (4 ~ 24MHz) 01 = clock source from PLL clock 1x = clock source from internal 22.1184 MHz oscillator clock
bits : 24 - 25 (2 bit)
access : read-write

PWM01_S : PWM0 and PWM1 clock source select. PWM0 and PWM1 uses the same Engine clock source, both of them with the same pre-scalar 00 = clock source from external crystal clock (4 ~ 24MHz) 10 = clock source from HCLK 11 = clock source from internal 22.1184 MHz oscillator clock
bits : 28 - 29 (2 bit)
access : read-write

PWM23_S : PWM2 and PWM3 clock source select. PWM2 and PWM3 uses the same Engine clock source, both of them with the same pre-scalar 00 = clock source from external crystal clock (4 ~ 24MHz) 10 = clock source from HCLK 11 = clock source from internal 22.1184 MHz oscillator clock
bits : 30 - 31 (2 bit)
access : read-write

HCLK_N : HCLK clock divide number from HCLK clock source The HCLK clock frequency = (HCLK clock source frequency) / (HCLK_N + 1)
bits : 0 - 3 (4 bit)
access : read-write

UART_N : UART clock divide number from UART clock source The UART clock frequency = (UART clock source frequency ) / (UART_N + 1)
bits : 8 - 11 (4 bit)
access : read-write

ADC_N : ADC clock divide number from ADC clock source The ADC clock frequency = (ADC clock source frequency ) / (ADC_N + 1)
bits : 16 - 23 (8 bit)
access : read-write

FRQDIV_S : Clock Divider Clock Source Select 00 = clock source from external crystal clock (4 ~ 24MHz) 10 = clock source from HCLK 11 = clock source from internal 22.1184 MHz oscillator clock
bits : 2 - 3 (2 bit)
access : read-write

PWM45_S : PWM4 and PWM5 clock source select. - PWM4 and PWM5 used the same Engine clock source, both of them with the same pre-scalar 00 = clock source from external crystal clock (4 ~ 24MHz) 10 = clock source from HCLK 11 = clock source from internal 22.1184 MHz oscillator clock
bits : 4 - 5 (2 bit)
access : read-write

PWM67_S : PWM6 and PWM7 clock source select. - PWM6 and PWM7 used the same Engine clock source, both of them with the same pre-scalar 00 = clock source from external crystal clock (4 ~ 24MHz) 10 = clock source from HCLK 11 = clock source from internal 22.1184 MHz oscillator clock
bits : 6 - 7 (2 bit)
access : read-write

FB_DV : PLL Feedback Divider Control Pins (PLL_F[8:0])
bits : 0 - 8 (9 bit)
access : read-write

IN_DV : PLL Input Divider Control Pins (PLL_R[4:0])
bits : 9 - 13 (5 bit)
access : read-write

OUT_DV : PLL Output Divider Control Pins (PLL_OD[1:0])
bits : 14 - 15 (2 bit)
access : read-write

PD : Power Down Mode. If set the IDLE bit "1" in PWRCON register, the PLL will enter power down mode too 0 = PLL is in normal mode (default) 1 = PLL is in power-down mode
bits : 16 - 16 (1 bit)
access : read-write

BP : PLL Bypass Control 0 = PLL is in normal mode (default) 1 = PLL clock output is same as clock input (XTALin)
bits : 17 - 17 (1 bit)
access : read-write

OE : PLL OE (FOUT enable) pin Control 0 = PLL FOUT enable 1 = PLL FOUT is fixed low
bits : 18 - 18 (1 bit)
access : read-write

PLL_SRC : PLL Source Clock Select 1 = PLL source clock from 22.1184 MHz oscillator 0 = PLL source clock from external crystal clock (4 ~ 24 MHz)
bits : 19 - 19 (1 bit)
access : read-write

FSEL : Divider Output Frequency Selection Bits The formula of output frequency is Fout = Fin/2(N+1), where Fin is the input clock frequency, Fout is the frequency of divider output clock, N is the 4-bit value of FSEL[3:0].
bits : 0 - 3 (4 bit)
access : read-write

DIVIDER_EN : Frequency Divider Enable Bit 0 = Disable Frequency Divider 1 = Enable Frequency Divider
bits : 4 - 4 (1 bit)
access : read-write

ISP_EN : Flash ISP Controller Clock Enable Control. 1 = To enable the Flash ISP controller clock. 0 = To disable the Flash ISP controller clock.
bits : 2 - 2 (1 bit)
access : read-write

EBI_EN : EBI Controller Clock Enable Control. 1 = To enable the EBI Controller clock. 0 = To disable the EBI Controller clock.
bits : 3 - 3 (1 bit)
access : read-write

WDT_EN : Watch Dog Timer Clock Enable. This bit is the protected bit, program this need a open lock sequence, write "59h","16h","88h" to address 0x5000_0100 to un-lock this bit. Reference the register REGWRPROT at address GCR_BA + 0x100 0 = Disable Watchdog Timer Clock 1 = Enable Watchdog Timer Clock
bits : 0 - 0 (1 bit)
access : read-write

TMR0_EN : Timer0 Clock Enable Control 0 = Disable Timer0 Clock 1 = Enable Timer0 Clock
bits : 2 - 2 (1 bit)
access : read-write

TMR1_EN : Timer1 Clock Enable Control 0 = Disable Timer1 Clock 1 = Enable Timer1 Clock
bits : 3 - 3 (1 bit)
access : read-write

TMR2_EN : Timer2 Clock Enable Control 0 = Disable Timer2 Clock 1 = Enable Timer2 Clock
bits : 4 - 4 (1 bit)
access : read-write

TMR3_EN : Timer3 Clock Enable Control 0 = Disable Timer3 Clock 1 = Enable Timer3 Clock
bits : 5 - 5 (1 bit)
access : read-write

FDIV_EN : Clock Divider Clock Enable Control 0 = Disable FDIV Clock 1 = Enable FDIV Clock
bits : 6 - 6 (1 bit)
access : read-write

I2C_EN : I2C Clock Enable Control. 0 = Disable I2C Clock 1 = Enable I2C Clock
bits : 8 - 8 (1 bit)
access : read-write

SPI0_EN : SPI0 Clock Enable Control. 0 = Disable SPI0 Clock 1 = Enable SPI0 Clock
bits : 12 - 12 (1 bit)
access : read-write

SPI1_EN : SPI1 Clock Enable Control. 0 = Disable SPI1 Clock 1 = Enable SPI1 Clock
bits : 13 - 13 (1 bit)
access : read-write

UART0_EN : UART0 Clock Enable Control. 1 = Enable UART0 clock 0 = Disable UART0 clock
bits : 16 - 16 (1 bit)
access : read-write

UART1_EN : UART1 Clock Enable Control. 1 = Enable UART1 clock 0 = Disable UART1 clock
bits : 17 - 17 (1 bit)
access : read-write

PWM01_EN : PWM_01 Clock Enable Control. 1 = Enable PWM01 clock 0 = Disable PWM01 clock
bits : 20 - 20 (1 bit)
access : read-write

PWM23_EN : PWM_23 Clock Enable Control. 1 = Enable PWM23 clock 0 = Disable PWM23 clock
bits : 21 - 21 (1 bit)
access : read-write

PWM45_EN : PWM_45 Clock Enable Control. 1 = Enable PWM45 clock 0 = Disable PWM45 clock
bits : 22 - 22 (1 bit)
access : read-write

PWM67_EN : PWM_67 Clock Enable Control. 1 = Enable PWM67 clock 0 = Disable PWM67 clock
bits : 23 - 23 (1 bit)
access : read-write

ADC_EN : Analog-Digital-Converter (ADC) Clock Enable Control. 1 = Enable ADC clock 0 = Disable ADC clock
bits : 28 - 28 (1 bit)
access : read-write

XTL12M_STB : XTL12M clock source stable flag 1 = External Crystal clock is stable 0 = External Crystal clock is not stable or not enable
bits : 0 - 0 (1 bit)
access : read-only

PLL_STB : PLL clock source stable flag 1 = PLL clock is stable 0 = PLL clock is not stable or not enable
bits : 2 - 2 (1 bit)
access : read-only

OSC10K_STB : OSC10K clock source stable flag 1 = OSC10K clock is stable 0 = OSC10K clock is not stable or not enable
bits : 3 - 3 (1 bit)
access : read-only

OSC22M_STB : OSC22M clock source stable flag 1 = OSC22M clock is stable 0 = OSC22M clock is not stable or not enable
bits : 4 - 4 (1 bit)
access : read-only

CLK_SW_FAIL : Clock switch fail flag 1 = Clock switch fail 0 = Clock switch success This bit will be set when target switch clock source is not stable. Write 1 to clear this bit to zero.
bits : 7 - 7 (1 bit)
access : read-write