PDID

REGWRPROT

BODCR

PORCR

P0_MFP

P1_MFP

P2_MFP

P3_MFP

RSTSRC

P4_MFP

IPRSTC1

IPRSTC2

PDID : This register reflects device part number code. S/W can read this register to identify which device is used.
bits : 0 - 31 (32 bit)
access : read-only

REGWRPROT : Register Write-Protected Code (Write Only) Some write-protected registers have to be disabled the protected function by writing the sequence value "59h", "16h", "88h" to this field. After this sequence is completed, the REGPROTDIS bit will be set to 1 and write-protected registers can be normal write.
bits : 0 - 7 (8 bit)
access : write-only

REGPROTDIS : Register Write-Protected Disable index (Read only) 1 = Protection is disabled for writing protected registers 0 = Protection is enabled for writing protected registers. Any write to the protected register is ignored. The Write-Protected registers list are below table: Registers Address Note IPRSTC1 0x5000_0008 None BODCR 0x5000_0018 None PORCR 0x5000_001C None PWRCON 0x5000_0200 bit[6] is not protected for power wake-up interrupt clear APBCLK bit[0] 0x5000_0208 bit[0] is watch dog clock enable CLKSEL0 0x5000_0210 HCLK and CPU STCLK clock source select CLK_SEL1 bit[1:0] 0x5000_0214 Watch dog clock source select ISPCON 0x5000_C000 Flash ISP Control register WTCR 0x4000_4000 None FATCON 0x5000_C018 None
bits : 0 - 0 (1 bit)
access : read-only

BOD_EN : Brown Out Detector Enable (initiated & write-protected bit) The default value is set by flash controller user configuration register config0 bit[23] 1= Brown Out Detector function is enabled 0= Brown Out Detector function is disabled
bits : 0 - 0 (1 bit)
access : read-write

BOD_VL : Brown Out Detector Threshold Voltage Selection (initiated & write-protected bit) The default value is set by flash controller user configuration register config0 bit[22:21] BOV_VL[1] BOV_VL[0] Brown out voltage 1 1 4.5V 1 0 3.8V 0 1 2.7V 0 0 2.2V
bits : 1 - 2 (2 bit)
access : read-write

BOD_RSTEN : Brown Out Reset Enable (initiated & write-protected bit) 1= Enable the Brown Out "RESET" function, when the Brown Out Detector function is enable and the detected voltage is lower than the threshold then assert a signal to reset the chip The default value is set by flash controller user configuration register config0 bit[20] 0= Enable the Brown Out "INTERRUPT" function, when the Brown Out Detector function is enable and the detected voltage is lower than the threshold then assert a signal to interrupt the MCU Cortex-M0 When the BOD_EN is enabled and the interrupt is assert, the interrupt will keep till to the BOD_EN set to "0". The interrupt for CPU can be blocked by disable the NVIC in CPU for BOD interrupt or disable the interrupt source by disable the BOD_EN and then re-enable the BOD_EN function if the BOD function is required
bits : 3 - 3 (1 bit)
access : read-write

BOD_INTF : Brown Out Detector Interrupt Flag 1= When Brown Out Detector detects the VDD is dropped through the voltage of BOD_VL setting or the VDD is raised up through the voltage of BOD_VL setting, this bit is set to "1" and the brown out interrupt is requested if brown out interrupt is enabled. 0= Brown Out Detector does not detect any voltage draft at VDD down through or up through the voltage of BOD_VL setting.
bits : 4 - 4 (1 bit)
access : read-write

BOD_LPM : Brown Out Detector Low power Mode (write-protected bit) 1= Enable the BOD low power mode 0= BOD operate in normal mode (default) The BOD consumes about 100uA in normal mode, the low power mode can reduce the current to about 1/10 but slow the BOD response.
bits : 5 - 5 (1 bit)
access : read-write

BOD_OUT : The status for Brown Out Detector output state 1= Brown Out Detector status output is 1, the detected voltage is lower than BOD_VL setting. If the BOD_EN is "0"(disabled), this bit always response "0" 0= Brown Out Detector status output is 0, the detected voltage is higher than BOD_VL setting
bits : 6 - 6 (1 bit)
access : read-only

LVR_EN : Low Voltage Reset Enable (write-protected bit) The LVR function reset the chip when the input power voltage is lower than LVR circuit setting. LVR function is enabled in default. 1= Enabled Low Voltage Reset function - After enable the bit, the LVR function will active with 100uS delay for LVR output stable.(default). 0= Disabled Low Voltage Reset function
bits : 7 - 7 (1 bit)
access : read-write

POR_DIS_CODE : The register is used for the Power-On-Reset enable control. When power on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again. If set the POR_DIS_CODE equal to 0x5AA5, the POR reset function will be disabled and the POR function will re-active till the power voltage is lower to set the POR_DIS_CODE to another value or reset by chip other reset function. Include: PIN reset, Watch dog, LVR reset BOD reset, ICE reset command and the software-chip reset function This register is the protected register, program this need an open lock sequence, write "59h","16h","88h" to address 0x5000_0100 to un-lock this bit. Reference the register REGWRPROT at address GCR_BA + 0x100
bits : 0 - 15 (16 bit)
access : read-write

P0_MFP : P0 multiple function Selection The pin function of P0 is depending on P0_MFP and P0_ALT. Refer to P0_ALT descriptions in detail.
bits : 0 - 7 (8 bit)
access : read-write

P0_ALT0 : P0.0 alternate function Selection The pin function of P0.0 is depend on P0_MFP[0] and P0_ALT[0]. P0_ALT[0] P0_MFP[0] P0.0function 0 0 P0.0 0 1 AD0(EBI) 1 0 CTS1(UART1) 1 1 Reserved
bits : 8 - 8 (1 bit)
access : read-write

P0_ALT1 : P0.1 alternate function Selection The pin function of P0.1 is depend on P0_MFP[1] and P0_ALT[1]. P0_ALT[1] P0_MFP[1] P0.1function 0 0 P0.1 0 1 AD1(EBI) 1 0 RTS1(UART1) 1 1 Reserved
bits : 9 - 9 (1 bit)
access : read-write

P0_ALT2 : P0.2 alternate function Selection The pin function of P0.2 is depend on P0_MFP[2] and P0_ALT[2]. P0_ALT[2] P0_MFP[2] P0.2function 0 0 P0.2 0 1 AD2(EBI) 1 0 CTS0(UART0) 1 1 Reserved
bits : 10 - 10 (1 bit)
access : read-write

P0_ALT3 : P0.3 alternate function Selection The pin function of P0.3 is depend on P0_MFP[3] and P0_ALT[3]. P0_ALT[3] P0_MFP[3] P0.3function 0 0 P0.3 0 1 AD3(EBI) 1 0 RTS0(UART0) 1 1 Reserved
bits : 11 - 11 (1 bit)
access : read-write

P0_ALT4 : P0.4 alternate function Selection The pin function of P0.4 is depend on P0_MFP[4] and P0_ALT[4]. P0_ALT[4] P0_MFP[4] P0.4function 0 0 P0.4 0 1 AD4(EBI) 1 0 SPISS1(SPI1) 1 1 Reserved
bits : 12 - 12 (1 bit)
access : read-write

P0_ALT5 : P0.5 alternate function Selection The pin function of P0.5 is depend on P0_MFP[5] and P0_ALT[5]. P0_ALT[5] P0_MFP[5] P0.5 function 0 0 P0.5 0 1 AD5(EBI) 1 0 MOSI_1(SPI1) 1 1 Reserved
bits : 13 - 13 (1 bit)
access : read-write

P0_ALT6 : P0.6 alternate function Selection The pin function of P0.6 is depend on P0_MFP[6] and P0_ALT[6]. P0_ALT[6] P0_MFP[6] P0.6 function 0 0 P0.6 0 1 AD6(EBI) 1 0 MISO_1(SPI1) 1 1 Reserved
bits : 14 - 14 (1 bit)
access : read-write

P0_ALT7 : P0.7 alternate function Selection The pin function of P0.7 is depend on P0_MFP[7] and P0_ALT[7]. P0_ALT[7] P0_MFP[7] P0.7 function 0 0 P0.7 0 1 AD7(EBI) 1 0 SPICLK1(SPI1) 1 1 Reserved
bits : 15 - 15 (1 bit)
access : read-write

P0_TYPEn : P0[7:0] input Schmitt Trigger function Enable 1= P0[7:0] I/O input Schmitt Trigger function enable 0= P0[7:0] I/O input Schmitt Trigger function disable
bits : 16 - 23 (8 bit)
access : read-write

P1_MFP : P1 multiple function Selection The pin function of P1 is depending on P1_MFP and P1_ALT. Refer to P1_ALT descriptions in detail.
bits : 0 - 7 (8 bit)
access : read-write

P1_ALT0 : P1.0 alternate function Selection The pin function of P1.0 is depend on P1_MFP[0] and P1_ALT[0]. P1_ALT[0] P1_MFP[0] P1.0function 0 0 P1.0 0 1 AIN0(ADC) 1 0 T2(Timer2) 1 1 Reserved
bits : 8 - 8 (1 bit)
access : read-write

P1_ALT1 : P1.1 alternate function Selection The pin function of P1.1 is depend on P1_MFP[1] and P1_ALT[1]. P1_ALT[1] P1_MFP[1] P1.1function 0 0 P1.1 0 1 AIN1(ADC) 1 0 T3(Timer3) 1 1 Reserved
bits : 9 - 9 (1 bit)
access : read-write

P1_ALT2 : P1.2 alternate function Selection The pin function of P1.2 is depend on P1_MFP[2] and P1_ALT[2]. P1_ALT[2] P1_MFP[2] P1.2function 0 0 P1.2 0 1 AIN2(ADC) 1 0 RXD1(UART1) 1 1 Reserved
bits : 10 - 10 (1 bit)
access : read-write

P1_ALT3 : P1.3 alternate function Selection The pin function of P1.3 is depend on P1_MFP[3] and P1_ALT[3]. P1_ALT[3] P1_MFP[3] P1.3function 0 0 P1.3 0 1 AIN3(ADC) 1 0 TXD1(UART1) 1 1 Reserved
bits : 11 - 11 (1 bit)
access : read-write

P1_ALT4 : P1.4 alternate function Selection The pin function of P1.4 is depend on P1_MFP[4] and P1_ALT[4]. P1_ALT[4] P1_MFP[4] P1.4function 0 0 P1.4 0 1 AIN4(ADC) 1 0 SPISS0(SPI0) 1 1 Reserved
bits : 12 - 12 (1 bit)
access : read-write

P1_ALT5 : P1.5 alternate function Selection The pin function of P1.5 is depend on P1_MFP[5] and P1_ALT[5]. P1_ALT[5] P1_MFP[5] P1.5 function 0 0 P1.5 0 1 AIN5(ADC) 1 0 MOSI_0(SPI0) 1 1 Reserved
bits : 13 - 13 (1 bit)
access : read-write

P1_ALT6 : P1.6 alternate function Selection The pin function of P1.6 is depend on P1_MFP[6] and P1_ALT[6]. P1_ALT[6] P1_MFP[6] P1.6 function 0 0 P1.6 0 1 AIN6(ADC) 1 0 MISO_0(SPI0) 1 1 Reserved
bits : 14 - 14 (1 bit)
access : read-write

P1_ALT7 : P1.7 alternate function Selection The pin function of P1.7 is depend on P1_MFP[7] and P1_ALT[7]. P1_ALT[7] P1_MFP[7] P1.7 function 0 0 P1.7 0 1 AIN7(ADC) 1 0 SPICLK0(SPI0) 1 1 Reserved
bits : 15 - 15 (1 bit)
access : read-write

P1_TYPEn : P1[7:0] input Schmitt Trigger function Enable 1= P1[7:0] I/O input Schmitt Trigger function enable 0= P1[7:0] I/O input Schmitt Trigger function disable
bits : 16 - 23 (8 bit)
access : read-write

P2_MFP : P2 multiple function Selection The pin function of P2 is depending on P2_MFP and P2_ALT. Refer to P2_ALT descriptions in detail.
bits : 0 - 7 (8 bit)
access : read-write

P2_ALT0 : P2.0 alternate function Selection The pin function of P2.0 is depend on P2_MFP[0] and P2_ALT[0]. P2_ALT[0] P2_MFP[0] P2.0function 0 0 P2.0 0 1 AD8(EBI) 1 0 PWM0(PWM generator 0) 1 1 Reserved
bits : 8 - 8 (1 bit)
access : read-write

P2_ALT1 : P2.1 alternate function Selection The pin function of P2.1 is depend on P2_MFP[1] and P2_ALT[1]. P2_ALT[1] P2_MFP[1] P2.1function 0 0 P2.1 0 1 AD9(EBI) 1 0 PWM1(PWM generator 0) 1 1 Reserved
bits : 9 - 9 (1 bit)
access : read-write

P2_ALT2 : P2.2 alternate function Selection The pin function of P2.2 is depend on P2_MFP[2] and P2_ALT[2]. P2_ALT[2] P2_MFP[2] P2.2function 0 0 P2.2 0 1 AD10(EBI) 1 0 PWM2(PWM generator 2) 1 1 Reserved
bits : 10 - 10 (1 bit)
access : read-write

P2_ALT3 : P2.3 alternate function Selection The pin function of P2.3 is depend on P2_MFP[3] and P2_ALT[3]. P2_ALT[3] P2_MFP[3] P2.3function 0 0 P2.3 0 1 AD11(EBI) 1 0 PWM3(PWM generator 2) 1 1 Reserved
bits : 11 - 11 (1 bit)
access : read-write

P2_ALT4 : P2.4 alternate function Selection The pin function of P2.4 is depend on P2_MFP[4] and P2_ALT[4]. P2_ALT[4] P2_MFP[4] P0.4function 0 0 P0.4 0 1 AD12(EBI) 1 0 PWM4(PWM generator 4) 1 1 Reserved
bits : 12 - 12 (1 bit)
access : read-write

P2_ALT5 : P2.5 alternate function Selection The pin function of P2.5 is depend on P2_MFP[5] and P2_ALT[5]. P2_ALT[5] P2_MFP[5] P2.5 function 0 0 P2.5 0 1 AD13(EBI) 1 0 PWM5(PWM generator 4) 1 1 Reserved
bits : 13 - 13 (1 bit)
access : read-write

P2_ALT6 : P2.6 alternate function Selection The pin function of P2.6 is depend on P2_MFP[6] and P2_ALT[6]. P2_ALT[6] P2_MFP[6] P2.6 function 0 0 P2.6 0 1 AD14(EBI) 1 0 PWM6(PWM generator 6) 1 1 Reserved
bits : 14 - 14 (1 bit)
access : read-write

P2_ALT7 : P2.7 alternate function Selection The pin function of P2.7 is depend on P2_MFP[7] and P2_ALT[7]. P2_ALT[7] P2_MFP[7] P2.7 function 0 0 P2.7 0 1 AD15(EBI) 1 0 PWM7(PWM generator 6) 1 1 Reserved
bits : 15 - 15 (1 bit)
access : read-write

P2_TYPEn : P2[7:0] input Schmitt Trigger function Enable 1= P2[7:0] I/O input Schmitt Trigger function enable 0= P2[7:0] I/O input Schmitt Trigger function disable
bits : 16 - 23 (8 bit)
access : read-write

P3_MFP : P3 multiple function Selection The pin function of P3 is depending on P3_MFP and P3_ALT. Refer to P3_ALT descriptions in detail.
bits : 0 - 7 (8 bit)
access : read-write

P3_ALT0 : P3.0 alternate function Selection The pin function of P3.0 is depend on P3_MFP[0] and P3_ALT[0]. P3_ALT[0] P3_MFP[0] P3.0function 0 0 P3.0 0 1 RXD(UART0) 1 x Reserved
bits : 8 - 8 (1 bit)
access : read-write

P3_ALT1 : P3.1 alternate function Selection The pin function of P3.1 is depend on P3_MFP[1] and P3_ALT[1]. P3_ALT[1] P3_MFP[1] P3.1function 0 0 P3.1 0 1 TXD(UART0) 1 x Reserved
bits : 9 - 9 (1 bit)
access : read-write

P3_ALT2 : P3.2 alternate function Selection The pin function of P3.2 is depend on P3_MFP[2] and P3_ALT[2]. P3_ALT[2] P3_MFP[2] P3.2function 0 0 P3.2 0 1 /INT0 1 1 Reserved
bits : 10 - 10 (1 bit)
access : read-write

P3_ALT3 : P3.3 alternate function Selection The pin function of P3.3 is depend on P3_MFP[3] and P3_ALT[3]. P3_ALT[3] P3_MFP[3] P3.3function 0 0 P3.3 0 1 /INT1 1 0 MCLK(EBI) 1 x Reserved
bits : 11 - 11 (1 bit)
access : read-write

P3_ALT4 : P3.4 alternate function Selection The pin function of P3.4 is depend on P3_MFP[4] and P3_ALT[4]. P3_ALT[4] P3_MFP[4] P3.4function 0 0 P3.4 0 1 T0(Timer0) 1 0 SDA(I2C) 1 1 Reserved
bits : 12 - 12 (1 bit)
access : read-write

P3_ALT5 : P3.5 alternate function Selection The pin function of P3.5 is depend on P3_MFP[5] and P3_ALT[5]. P3_ALT[5] P3_MFP[5] P3.5 function 0 0 P3.5 0 1 T1(Timer1) 1 0 SCL(I2C) 1 1 Reserved
bits : 13 - 13 (1 bit)
access : read-write

P3_ALT6 : P3.6 alternate function Selection The pin function of P3.6 is depend on P3_MFP[6] and P3_ALT[6]. P3_ALT[6] P3_MFP[6] P3.6 function 0 0 P3.6 0 1 WR(EBI) 1 0 CKO(Clock Driver output) 1 1 Reserved
bits : 14 - 14 (1 bit)
access : read-write

P3_ALT7 : P3.7 alternate function Selection The pin function of P3.7 is depend on P3_MFP[7] and P3_ALT[7]. P3_ALT[7] P3_MFP[7] P3.7 function 0 0 P3.7 0 1 RD(EBI) 1 x Reserved
bits : 15 - 15 (1 bit)
access : read-write

P3_TYPEn : P3[7:0] input Schmitt Trigger function Enable 1= P3[7:0] I/O input Schmitt Trigger function enable 0= P3[7:0] I/O input Schmitt Trigger function disable
bits : 16 - 23 (8 bit)
access : read-write

RSTS_POR : The RSTS_POR flag is set by the "reset signal" which is from the Power-On Reset (POR) module or bit CHIP_RST (IPRSTC1[0]) is set, to indicate the previous reset source. 1= The Power-On-Reset(POR) or CHIP_RST=1 had issued the reset signal to reset the system. 0= No reset from POR This bit is cleared by writing 1 to itself.
bits : 0 - 0 (1 bit)
access : read-write

RSTS_RESET : The RSTS_RESET flag is set by the "reset signal" from the /RESET pin to indicate the previous reset source. 1= The Pin /RESET had issued the reset signal to reset the system. 0= No reset from Pin /RESET This bit is cleared by writing 1 to itself.
bits : 1 - 1 (1 bit)
access : read-write

RSTS_WDT : The RSTS_WDT flag is set by the "reset signal" from the Watch Dog Timer to indicate the previous reset source. 1= The Watch Dog Timer had issued the reset signal to reset the system. 0= No reset from Watch-Dog This bit is cleared by writing 1 to itself.
bits : 2 - 2 (1 bit)
access : read-write

RSTS_LVR : The RSTS_LVR flag is set by the "reset signal" from the Low-Voltage-Reset module to indicate the previous reset source. 1= The LVR module had issued the reset signal to reset the system. 0= No reset from LVR This bit is cleared by writing 1 to itself.
bits : 3 - 3 (1 bit)
access : read-write

RSTS_BOD : The RSTS_BOD flag is set by the "reset signal" from the Brown-Out-Detected module to indicate the previous reset source. 1= The Brown-Out-Detected module had issued the reset signal to reset the system. 0= No reset from BOD This bit is cleared by writing 1 to itself.
bits : 4 - 4 (1 bit)
access : read-write

RSTS_MCU : The RSTS_MCU flag is set by the "reset signal" from the MCU Cortex_M0 kernel to indicate the previous reset source. 1= The MCU Cortex_M0 had issued the reset signal to reset the system by software writing 1 to bit SYSRESTREQ(AIRCR[2], Application Interrupt and Reset Control Register) in system control registers of Cortex_M0 kernel. 0= No reset from MCU This bit is cleared by writing 1 to itself.
bits : 5 - 5 (1 bit)
access : read-write

RSTS_CPU : The RSTS_CPU flag is set by hardware if software writes CPU_RST (IPRSTC1[1]) with a "1" to rest Cortex-M0 CPU kernel and Flash memory controller(FMC). 1= The Cortex-M0 CPU kernel and FMC are reset by software set CPU_RST to 1. 0= No reset from CPU This bit is cleared by writing 1 to itself.
bits : 7 - 7 (1 bit)
access : read-write

P4_MFP : P4 multiple function Selection The pin function of P4 is depending on P4_MFP and P4_ALT. Refer to P4_ALT descriptions in detail.
bits : 0 - 7 (8 bit)
access : read-write

P4_ALT0 : P4.0 alternate function Selection The pin function of P4.0 is depend on P4_MFP[0] and P4_ALT[0]. P4_ALT[0] P4_MFP[0] P4.0function 0 0 P4.0 0 1 PWM0(PWM generator 0) 1 x Reserved
bits : 8 - 8 (1 bit)
access : read-write

P4_ALT1 : P4.1 alternate function Selection The pin function of P4.1 is depend on P4_MFP[1] and P4_ALT[1]. P4_ALT[1] P4_MFP[1] P4.1function 0 0 P4.1 0 1 PWM1(PWM generator 0) 1 x Reserved
bits : 9 - 9 (1 bit)
access : read-write

P4_ALT2 : P4.2 alternate function Selection The pin function of P4.2 is depend on P4_MFP[2] and P4_ALT[2]. P4_ALT[2] P4_MFP[2] P4.2function 0 0 P4.2 0 1 PWM2(PWM generator 2) 1 x Reserved
bits : 10 - 10 (1 bit)
access : read-write

P4_ALT3 : P4.3 alternate function Selection The pin function of P4.3 is depend on P4_MFP[3] and P4_ALT[3]. P4_ALT[3] P4_MFP[3] P4.3function 0 0 P4.3 0 1 PWM3(PWM generator 2) 1 x Reserved
bits : 11 - 11 (1 bit)
access : read-write

P4_ALT4 : P4.4 alternate function Selection The pin function of P4.4 is depend on P4_MFP[4] and P4_ALT[4]. P4_ALT[4] P4_MFP[4] P4.4function 0 0 P4.4 0 1 /CS(EBI) 1 x Reserved
bits : 12 - 12 (1 bit)
access : read-write

P4_ALT5 : P4.5 alternate function Selection The pin function of P4.5 is depend on P4_MFP[5] and P4_ALT[5]. P4_ALT[5] P4_MFP[5] P4.5 function 0 0 P4.5 0 1 ALE(EBI) 1 x Reserved
bits : 13 - 13 (1 bit)
access : read-write

P4_ALT6 : P4.6 alternate function Selection The pin function of P4.6 is depend on P4_MFP[6] and P4_ALT[6]. P4_ALT[6] P4_MFP[6] P4.6 function 0 0 P4.6 0 1 ICE_CLK(ICE) 1 x Reserved
bits : 14 - 14 (1 bit)
access : read-write

P4_ALT7 : P4.7 alternate function Selection The pin function of P4.7 is depend on P4_MFP[7] and P4_ALT[7]. P4_ALT[7] P4_MFP[7] P4.7 function 0 0 P4.7 0 1 ICE_DAT(ICE) 1 x Reserved
bits : 15 - 15 (1 bit)
access : read-write

P4_TYPEn : P4[7:0] input Schmitt Trigger function Enable 1= P4[7:0] I/O input Schmitt Trigger function enable 0= P4[7:0] I/O input Schmitt Trigger function disable
bits : 16 - 23 (8 bit)
access : read-write

CHIP_RST : CHIP one shot reset. Set this bit will reset the CHIP, including CPU kernel and all peripherals, and this bit will automatically return to "0" after the 2 clock cycles. The CHIP_RST is same as the POR reset , all the chip module is reset and the chip setting from flash are also reload This bit is the protected bit, program this need an open lock sequence, write "59h","16h","88h" to address 0x5000_0100 to un-lock this bit. Reference the register REGWRPROT at address GCR_BA + 0x100 0= Normal 1= Reset CHIP
bits : 0 - 0 (1 bit)
access : read-write

CPU_RST : CPU kernel one shot reset. Set this bit will reset the Cortex-M0 CPU kernel and Flash memory controller (FMC). This bit will automatically return to "0" after the 2 clock cycles This bit is the protected bit, program this need an open lock sequence, write "59h","16h","88h" to address 0x5000_0100 to un-lock this bit. Reference the register REGWRPROT at address GCR_BA + 0x100 0= Normal 1= Reset CPU
bits : 1 - 1 (1 bit)
access : read-write

EBI_RST : EBI Controller Reset Set these bit "1" will generate a reset signal to the EBI. User need to set this bit to "0" to release from the reset state This bit is the protected bit, program this need an open lock sequence, write "59h","16h","88h" to address 0x5000_0100 to un-lock this bit. Reference the register REGWRPROT at address GCR_BA + 0x100 0= Normal operation 1= EBI IP reset
bits : 3 - 3 (1 bit)
access : read-write

GPIO_RST : GPIO (P0~P4) controller Reset 0= GPIO controller normal operation 1= GPIO controller reset
bits : 1 - 1 (1 bit)
access : read-write

TMR0_RST : Timer0 controller Reset 0= Timer0 controller normal operation 1= Timer0 controller reset
bits : 2 - 2 (1 bit)
access : read-write

TMR1_RST : Timer1 controller Reset 0= Timer1 controller normal operation 1= Timer1 controller reset
bits : 3 - 3 (1 bit)
access : read-write

TMR2_RST : Timer2 controller Reset 0= Timer2 controller normal operation 1= Timer2 controller reset
bits : 4 - 4 (1 bit)
access : read-write

TMR3_RST : Timer3 controller Reset 0= Timer3 controller normal operation 1= Timer3 controller reset
bits : 5 - 5 (1 bit)
access : read-write

I2C_RST : I2C controller Reset 0= I2C controller normal operation 1= I2C controller reset
bits : 8 - 8 (1 bit)
access : read-write

SPI0_RST : SPI0 controller Reset 0= SPI0 controller normal operation 1= SPI0 controller reset
bits : 12 - 12 (1 bit)
access : read-write

SPI1_RST : SPI1 controller Reset 0= SPI1 controller normal operation 1= SPI1 controller reset
bits : 13 - 13 (1 bit)
access : read-write

UART0_RST : UART0 controller Reset 0= UART0 controller Normal operation 1= UART0 controller reset
bits : 16 - 16 (1 bit)
access : read-write

UART1_RST : UART1 controller Reset 0 = UART1 controller normal operation 1 = UART1 controller reset
bits : 17 - 17 (1 bit)
access : read-write

PWM03_RST : PWM0~3 controller Reset 0= PWM0~3 controller normal operation 1= PWM0~3 controller reset
bits : 20 - 20 (1 bit)
access : read-write

PWM47_RST : PWM4~7 controller Reset 0= PWM4~7 controller normal operation 1= PWM4~7 controller reset
bits : 21 - 21 (1 bit)
access : read-write

ADC_RST : ADC Controller Reset 0= ADC controller normal operation 1= ADC controller reset
bits : 28 - 28 (1 bit)
access : read-write