PMD

PIN

DBEN

IMD

IEN

ISRC

OFFD

DOUT

DMASK

PMD0 : P0 I/O Pin[0] Mode Control Determine each I/O type of P0 pins 00 = P0[0] pin is in INPUT mode. 01 = P0[0] pin is in OUTPUT mode. 10 = P0[0] pin is in Open-Drain mode. 11 = P0[0] pin is in Quasi-bidirectional mode.
bits : 0 - 1 (2 bit)
access : read-write

PMD1 : P0 I/O Pin[1] Mode Control Determine each I/O type of P0 pins 00 = P0[1] pin is in INPUT mode. 01 = P0[1] pin is in OUTPUT mode. 10 = P0[1] pin is in Open-Drain mode. 11 = P0[1] pin is in Quasi-bidirectional mode.
bits : 2 - 3 (2 bit)
access : read-write

PMD2 : P0 I/O Pin[2] Mode Control Determine each I/O type of P0 pins 00 = P0[2] pin is in INPUT mode. 01 = P0[2] pin is in OUTPUT mode. 10 = P0[2] pin is in Open-Drain mode. 11 = P0[2] pin is in Quasi-bidirectional mode.
bits : 4 - 5 (2 bit)
access : read-write

PMD3 : P0 I/O Pin[3] Mode Control Determine each I/O type of P0 pins 00 = P0[3] pin is in INPUT mode. 01 = P0[3] pin is in OUTPUT mode. 10 = P0[3] pin is in Open-Drain mode. 11 = P0[3] pin is in Quasi-bidirectional mode.
bits : 6 - 7 (2 bit)
access : read-write

PMD4 : P0 I/O Pin[4] Mode Control Determine each I/O type of P0 pins 00 = P0[4] pin is in INPUT mode. 01 = P0[4] pin is in OUTPUT mode. 10 = P0[4] pin is in Open-Drain mode. 11 = P0[4] pin is in Quasi-bidirectional mode.
bits : 8 - 9 (2 bit)
access : read-write

PMD5 : P0 I/O Pin[5] Mode Control Determine each I/O type of P0 pins 00 = P0[5] pin is in INPUT mode. 01 = P0[5] pin is in OUTPUT mode. 10 = P0[5] pin is in Open-Drain mode. 11 = P0[5] pin is in Quasi-bidirectional mode.
bits : 10 - 11 (2 bit)
access : read-write

PMD6 : P0 I/O Pin[6] Mode Control Determine each I/O type of P0 pins 00 = P0[6] pin is in INPUT mode. 01 = P0[6] pin is in OUTPUT mode. 10 = P0[6] pin is in Open-Drain mode. 11 = P0[6] pin is in Quasi-bidirectional mode.
bits : 12 - 13 (2 bit)
access : read-write

PMD7 : P0 I/O Pin[7] Mode Control Determine each I/O type of P0 pins 00 = P0[7] pin is in INPUT mode. 01 = P0[7] pin is in OUTPUT mode. 10 = P0[7] pin is in Open-Drain mode. 11 = P0[7] pin is in Quasi-bidirectional mode.
bits : 14 - 15 (2 bit)
access : read-write

PIN0 : P0 Pin Values The value read from each of these bit reflects the actual status of the respective P0 Pin[0].
bits : 0 - 0 (1 bit)
access : read-only

PIN1 : P0 Pin Values The value read from each of these bit reflects the actual status of the respective P0 Pin[1].
bits : 1 - 1 (1 bit)
access : read-only

PIN2 : P0 Pin Values The value read from each of these bit reflects the actual status of the respective P0 Pin[2].
bits : 2 - 2 (1 bit)
access : read-only

PIN3 : P0 Pin Values The value read from each of these bit reflects the actual status of the respective P0 Pin[3].
bits : 3 - 3 (1 bit)
access : read-only

PIN4 : P0 Pin Values The value read from each of these bit reflects the actual status of the respective P0 Pin[4].
bits : 4 - 4 (1 bit)
access : read-only

PIN5 : P0 Pin Values The value read from each of these bit reflects the actual status of the respective P0 Pin[5].
bits : 5 - 5 (1 bit)
access : read-only

PIN6 : P0 Pin Values The value read from each of these bit reflects the actual status of the respective P0 Pin[6].
bits : 6 - 6 (1 bit)
access : read-only

PIN7 : P0 Pin Values The value read from each of these bit reflects the actual status of the respective P0 Pin[7].
bits : 7 - 7 (1 bit)
access : read-only

DBEN0 : P0 Input Signal De-bounce Enable DBEN[0] used to enable the de-bounce function for each corresponding bit. if the input signal pulse width can't be sampled by continuous two de-bounce sample cycle. The input signal transition is seen as the signal bounce and will not trigger the interrupt. The DBEN[0] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt 0 = The bit[0] de-bounce function is disabled 1 = The bit[0] de-bounce function is enabled The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 0 - 0 (1 bit)
access : read-write

DBEN1 : P0 Input Signal De-bounce Enable DBEN[1] used to enable the de-bounce function for each corresponding bit. if the input signal pulse width can't be sampled by continuous two de-bounce sample cycle. The input signal transition is seen as the signal bounce and will not trigger the interrupt. The DBEN[1] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt 0 = The bit[1] de-bounce function is disabled 1 = The bit[1] de-bounce function is enabled The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 1 - 1 (1 bit)
access : read-write

DBEN2 : P0 Input Signal De-bounce Enable DBEN[2] used to enable the de-bounce function for each corresponding bit. if the input signal pulse width can't be sampled by continuous two de-bounce sample cycle. The input signal transition is seen as the signal bounce and will not trigger the interrupt. The DBEN[2] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt 0 = The bit[2] de-bounce function is disabled 1 = The bit[2] de-bounce function is enabled The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 2 - 2 (1 bit)
access : read-write

DBEN3 : P0 Input Signal De-bounce Enable DBEN[3] used to enable the de-bounce function for each corresponding bit. if the input signal pulse width can't be sampled by continuous two de-bounce sample cycle. The input signal transition is seen as the signal bounce and will not trigger the interrupt. The DBEN[3] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt 0 = The bit[3] de-bounce function is disabled 1 = The bit[3] de-bounce function is enabled The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 3 - 3 (1 bit)
access : read-write

DBEN4 : P0 Input Signal De-bounce Enable DBEN[4] used to enable the de-bounce function for each corresponding bit. if the input signal pulse width can't be sampled by continuous two de-bounce sample cycle. The input signal transition is seen as the signal bounce and will not trigger the interrupt. The DBEN[4] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt 0 = The bit[4] de-bounce function is disabled 1 = The bit[4] de-bounce function is enabled The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 4 - 4 (1 bit)
access : read-write

DBEN5 : P0 Input Signal De-bounce Enable DBEN[5] used to enable the de-bounce function for each corresponding bit. if the input signal pulse width can't be sampled by continuous two de-bounce sample cycle. The input signal transition is seen as the signal bounce and will not trigger the interrupt. The DBEN[5] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt 0 = The bit[5] de-bounce function is disabled 1 = The bit[5] de-bounce function is enabled The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 5 - 5 (1 bit)
access : read-write

DBEN6 : P0 Input Signal De-bounce Enable DBEN[6] used to enable the de-bounce function for each corresponding bit. if the input signal pulse width can't be sampled by continuous two de-bounce sample cycle. The input signal transition is seen as the signal bounce and will not trigger the interrupt. The DBEN[6] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt 0 = The bit[6] de-bounce function is disabled 1 = The bit[6] de-bounce function is enabled The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 6 - 6 (1 bit)
access : read-write

DBEN7 : P0 Input Signal De-bounce Enable DBEN[7] used to enable the de-bounce function for each corresponding bit. if the input signal pulse width can't be sampled by continuous two de-bounce sample cycle. The input signal transition is seen as the signal bounce and will not trigger the interrupt. The DBEN[7] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt 0 = The bit[7] de-bounce function is disabled 1 = The bit[7] de-bounce function is enabled The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 7 - 7 (1 bit)
access : read-write

IMD0 : Port 0 Interrupt Mode Control IMD[0] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger souce is control de-bounce. If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt 0 = Edge trigger interrupt 1 = Level trigger interrupt if set pin as the level trigger interrupt, then only one level can be set on the registers P0_IEN. if set both the level to trigger interrupt, the setting is ignored and no interrupt will occur. The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 0 - 0 (1 bit)
access : read-write

IMD1 : Port 0 Interrupt Mode Control IMD[1] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger souce is control de-bounce. If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt 0 = Edge trigger interrupt 1 = Level trigger interrupt if set pin as the level trigger interrupt, then only one level can be set on the registers P0_IEN. if set both the level to trigger interrupt, the setting is ignored and no interrupt will occur. The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 1 - 1 (1 bit)
access : read-write

IMD2 : Port 0 Interrupt Mode Control IMD[2] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger souce is control de-bounce. If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt 0 = Edge trigger interrupt 1 = Level trigger interrupt if set pin as the level trigger interrupt, then only one level can be set on the registers P0_IEN. if set both the level to trigger interrupt, the setting is ignored and no interrupt will occur. The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 2 - 2 (1 bit)
access : read-write

IMD3 : Port 0 Interrupt Mode Control IMD[3] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger souce is control de-bounce. If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt 0 = Edge trigger interrupt 1 = Level trigger interrupt if set pin as the level trigger interrupt, then only one level can be set on the registers P0_IEN. if set both the level to trigger interrupt, the setting is ignored and no interrupt will occur. The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 3 - 3 (1 bit)
access : read-write

IMD4 : Port 0 Interrupt Mode Control IMD[4] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger souce is control de-bounce. If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt 0 = Edge trigger interrupt 1 = Level trigger interrupt if set pin as the level trigger interrupt, then only one level can be set on the registers P0_IEN. if set both the level to trigger interrupt, the setting is ignored and no interrupt will occur. The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 4 - 4 (1 bit)
access : read-write

IMD5 : Port 0 Interrupt Mode Control IMD[5] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger souce is control de-bounce. If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt 0 = Edge trigger interrupt 1 = Level trigger interrupt if set pin as the level trigger interrupt, then only one level can be set on the registers P0_IEN. if set both the level to trigger interrupt, the setting is ignored and no interrupt will occur. The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 5 - 5 (1 bit)
access : read-write

IMD6 : Port 0 Interrupt Mode Control IMD[6] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger souce is control de-bounce. If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt 0 = Edge trigger interrupt 1 = Level trigger interrupt if set pin as the level trigger interrupt, then only one level can be set on the registers P0_IEN. if set both the level to trigger interrupt, the setting is ignored and no interrupt will occur. The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 6 - 6 (1 bit)
access : read-write

IMD7 : Port 0 Interrupt Mode Control IMD[7] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger souce is control de-bounce. If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt 0 = Edge trigger interrupt 1 = Level trigger interrupt if set pin as the level trigger interrupt, then only one level can be set on the registers P0_IEN. if set both the level to trigger interrupt, the setting is ignored and no interrupt will occur. The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 7 - 7 (1 bit)
access : read-write

IF_EN0 : Port0 Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[0] used to enable the interrupt for each of the corresponding input P0[0]. Set bit "1" also enable the pin wakeup function. When set the IF_EN[0] bit "1": If the interrupt is level mode trigger, the input P0[0] state at level "low" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[0] state change from "high-to-low" will generate the interrupt. 1 = Enable the P0[0] state low-level or high-to-low change interrupt 0 = Disable the P0[0] state low-level or high-to-low change interrupt
bits : 0 - 0 (1 bit)
access : read-write

IF_EN1 : Port0 Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[1] used to enable the interrupt for each of the corresponding input P0[1]. Set bit "1" also enable the pin wakeup function. When set the IF_EN[1] bit "1": If the interrupt is level mode trigger, the input P0[1] state at level "low" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[1] state change from "high-to-low" will generate the interrupt. 1 = Enable the P0[1] state low-level or high-to-low change interrupt 0 = Disable the P0[1] state low-level or high-to-low change interrupt
bits : 1 - 1 (1 bit)
access : read-write

IF_EN2 : Port0 Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[2] used to enable the interrupt for each of the corresponding input P0[2]. Set bit "1" also enable the pin wakeup function. When set the IF_EN[2] bit "1": If the interrupt is level mode trigger, the input P0[2] state at level "low" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[2] state change from "high-to-low" will generate the interrupt. 1 = Enable the P0[2] state low-level or high-to-low change interrupt 0 = Disable the P0[2] state low-level or high-to-low change interrupt
bits : 2 - 2 (1 bit)
access : read-write

IF_EN3 : Port0 Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[3] used to enable the interrupt for each of the corresponding input P0[3]. Set bit "1" also enable the pin wakeup function. When set the IF_EN[3] bit "1": If the interrupt is level mode trigger, the input P0[3] state at level "low" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[3] state change from "high-to-low" will generate the interrupt. 1 = Enable the P0[3] state low-level or high-to-low change interrupt 0 = Disable the P0[3] state low-level or high-to-low change interrupt
bits : 3 - 3 (1 bit)
access : read-write

IF_EN4 : Port0 Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[4] used to enable the interrupt for each of the corresponding input P0[4]. Set bit "1" also enable the pin wakeup function. When set the IF_EN[4] bit "1": If the interrupt is level mode trigger, the input P0[4] state at level "low" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[4] state change from "high-to-low" will generate the interrupt. 1 = Enable the P0[4] state low-level or high-to-low change interrupt 0 = Disable the P0[4] state low-level or high-to-low change interrupt
bits : 4 - 4 (1 bit)
access : read-write

IF_EN5 : Port0 Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[5] used to enable the interrupt for each of the corresponding input P0[5]. Set bit "1" also enable the pin wakeup function. When set the IF_EN[5] bit "1": If the interrupt is level mode trigger, the input P0[5] state at level "low" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[5] state change from "high-to-low" will generate the interrupt. 1 = Enable the P0[5] state low-level or high-to-low change interrupt 0 = Disable the P0[5] state low-level or high-to-low change interrupt
bits : 5 - 5 (1 bit)
access : read-write

IF_EN6 : Port0 Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[6] used to enable the interrupt for each of the corresponding input P0[6]. Set bit "1" also enable the pin wakeup function. When set the IF_EN[6] bit "1": If the interrupt is level mode trigger, the input P0[6] state at level "low" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[6] state change from "high-to-low" will generate the interrupt. 1 = Enable the P0[6] state low-level or high-to-low change interrupt 0 = Disable the P0[6] state low-level or high-to-low change interrupt
bits : 6 - 6 (1 bit)
access : read-write

IF_EN7 : Port0 Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[7] used to enable the interrupt for each of the corresponding input P0[7]. Set bit "1" also enable the pin wakeup function. When set the IF_EN[7] bit "1": If the interrupt is level mode trigger, the input P0[7] state at level "low" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[7] state change from "high-to-low" will generate the interrupt. 1 = Enable the P0[7] state low-level or high-to-low change interrupt 0 = Disable the P0[7] state low-level or high-to-low change interrupt
bits : 7 - 7 (1 bit)
access : read-write

IR_EN0 : Port 0 Interrupt Enable by Input Rising Edge or Input Level High IR_EN[0] used to enable the interrupt for each of the corresponding input P0[0]. Set bit "1" also enable the pin wakeup function. When set the IR_EN[0] bit "1": If the interrupt is level mode trigger, the input P0[0] state at level "high" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[0] state change from "low-to-high" will generate the interrupt. 1 = Enable the P0[0] level-high or low-to-high interrupt 0 = Disable the P0[0] level-high or low-to-high interrupt
bits : 16 - 16 (1 bit)
access : read-write

IR_EN1 : Port 0 Interrupt Enable by Input Rising Edge or Input Level High IR_EN[1] used to enable the interrupt for each of the corresponding input P0[1]. Set bit "1" also enable the pin wakeup function. When set the IR_EN[1] bit "1": If the interrupt is level mode trigger, the input P0[1] state at level "high" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[1] state change from "low-to-high" will generate the interrupt. 1 = Enable the P0[1] level-high or low-to-high interrupt 0 = Disable the P0[1] level-high or low-to-high interrupt
bits : 17 - 17 (1 bit)
access : read-write

IR_EN2 : Port 0 Interrupt Enable by Input Rising Edge or Input Level High IR_EN[2] used to enable the interrupt for each of the corresponding input P0[2]. Set bit "1" also enable the pin wakeup function. When set the IR_EN[2] bit "1": If the interrupt is level mode trigger, the input P0[2] state at level "high" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[2] state change from "low-to-high" will generate the interrupt. 1 = Enable the P0[2] level-high or low-to-high interrupt 0 = Disable the P0[2] level-high or low-to-high interrupt
bits : 18 - 18 (1 bit)
access : read-write

IR_EN3 : Port 0 Interrupt Enable by Input Rising Edge or Input Level High IR_EN[3] used to enable the interrupt for each of the corresponding input P0[3]. Set bit "1" also enable the pin wakeup function. When set the IR_EN[3] bit "1": If the interrupt is level mode trigger, the input P0[3] state at level "high" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[3] state change from "low-to-high" will generate the interrupt. 1 = Enable the P0[3] level-high or low-to-high interrupt 0 = Disable the P0[3] level-high or low-to-high interrupt
bits : 19 - 19 (1 bit)
access : read-write

IR_EN4 : Port 0 Interrupt Enable by Input Rising Edge or Input Level High IR_EN[4] used to enable the interrupt for each of the corresponding input P0[4]. Set bit "1" also enable the pin wakeup function. When set the IR_EN[4] bit "1": If the interrupt is level mode trigger, the input P0[4] state at level "high" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[4] state change from "low-to-high" will generate the interrupt. 1 = Enable the P0[4] level-high or low-to-high interrupt 0 = Disable the P0[4] level-high or low-to-high interrupt
bits : 20 - 20 (1 bit)
access : read-write

IR_EN5 : Port 0 Interrupt Enable by Input Rising Edge or Input Level High IR_EN[5] used to enable the interrupt for each of the corresponding input P0[5]. Set bit "1" also enable the pin wakeup function. When set the IR_EN[5] bit "1": If the interrupt is level mode trigger, the input P0[5] state at level "high" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[5] state change from "low-to-high" will generate the interrupt. 1 = Enable the P0[5] level-high or low-to-high interrupt 0 = Disable the P0[5] level-high or low-to-high interrupt
bits : 21 - 21 (1 bit)
access : read-write

IR_EN6 : Port 0 Interrupt Enable by Input Rising Edge or Input Level High IR_EN[6] used to enable the interrupt for each of the corresponding input P0[6]. Set bit "1" also enable the pin wakeup function. When set the IR_EN[6] bit "1": If the interrupt is level mode trigger, the input P0[6] state at level "high" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[6] state change from "low-to-high" will generate the interrupt. 1 = Enable the P0[6] level-high or low-to-high interrupt 0 = Disable the P0[6] level-high or low-to-high interrupt
bits : 22 - 22 (1 bit)
access : read-write

IR_EN7 : Port 0 Interrupt Enable by Input Rising Edge or Input Level High IR_EN[7] used to enable the interrupt for each of the corresponding input P0[7]. Set bit "1" also enable the pin wakeup function. When set the IR_EN[7] bit "1": If the interrupt is level mode trigger, the input P0[7] state at level "high" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[7] state change from "low-to-high" will generate the interrupt. 1 = Enable the P0[7] level-high or low-to-high interrupt 0 = Disable the P0[7] level-high or low-to-high interrupt
bits : 23 - 23 (1 bit)
access : read-write

ISRC0 : Port 0 Interrupt Trigger Source Indicator Read: 1 = Indicates P0[0] generate an interrupt 0 = No interrupt at P0[0] Write: 1 = Clear the correspond pending interrupt 0 = No action
bits : 0 - 0 (1 bit)
access : read-write

ISRC1 : Port 0 Interrupt Trigger Source Indicator Read: 1 = Indicates P0[1] generate an interrupt 0 = No interrupt at P0[1] Write: 1 = Clear the correspond pending interrupt 0 = No action
bits : 1 - 1 (1 bit)
access : read-write

ISRC2 : Port 0 Interrupt Trigger Source Indicator Read: 1 = Indicates P0[2] generate an interrupt 0 = No interrupt at P0[2] Write: 1 = Clear the correspond pending interrupt 0 = No action
bits : 2 - 2 (1 bit)
access : read-write

ISRC3 : Port 0 Interrupt Trigger Source Indicator Read: 1 = Indicates P0[3] generate an interrupt 0 = No interrupt at P0[3] Write: 1 = Clear the correspond pending interrupt 0 = No action
bits : 3 - 3 (1 bit)
access : read-write

ISRC4 : Port 0 Interrupt Trigger Source Indicator Read: 1 = Indicates P0[4] generate an interrupt 0 = No interrupt at P0[4] Write: 1 = Clear the correspond pending interrupt 0 = No action
bits : 4 - 4 (1 bit)
access : read-write

ISRC5 : Port 0 Interrupt Trigger Source Indicator Read: 1 = Indicates P0[5] generate an interrupt 0 = No interrupt at P0[5] Write: 1 = Clear the correspond pending interrupt 0 = No action
bits : 5 - 5 (1 bit)
access : read-write

ISRC6 : Port 0 Interrupt Trigger Source Indicator Read: 1 = Indicates P0[6] generate an interrupt 0 = No interrupt at P0[6] Write: 1 = Clear the correspond pending interrupt 0 = No action
bits : 6 - 6 (1 bit)
access : read-write

ISRC7 : Port 0 Interrupt Trigger Source Indicator Read: 1 = Indicates P0[7] generate an interrupt 0 = No interrupt at P0[7] Write: 1 = Clear the correspond pending interrupt 0 = No action
bits : 7 - 7 (1 bit)
access : read-write

OFFD : OFFD: P0 Pin OFF digital input path Enable 1 = Disable IO digital input path (digital input tied to low) 0 = Enable IO digital input path
bits : 16 - 23 (8 bit)
access : read-write

DOUT0 : P0 Pin[0] Output Value Each of these bits control the status of a P0 pin when the P0 pin is configures as output, open-drain and quasi-mode. 1 = P0 Pin[0] will drive High if the corresponding output mode enabling bit is set. 0 = P0 Pin[0] will drive Low if the corresponding output mode enabling bit is set.
bits : 0 - 0 (1 bit)
access : read-write

DOUT1 : P0 Pin[1] Output Value Each of these bits control the status of a P0 pin when the P0 pin is configures as output, open-drain and quasi-mode. 1 = P0 Pin[1] will drive High if the corresponding output mode enabling bit is set. 0 = P0 Pin[1] will drive Low if the corresponding output mode enabling bit is set.
bits : 1 - 1 (1 bit)
access : read-write

DOUT2 : P0 Pin[2] Output Value Each of these bits control the status of a P0 pin when the P0 pin is configures as output, open-drain and quasi-mode. 1 = P0 Pin[2] will drive High if the corresponding output mode enabling bit is set. 0 = P0 Pin[2] will drive Low if the corresponding output mode enabling bit is set.
bits : 2 - 2 (1 bit)
access : read-write

DOUT3 : P0 Pin[3] Output Value Each of these bits control the status of a P0 pin when the P0 pin is configures as output, open-drain and quasi-mode. 1 = P0 Pin[3] will drive High if the corresponding output mode enabling bit is set. 0 = P0 Pin[3] will drive Low if the corresponding output mode enabling bit is set.
bits : 3 - 3 (1 bit)
access : read-write

DOUT4 : P0 Pin[4] Output Value Each of these bits control the status of a P0 pin when the P0 pin is configures as output, open-drain and quasi-mode. 1 = P0 Pin[4] will drive High if the corresponding output mode enabling bit is set. 0 = P0 Pin[4] will drive Low if the corresponding output mode enabling bit is set.
bits : 4 - 4 (1 bit)
access : read-write

DOUT5 : P0 Pin[5] Output Value Each of these bits control the status of a P0 pin when the P0 pin is configures as output, open-drain and quasi-mode. 1 = P0 Pin[5] will drive High if the corresponding output mode enabling bit is set. 0 = P0 Pin[5] will drive Low if the corresponding output mode enabling bit is set.
bits : 5 - 5 (1 bit)
access : read-write

DOUT6 : P0 Pin[6] Output Value Each of these bits control the status of a P0 pin when the P0 pin is configures as output, open-drain and quasi-mode. 1 = P0 Pin[6] will drive High if the corresponding output mode enabling bit is set. 0 = P0 Pin[6] will drive Low if the corresponding output mode enabling bit is set.
bits : 6 - 6 (1 bit)
access : read-write

DOUT7 : P0 Pin[7] Output Value Each of these bits control the status of a P0 pin when the P0 pin is configures as output, open-drain and quasi-mode. 1 = P0 Pin[7] will drive High if the corresponding output mode enabling bit is set. 0 = P0 Pin[7] will drive Low if the corresponding output mode enabling bit is set.
bits : 7 - 7 (1 bit)
access : read-write

DMASK0 : P0 Data Output Write Mask These bits are used to protect the corresponding register of P0_DOUT bit[0]. When set the DMASK bit[0] to "1", the corresponding DOUT0 bit is protected. The write signal is masked, write data to the protect bit is ignored 0 = The corresponding P0_DOUT[0] bit can be updated 1 = The corresponding P0_DOUT[0] bit is protected
bits : 0 - 0 (1 bit)
access : read-write

DMASK1 : P0 Data Output Write Mask These bits are used to protect the corresponding register of P0_DOUT bit[1]. When set the DMASK bit[1] to "1", the corresponding DOUT1 bit is protected. The write signal is masked, write data to the protect bit is ignored 0 = The corresponding P0_DOUT[1] bit can be updated 1 = The corresponding P0_DOUT[1] bit is protected
bits : 1 - 1 (1 bit)
access : read-write

DMASK2 : P0 Data Output Write Mask These bits are used to protect the corresponding register of P0_DOUT bit[2]. When set the DMASK bit[2] to "1", the corresponding DOUT2 bit is protected. The write signal is masked, write data to the protect bit is ignored 0 = The corresponding P0_DOUT[2] bit can be updated 1 = The corresponding P0_DOUT[2] bit is protected
bits : 2 - 2 (1 bit)
access : read-write

DMASK3 : P0 Data Output Write Mask These bits are used to protect the corresponding register of P0_DOUT bit[3]. When set the DMASK bit[3] to "1", the corresponding DOUT3 bit is protected. The write signal is masked, write data to the protect bit is ignored 0 = The corresponding P0_DOUT[3] bit can be updated 1 = The corresponding P0_DOUT[3] bit is protected
bits : 3 - 3 (1 bit)
access : read-write

DMASK4 : P0 Data Output Write Mask These bits are used to protect the corresponding register of P0_DOUT bit[4]. When set the DMASK bit[4] to "1", the corresponding DOUT4 bit is protected. The write signal is masked, write data to the protect bit is ignored 0 = The corresponding P0_DOUT[4] bit can be updated 1 = The corresponding P0_DOUT[4] bit is protected
bits : 4 - 4 (1 bit)
access : read-write

DMASK5 : P0 Data Output Write Mask These bits are used to protect the corresponding register of P0_DOUT bit[6]. When set the DMASK bit[6] to "1", the corresponding DOUT6 bit is protected. The write signal is masked, write data to the protect bit is ignored 0 = The corresponding P0_DOUT[6] bit can be updated 1 = The corresponding P0_DOUT[6] bit is protected
bits : 5 - 5 (1 bit)
access : read-write

DMASK6 : P0 Data Output Write Mask These bits are used to protect the corresponding register of P0_DOUT bit[6]. When set the DMASK bit[6] to "1", the corresponding DOUT6 bit is protected. The write signal is masked, write data to the protect bit is ignored 0 = The corresponding P0_DOUT[6] bit can be updated 1 = The corresponding P0_DOUT[6] bit is protected
bits : 6 - 6 (1 bit)
access : read-write

DMASK7 : P0 Data Output Write Mask These bits are used to protect the corresponding register of P0_DOUT bit[7]. When set the DMASK bit[7] to "1", the corresponding DOUT7 bit is protected. The write signal is masked, write data to the protect bit is ignored 0 = The corresponding P0_DOUT[7] bit can be updated 1 = The corresponding P0_DOUT[7] bit is protected
bits : 7 - 7 (1 bit)
access : read-write