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address_offset : 0x0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
Interrupt De-bounce Cycle Control
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBCLKSEL : De-bounce sampling cycle selection DBCLKSEL Description 0 Sample interrupt input once per 1 clocks 1 Sample interrupt input once per 2 clocks 2 Sample interrupt input once per 4 clocks 3 Sample interrupt input once per 8 clocks 4 Sample interrupt input once per 16 clocks 5 Sample interrupt input once per 32 clocks 6 Sample interrupt input once per 64 clocks 7 Sample interrupt input once per 128 clocks 8 Sample interrupt input once per 256 clocks 9 Sample interrupt input once per 2*256 clocks 10 Sample interrupt input once per 4*256clocks 11 Sample interrupt input once per 8*256 clocks 12 Sample interrupt input once per 16*256 clocks 13 Sample interrupt input once per 32*256 clocks 14 Sample interrupt input once per 64*256 clocks 15 Sample interrupt input once per 128*256 clocks
bits : 0 - 3 (4 bit)
access : read-write
DBCLKSRC : De-bounce counter clock source select 1 = De-bounce counter clock source is the internal 10KHz clock 0 = De-bounce counter clock source is the HCLK
bits : 4 - 4 (1 bit)
access : read-write
ICLK_ON : Interrupt clock On mode Set this bit "0" will disable the interrupt generate circuit clock, if the pin[n] interrupt is disabled 0 = disable the clock if the P0/1/2/3/4[n] interrupt is disabled 1 = interrupt generated circuit clock always enable n=0~7
bits : 5 - 5 (1 bit)
access : read-write
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