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address_offset : 0x0 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x20 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x10 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x34 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
Control and Status Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GO_BUSY : Go and Busy Status 1 = In master mode, writing 1 to this bit to start the SPI data transfer; in slave mode, writing 1 to this bit indicates that the slave is ready to communicate with a master. 0 = Writing 0 to this bit to stop data transfer if SPI is transferring. During the data transfer, this bit keeps the value of 1. As the transfer is finished, this bit will be cleared automatically. NOTE: All registers should be set before writing 1 to this GO_BUSY bit. The transfer result will be unpredictable if software changes related settings when GO_BUSY bit is 1.
bits : 0 - 0 (1 bit)
access : read-write
RX_NEG : Receive At Negative Edge 1 = The received data input signal is latched at the falling edge of SPICLK. 0 = The received data input signal is latched at the rising edge of SPICLK.
bits : 1 - 1 (1 bit)
access : read-write
TX_NEG : Transmit At Negative Edge 1 = The transmitted data output signal is changed at the falling edge of SPICLK. 0 = The transmitted data output signal is changed at the rising edge of SPICLK.
bits : 2 - 2 (1 bit)
access : read-write
TX_BIT_LEN : Transmit Bit Length This field specifies how many bits are transmitted in one transaction. Up to 32 bits can be transmitted. TX_BIT_LEN = 0x01 ... 1 bit TX_BIT_LEN = 0x02 ... 2 bits ...... TX_BIT_LEN = 0x1f ... 31 bits TX_BIT_LEN = 0x00 .. 32 bits
bits : 3 - 7 (5 bit)
access : read-write
TX_NUM : Numbers of Transmit/Receive Word This field specifies how many transmit/receive word numbers should be executed in one transfer. 00 = Only one transmit/receive word will be executed in one transfer. 01 = Two successive transmit/receive words will be executed in one transfer. (burst mode) 10 = Reserved. 11 = Reserved.
bits : 8 - 9 (2 bit)
access : read-write
LSB : LSB First 1 = The LSB is sent first on the line (bit 0 of SPI_TX0/1), and the first bit received from the line will be put in the LSB position of the RX register (bit 0 of SPI_RX0/1). 0 = The MSB is transmitted/received first (which bit in SPI_TX0/1 and SPI_RX0/1 register that is depends on the TX_BIT_LEN field).
bits : 10 - 10 (1 bit)
access : read-write
CLKP : Clock Polarity 1 = SPICLK idle high. 0 = SPICLK idle low.
bits : 11 - 11 (1 bit)
access : read-write
SP_CYCLE : Suspend Interval (master only) These four bits provide configurable suspend interval between two successive transmit/receive transactions in a transfer. The suspend interval is from the last falling clock edge of the current transaction to the first rising clock edge of the successive transaction if CLKP = 0. If CLKP = 1, the interval is from the rising clock edge to the falling clock edge. The default value is 0x0. When TX_NUM = 00b, setting this field has no effect on transfer. The desired suspend interval is obtained according to the following equation: (SP_CYCLE[3:0] + 2)*period of SPI clock SP_CYCLE = 0x0 ... 2 SPICLK clock cycle SP_CYCLE = 0x1 ... 3 SPICLK clock cycle ...... SP_CYCLE = 0xe ... 16 SPICLK clock cycle SP_CYCLE = 0xf ... 17 SPICLK clock cycle
bits : 12 - 15 (4 bit)
access : read-write
IF : Interrupt Flag 1 = It indicates that the transfer is done. The interrupt flag is set if it was enable. 0 = It indicates that the transfer does not finish yet. NOTE: This bit can be cleared by writing 1 to itself.
bits : 16 - 16 (1 bit)
access : read-write
IE : Interrupt Enable 1 = Enable MICROWIRE/SPI Interrupt. 0 = Disable MICROWIRE/SPI Interrupt.
bits : 17 - 17 (1 bit)
access : read-write
SLAVE : SLAVE Mode Indication 1 = Slave mode. 0 = Master mode.
bits : 18 - 18 (1 bit)
access : read-write
REORDER : Reorder Mode Select 00 = Disable both byte reorder and byte suspend functions. 01 = Enable byte reorder function and insert a byte suspend interval (2~17 SPICLK cycles) among each byte. The setting of TX_BIT_LEN must be configured as 0x00. (32 bits/word). 10 = Enable byte reorder function, but disable byte suspend function. 11 = Disable byte reorder function, but insert a suspend interval (2~17 SPICLK cycles) among each byte. The setting of TX_BIT_LEN must be configured as 0x00. (32 bits/word). Byte reorder function is only available if TX_BIT_LEN is defined as 16, 24 and 32.
bits : 19 - 20 (2 bit)
access : read-write
VARCLK_EN : Variable Clock Enable (master only) 1 = The serial clock output frequency is variable. The output frequency is decided by the value of VARCLK, DIVIDER, and DIVIDER2. 0 = The serial clock output frequency is fixed and decided only by the value of DIVIDER. Note that when enable this VARCLK_EN bit, the setting of TX_BIT_LEN must be programmed as 0x10 (16 bits mode)
bits : 23 - 23 (1 bit)
access : read-write
Data Receive Register 0
address_offset : 0x10 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RX : Data Receive Register The Data Receive Registers hold the value of received data of the last executed transfer. The number of valid bits depend on the transmit bit length field in the SPI_CNTRL register. For example, if TX_BIT_LEN is set to 0x08 and TX_NUM is set to 0x0, bit RX0[7:0] holds the received data. NOTE: The Data Receive Registers are read only registers.
bits : 0 - 31 (32 bit)
access : read-only
Data Receive Register 1
address_offset : 0x14 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RX : Data Receive Register The Data Receive Registers hold the value of received data of the last executed transfer. The number of valid bits depend on the transmit bit length field in the SPI_CNTRL register. For example, if TX_BIT_LEN is set to 0x08 and TX_NUM is set to 0x0, bit RX0[7:0] holds the received data. NOTE: The Data Receive Registers are read only registers.
bits : 0 - 31 (32 bit)
access : read-only
Data Transmit Register 0
address_offset : 0x20 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TX : Data Transmit Register The Data Transmit Registers hold the data to be transmitted in the next transfer. The number of valid bits depend on the transmit bit length field in the CNTRL register. For example, if TX_BIT_LEN is set to 0x08 and the TX_NUM is set to 0x0, the bit TX0[7:0] will be transmitted in next transfer. If TX_BIT_LEN is set to 0x00 and TX_NUM is set to 0x1, the core will perform two successive 32-bit transmit/receive using the same setting (the order is TX0[31:0], TX1[31:0]).
bits : 0 - 31 (32 bit)
access : write-only
Data Transmit Register 1
address_offset : 0x24 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TX : Data Transmit Register The Data Transmit Registers hold the data to be transmitted in the next transfer. The number of valid bits depend on the transmit bit length field in the CNTRL register. For example, if TX_BIT_LEN is set to 0x08 and the TX_NUM is set to 0x0, the bit TX0[7:0] will be transmitted in next transfer. If TX_BIT_LEN is set to 0x00 and TX_NUM is set to 0x1, the core will perform two successive 32-bit transmit/receive using the same setting (the order is TX0[31:0], TX1[31:0]).
bits : 0 - 31 (32 bit)
access : write-only
Variable Clock Pattern Register
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VARCLK : Variable Clock Pattern The value in this field is the frequency patterns of the SPI clock. If the bit patterns of VARCLK are 0, the output frequency of SPICLK is according the value of DIVIDER. If the bit patterns of VARCLK are 1, the output frequency of SPICLK is according the value of DIVIDER2. Refer to register SPI_DIVIDER.
bits : 0 - 31 (32 bit)
access : read-write
Clock Divider Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIVIDER : Clock Divider Register (master only) The value in this field is the frequency divider of the system clock, PCLK, to generate the serial clock on the output SPICLK. The desired frequency is obtained according to the following equation: fsclk = fpclk / ((DIVIDER+1)*2) In slave mode, the period of SPI clock driven by a master shall equal or over 5 times the period of PCLK. In other words, the maximum frequency of SPI clock is the fifth of the frequency of slave's PCLK.
bits : 0 - 15 (16 bit)
access : read-write
DIVIDER2 : Clock Divider 2 Register (master only) The value in this field is the 2nd frequency divider of the system clock, PCLK, to generate the serial clock on the output SPICLK. The desired frequency is obtained according to the following equation: fsclk = fpclk / ((DIVIDER2+1)*2)
bits : 16 - 31 (16 bit)
access : read-write
Slave Select Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SSR : Slave Select Register (master only) If AUTOSS bit is cleared, writing 1 to this bit sets the SPISSx line to active state and writing 0 sets the line back to inactive state. If AUTOSS bit is set, writing 1 to this bit will select the SPISSx line to be automatically driven to active state for the duration of the transmit/receive, and will be driven to inactive state for the rest of the time. (The active level of SPISSx0/1 is specified in SS_LVL).
bits : 0 - 0 (1 bit)
access : read-write
SS_LVL : Slave Select Active Level It defines the active level of slave select signal (SPISSx). 1 = The slave select signal SPISSx is active at high-level/rising-edge. 0 = The slave select signal SPISSx is active at low-level/falling-edge.
bits : 2 - 2 (1 bit)
access : read-write
AUTOSS : Automatic Slave Select (master only) 1 = If this bit is set, SPISSx signal is generated automatically. It means that slave select signal will be asserted by the SPI controller when transmit/receive is started by setting GO_BUSY, and is de-asserted after each transmit/receive is finished. 0 = If this bit is cleared, slave select signal will be asserted and de-asserted by setting and clearing SSR[0].
bits : 3 - 3 (1 bit)
access : read-write
SS_LTRIG : Slave Select Level Trigger (slave only) 1: The slave select signal will be level-trigger. It depends on SS_LVL to decide the signal is active low or active high. 0: The input slave select signal is edge-trigger. This is default value.
bits : 4 - 4 (1 bit)
access : read-write
LTRIG_FLAG : Level Trigger Flag When the SS_LTRIG bit is set in slave mode, this bit can be read to indicate the received bit number is met the requirement or not. 1 = The transaction number and the transferred bit length met the specified requirements which defined in TX_NUM and TX_BIT_LEN. 0 = The transaction number or the transferred bit length of one transaction doesn't meet the specified requirements. Note: This bit is READ only
bits : 5 - 5 (1 bit)
access : read-only
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