UA_RBR

UA_THR

UA_MCR

UA_MSR

UA_FSR

UA_ISR

UA_TOR

UA_BAUD

UA_IRCR

UA_ACT_CSR

UA_FUN_SEL

UA_IER

UA_FCR

UA_LCR

_8_bitReceivedData : Receive Buffer Register By reading this register, the UART will return an 8-bit data received from Rx pin (LSB first).
bits : 0 - 7 (8 bit)
access : read-only

_8_bitTransmittedData : Transmit Holding Register By writing to this register, the UART will send out an 8-bit data through the Tx pin (LSB first).
bits : 0 - 7 (8 bit)
access : write-only

RTS : RTS (Request-To-Send) Signal 0: Drive RTS pin to logic 1 (If the Lev_RTS set to low level triggered). 1: Drive RTS pin to logic 0 (If the Lev_RTS set to low level triggered). 0: Drive RTS pin to logic 0 (If the Lev_RTS set to high level triggered). 1: Drive RTS pin to logic 1 (If the Lev_RTS set to high level triggered).
bits : 1 - 1 (1 bit)
access : read-write

Lev_RTS : RTS Trigger Level This bit can change the RTS trigger level. 0= low level triggered 1= high level triggered
bits : 9 - 9 (1 bit)
access : read-write

RTS_St : RTS Pin State This bit is the pin status of RTS.
bits : 13 - 13 (1 bit)
access : read-only

DCTSF : Detect CTS State Change Flag This bit is set whenever CTS input has change state, and it will generate Modem interrupt to CPU when IER [Modem_IEN]. NOTE: This bit is cleared by writing 1 to itself.
bits : 0 - 0 (1 bit)
access : read-only

CTS_St : CTS Pin Status This bit is the pin status of CTS.
bits : 4 - 4 (1 bit)
access : read-only

Lev_CTS : CTS Trigger Level This bit can change the CTS trigger level. 0= low level triggered 1= high level triggered
bits : 8 - 8 (1 bit)
access : read-write

Rx_Over_IF : Rx overflow Error IF (Read Only) This bit is set when Rx FIFO overflow. If the number of bytes of received data is greater than Rx FIFO(UA_RBR) size, 16 bytes of UART0/UART1, this bit will be set. NOTE: This bit is cleared by writing 1 to itself.
bits : 0 - 0 (1 bit)
access : read-only

RS_485_Add_Det : RS-485 Address Byte Detection Flag This bit is set to logic 1 and set UA_RS-485_CSR [RS-485_Add_EN] whenever in RS-485 mode the receiver detect any address byte received address byte character (bit9 = '1') bit", and it is reset whenever the CPU writes 1 to this bit. Note: This field is used for RS-485 mode.
bits : 3 - 3 (1 bit)
access : read-only

PEF : Parity Error Flag This bit is set to logic 1 whenever the received character does not have a valid "parity bit", and is reset whenever the CPU writes 1 to this bit.
bits : 4 - 4 (1 bit)
access : read-only

FEF : Framing Error Flag This bit is set to logic 1 whenever the received character does not have a valid "stop bit" (that is, the stop bit following the last data bit or parity bit is detected as a logic 0), and is reset whenever the CPU writes 1 to this bit.
bits : 5 - 5 (1 bit)
access : read-only

BIF : Break Interrupt Flag This bit is set to a logic 1 whenever the received data input(Rx) is held in the "spacing state" (logic 0) for longer than a full word transmission time (that is, the total time of "start bit" + data bits + parity + stop bits) and is reset whenever the CPU writes 1 to this bit.
bits : 6 - 6 (1 bit)
access : read-only

Rx_Pointer : Rx FIFO pointer (Read Only) This field indicates the Rx FIFO Buffer Pointer. When UART receives one byte from external device, Rx_Pointer increases one. When one byte of Rx FIFO is read by CPU, Rx_Pointer decreases one.
bits : 8 - 13 (6 bit)
access : read-only

Rx_Empty : Receiver FIFO Empty (Read Only) This bit initiate Rx FIFO empty or not. When the last byte of Rx FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data.
bits : 14 - 14 (1 bit)
access : read-only

Rx_Full : Receiver FIFO Full (Read Only) This bit initiates Rx FIFO full or not. This bit is set when Rx_Pointer is equal to 16(UART0/UART1), otherwise is cleared by hardware.
bits : 15 - 15 (1 bit)
access : read-only

Tx_Pointer : TX FIFO Pointer (Read Only) This field indicates the Tx FIFO Buffer Pointer. When CPU write one byte into UA_THR, Tx_Pointer increases one. When one byte of Tx FIFO is transferred to Transmitter Shift Register, Tx_Pointer decreases one.
bits : 16 - 21 (6 bit)
access : read-only

Tx_Empty : Transmitter FIFO Empty (Read Only) This bit indicates Tx FIFO empty or not. When the last byte of Tx FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into THR (Tx FIFO not empty).
bits : 22 - 22 (1 bit)
access : read-only

Tx_Full : Transmitter FIFO Full (Read Only) This bit indicates Tx FIFO full or not. This bit is set when Tx_Pointer is equal to 64/16(UART0/UART1), otherwise is cleared by hardware.
bits : 23 - 23 (1 bit)
access : read-only

Tx_Over_IF : Tx Overflow Error Interrupt Flag (Read Only) If Tx FIFO(UA_THR) is full, an additional write to UA_THR will cause this bit to logic 1. NOTE: This bit is cleared by writing 1 to itself.
bits : 24 - 24 (1 bit)
access : read-only

TE_Flag : Transmitter Empty Flag (Read Only) Bit is set by hardware when Tx FIFO(UA_THR) is empty and the STOP bit of the last byte has been transmitted. Bit is cleared automatically when Tx FIFO is not empty or the last byte transmission has not completed. NOTE: This bit is read only.
bits : 28 - 28 (1 bit)
access : read-only

RDA_IF : Receive Data Available Interrupt Flag (Read Only). When the number of bytes in the Rx FIFO equals the RFITL then the RDA_IF will be set. If IER[RDA_IEN] is enabled, the RDA interrupt will be generated. NOTE: This bit is read only and it will be cleared when the number of unread bytes of Rx FIFO drops below the threshold level (RFITL).
bits : 0 - 0 (1 bit)
access : read-only

THRE_IF : Transmit Holding Register Empty Interrupt Flag (Read Only). This bit is set when the last data of Tx FIFO is transferred to Transmitter Shift Register. If IER[THRE_IEN] is enabled, the THRE interrupt will be generated. NOTE: This bit is read only and it will be cleared when writing data into THR (Tx FIFO not empty).
bits : 1 - 1 (1 bit)
access : read-only

RLS_IF : Receive Line Interrupt Flag (Read Only). In UART mode this bit is set when the Rx receive data have parity error, framing error or break error (at least one of 3 bits, BIF, FEF and PEF, is set). In RS-485 mode, the field includes RS-485 Address Byte Detection Flag. If IER[RLS_IEN] is enabled, the RLS interrupt will be generated. NOTE: This bit is read only and reset to 0 when all bits of BIF, FEF, PEF and RS-485_Add_Det are cleared.
bits : 2 - 2 (1 bit)
access : read-only

Modem_IF : MODEM Interrupt Flag (Read Only) This bit is set when the CTS pin has state change (DCTSF=1). If IER[Modem_IEN] is enabled, the Modem interrupt will be generated. NOTE: This bit is read only and reset to 0 when bit DCTSF is cleared by a write 1 on DCTSF.
bits : 3 - 3 (1 bit)
access : read-only

Tout_IF : Time Out Interrupt Flag (Read Only) This bit is set when the Rx FIFO is not empty and no activities occur in the Rx FIFO and the time out counter equal to TOIC. If IER [Tout_IEN] is enabled, the Tout interrupt will be generated. NOTE: This bit is read only and user can read UA_RBR (Rx is in active) to clear it.
bits : 4 - 4 (1 bit)
access : read-only

Buf_Err_IF : Buffer Error Interrupt Flag (Read Only) This bit is set when the Tx or Rx FIFO overflows (Tx_Over_IF or Rx_Over_IF is set). When Buf_Err_IF is set, the transfer maybe not correct. If IER[Buf_Err_IEN] is enabled, the buffer error interrupt will be generated. NOTE: This bit is cleared when both Tx_Over_IF and Rx_Over_IF are cleared.
bits : 5 - 5 (1 bit)
access : read-only

RDA_INT : Receive Data Available Interrupt Indicator to Interrupt Controller (INT_RDA). An AND output with inputs of RDA_IEN and RDA_IF
bits : 8 - 8 (1 bit)
access : read-only

THRE_INT : Transmit Holding Register Empty Interrupt Indicator to Interrupt Controller (INT_THRE). An AND output with inputs of THRE_IEN and THRE_IF
bits : 9 - 9 (1 bit)
access : read-only

RLS_INT : Receive Line Status Interrupt Indicator to Interrupt Controller (INT_RLS). An AND output with inputs of RLS_IEN and RLS_IF Note: In RS-485 mode, the field includes RS-485 Address Byte Detection Flag.
bits : 10 - 10 (1 bit)
access : read-only

Modem_INT : MODEM Status Interrupt Indicator to Interrupt Controller (INT_MOS). An AND output with inputs of Modem_IEN and Modem_IF
bits : 11 - 11 (1 bit)
access : read-only

Tout_INT : Time Out Interrupt Indicator to Interrupt Controller (INT_Tout) An AND output with inputs of RTO_IEN and Tout_IF
bits : 12 - 12 (1 bit)
access : read-only

Buf_Err_INT : Buffer Error Interrupt Indicator to Interrupt Controller (INT_Buf_err) An AND output with inputs of BUF_ERR_IEN and Buf_Err_IF
bits : 13 - 13 (1 bit)
access : read-only

TOIC : Time Out Interrupt Comparator The time out counter resets and starts counting (the counting clock = baud rate) whenever the RX FIFO receives a new data word. Once the content of time out counter (TOUT_CNT) is equal to that of time out interrupt comparator (TOIC), a receiver time out interrupt (INT_TOUT) is generated if UA_IER [RTO_IEN]. A new incoming data word or RX FIFO empty clears INT_TOUT.
bits : 0 - 6 (7 bit)
access : read-write

DLY : TX Delay time value This field is use to programming the transfer delay time between the last stop bit leaving the TX-FIFO and the de-assertion of by setting UA_TOR. DLY register.
bits : 8 - 15 (8 bit)
access : read-write

BRD_LowByte : Baud Rate Divider The low byte of the baud rate divider
bits : 0 - 7 (8 bit)
access : read-write

BRD_HighByte : Baud Rate Divider The high byte of the baud rate divider
bits : 8 - 15 (8 bit)
access : read-write

Divider_X : Divider X The baud rate divider M = X+1.
bits : 24 - 27 (4 bit)
access : read-write

DIV_X_ONE : Divider X equal 1 0 = Divider M = X (the equation of M = X+1, but Divider_X[27:24] must > 8) 1 = Divider M = 1 (the equation of M = 1, but BRD[15:0] must > 3). Mode DIV_X_EN DIV_X_ONE DIVIDER X BRD Baud rate equation 0 Disable 0 B A UART_CLK / [16 * (A+2)] 1 Enable 0 B A UART_CLK/[(B+1)*(A+2)],B must >= 8 2 Enable 1 Don't Care A UART_CLK / (A+2), A must >=3
bits : 28 - 28 (1 bit)
access : read-write

DIV_X_EN : Divider X Enable The BRD = Baud Rate Divider, and the baud rate equation is Baud Rate = Clock / [ M * (BRD + 2) ] ; The default value of M is 16. 0 = Disable divider X (the equation of M = 16) 1 = Enable divider X (the equation of M = X+1, but Divider_X[27:24 must > 8). NOTE: When in IrDA mode, this bit must disable. Mode DIV_X_EN DIV_X_ONE DIVIDER X BRD Baud rate equation 0 Disable 0 B A UART_CLK / [16 * (A+2)] 1 Enable 0 B A UART_CLK/[(B+1)*(A+2)],B must >= 8 2 Enable 1 Don't Care A UART_CLK / (A+2), A must >=3
bits : 29 - 29 (1 bit)
access : read-write

Tx_SELECT : Tx_SELECT 1: Enable IrDA transmitter 0: Enable IrDA receiver
bits : 1 - 1 (1 bit)
access : read-write

LB : IrDA loop back mode for self test. 1: Enable IrDA loop back mode 0: Disable IrDA loop back mode
bits : 2 - 2 (1 bit)
access : read-write

INV_Tx : INV_Tx 1= Inverse Tx output signal 0= No inversion
bits : 5 - 5 (1 bit)
access : read-write

INV_Rx : INV_Rx 1= Inverse Rx input signal 0= No inversion
bits : 6 - 6 (1 bit)
access : read-write

RS_485_NMM : RS-485 Normal Multi-drop Operation Mode (NMM) 1: Enable RS-485 Normal Multi-drop Operation Mode (NMM) 0: Disable RS-485 Normal Multi-drop Operation Mode (NMM) Note: It can't be active with RS-485_AAD operation mode.
bits : 8 - 8 (1 bit)
access : read-write

RS_485_AAD : RS-485 Auto Address Detection Operation Mode (AAD) 1: Enable RS-485 Auto Address Detection Operation Mode (AAD) 0: Disable RS-485 Auto Address Detection Operation Mode (AAD) Note: It can't be active with RS-485_NMM operation mode.
bits : 9 - 9 (1 bit)
access : read-write

RS_485_AUD : RS-485 Auto Direction Mode (AUD) 1: Enable RS-485 Auto Direction Mode (AUD) 0: Disable RS-485 Auto Direction Mode (AUD) Note: It can be active with RS-485_AAD or RS-485_NMM operation mode.
bits : 10 - 10 (1 bit)
access : read-write

RS_485_Add_EN : RS-485 Address Detection Enable This bit is use to enable RS-485 address detection mode. 1: Enable address detection mode 0: Disable address detection mode Note: This field is used for RS-485 any operation mode.
bits : 15 - 15 (1 bit)
access : read-write

ADDR_MATCH : Address match value register This field contains the RS-485 address match values. Note: This field is used for RS-485 auto address detection mode.
bits : 24 - 31 (8 bit)
access : read-write

FUN_SEL : Function Select Enable 00 = UART Function. 01 = Reserved. 10 = Enable IrDA Function. 11 = Enable RS-485 Function.
bits : 0 - 1 (2 bit)
access : read-write

RDA_IEN : Receive Data Available Interrupt Enable. 0 = Mask off INT_RDA 1 = Enable INT_RDA
bits : 0 - 0 (1 bit)
access : read-write

THRE_IEN : Transmit Holding Register Empty Interrupt Enable 0 = Mask off INT_THRE 1 = Enable INT_THRE
bits : 1 - 1 (1 bit)
access : read-write

RLS_IEN : Receive Line Status Interrupt Enable 0 = Mask off INT_RLS 1 = Enable INT_RLS
bits : 2 - 2 (1 bit)
access : read-write

Modem_IEN : Modem Status Interrupt Enable 0 = Mask off INT_MOS 1 = Enable INT_MOS
bits : 3 - 3 (1 bit)
access : read-write

RTO_IEN : Rx Time out Interrupt Enable 0 = Mask off INT_tout 1 = Enable INT_tout
bits : 4 - 4 (1 bit)
access : read-write

BUF_ERR_IEN : Buffer Error Interrupt Enable 0 = Mask off INT_Buf_err 1 = Enable INT_Buf_err
bits : 5 - 5 (1 bit)
access : read-write

Wake_EN : Wake up CPU function enable 0 = Disable UART wake up CPU function 1 = Enable wake up function, when the system is in deep sleep mode, an external /CTS change will wake up CPU from deep sleep mode.
bits : 6 - 6 (1 bit)
access : read-write

Time_Out_EN : Time-Out Counter Enable 1 = Enable Time-out counter. 0 = Disable Time-out counter.
bits : 11 - 11 (1 bit)
access : read-write

Auto_RTS_EN : RTS Auto Flow Control Enable 1 = Enable RTS auto flow control. 0 = Disable RTS auto flow control. When RTS auto-flow is enabled, if the number of bytes in the Rx FIFO equals the UA_FCR [RTS_Tri_Lev], the UART will dessert RTS signal.
bits : 12 - 12 (1 bit)
access : read-write

Auto_CTS_EN : CTS Auto Flow Control Enable 1 = Enable CTS auto flow control. 0 = Disable CTS auto flow control. When CTS auto-flow is enabled, the UART will send data to external device when CTS input assert (UART will not send data to device until CTS is asserted).
bits : 13 - 13 (1 bit)
access : read-write

RFR : Rx Software Reset When Rx_RST is set, all the bytes in the transmit FIFO and Rx internal state machine are cleared. 0 = Writing 0 to this bit has no effect. 1 = Writing 1 to this bit will reset the Rx internal state machine and pointers. Note: This bit will auto clear and takes at least 3 UART engine clock cycles.
bits : 1 - 1 (1 bit)
access : read-write

TFR : Tx Software Reset When Tx_RST is set, all the bytes in the transmit FIFO and Tx internal state machine are cleared. 0 = Writing 0 to this bit has no effect. 1 = Writing 1 to this bit will reset the Tx internal state machine and pointers. Note: This bit will auto clear and takes at least 3 UART engine clock cycles.
bits : 2 - 2 (1 bit)
access : read-write

RFITL : Word Length Select RFITL INTR_RDA Tigger Level(Bytes) 0000 01 0001 04 0010 08 0011 14
bits : 4 - 7 (4 bit)
access : read-write

RX_DIS : Receiver Disable register. The receiver is disabled or not (set 1 is disable receiver) 1: Disable Receiver 0: Enable Receiver Note: This field is used for RS-485 Normal Multi-drop mode. It should be programmed before RS-485 enable function in UA_FUN_SEL. FUN_SEL is programmed.
bits : 8 - 8 (1 bit)
access : read-write

RTS_Tri_Lev : Word Length Select RTS_Tri_Lev Trigger Level(Bytes) 0000 01 0001 04 0010 08 0011 14
bits : 16 - 19 (4 bit)
access : read-write

WLS : Word Length Select WLS[1:0] Character length 00 5 bits 01 6 bits 10 7 bits 11 8 bits
bits : 0 - 1 (2 bit)
access : read-write

NSB : Number of "STOP bit" 0= One "STOP bit" is generated in the transmitted data 1= One and a half "STOP bit" is generated in the transmitted data when 5-bit word length is selected; Two "STOP bit" is generated when 6-, 7- and 8-bit word length is selected.
bits : 2 - 2 (1 bit)
access : read-write

PBE : Parity Bit Enable 0 = Parity bit is not generated (transmit data) or checked (receive data) during transfer. 1 = Parity bit is generated or checked between the "last data word bit" and "stop bit" of the serial data.
bits : 3 - 3 (1 bit)
access : read-write

EPE : Even Parity Enable 0 = Odd number of logic 1's are transmitted or checked in the data word and parity bits. 1 = Even number of logic 1's are transmitted or checked in the data word and parity bits. This bit has effect only when bit 3 (parity bit enable) is set.
bits : 4 - 4 (1 bit)
access : read-write

SPE : Stick Parity Enable 0 = Disable stick parity 1 = When bits PBE , EPE and SPE are set, the parity bit is transmitted and checked as cleared. When PBE and SPE are set and EPE is cleared, the parity bit is transmitted and checked as set.
bits : 5 - 5 (1 bit)
access : read-write

BCB : Break Control Bit When this bit is set to logic 1, the serial data output (Tx) is forced to the Spacing State (logic 0). This bit acts only on Tx and has no effect on the transmitter logic.
bits : 6 - 6 (1 bit)
access : read-write