Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x180 byte (0x0)
mem_usage : registers
protection : not protected
Regulator 1P1 Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE_LINREG : Control bit to enable the regulator output.
bits : 0 - 0 (1 bit)
access : read-write
ENABLE_BO : Control bit to enable the brownout circuitry in the regulator.
bits : 1 - 1 (1 bit)
access : read-write
ENABLE_ILIMIT : Control bit to enable the current-limit circuitry in the regulator.
bits : 2 - 2 (1 bit)
access : read-write
ENABLE_PULLDOWN : Control bit to enable the pull-down circuitry in the regulator
bits : 3 - 3 (1 bit)
access : read-write
BO_OFFSET : Control bits to adjust the regulator brownout offset voltage in 25mV steps
bits : 4 - 6 (3 bit)
access : read-write
OUTPUT_TRG : Control bits to adjust the regulator output voltage
bits : 8 - 12 (5 bit)
access : read-write
Enumeration:
0x4 : OUTPUT_TRG_4
0.8V
0x10 : OUTPUT_TRG_16
1.1V
End of enumeration elements list.
BO_VDD1P1 : Status bit that signals when a brownout is detected on the regulator output.
bits : 16 - 16 (1 bit)
access : read-only
OK_VDD1P1 : Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target
bits : 17 - 17 (1 bit)
access : read-only
ENABLE_WEAK_LINREG : Enables the weak 1p1 regulator
bits : 18 - 18 (1 bit)
access : read-write
SELREF_WEAK_LINREG : Selects the source for the reference voltage of the weak 1p1 regulator.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : SELREF_WEAK_LINREG_0
Weak-linreg output tracks low-power-bandgap voltage
0x1 : SELREF_WEAK_LINREG_1
Weak-linreg output tracks VDD_SOC_IN voltage
End of enumeration elements list.
Regulator 1P1 Register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE_LINREG : Control bit to enable the regulator output.
bits : 0 - 0 (1 bit)
access : read-write
ENABLE_BO : Control bit to enable the brownout circuitry in the regulator.
bits : 1 - 1 (1 bit)
access : read-write
ENABLE_ILIMIT : Control bit to enable the current-limit circuitry in the regulator.
bits : 2 - 2 (1 bit)
access : read-write
ENABLE_PULLDOWN : Control bit to enable the pull-down circuitry in the regulator
bits : 3 - 3 (1 bit)
access : read-write
BO_OFFSET : Control bits to adjust the regulator brownout offset voltage in 25mV steps
bits : 4 - 6 (3 bit)
access : read-write
OUTPUT_TRG : Control bits to adjust the regulator output voltage
bits : 8 - 12 (5 bit)
access : read-write
Enumeration:
0x4 : OUTPUT_TRG_4
0.8V
0x10 : OUTPUT_TRG_16
1.1V
End of enumeration elements list.
BO_VDD1P1 : Status bit that signals when a brownout is detected on the regulator output.
bits : 16 - 16 (1 bit)
access : read-only
OK_VDD1P1 : Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target
bits : 17 - 17 (1 bit)
access : read-only
ENABLE_WEAK_LINREG : Enables the weak 1p1 regulator
bits : 18 - 18 (1 bit)
access : read-write
SELREF_WEAK_LINREG : Selects the source for the reference voltage of the weak 1p1 regulator.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : SELREF_WEAK_LINREG_0
Weak-linreg output tracks low-power-bandgap voltage
0x1 : SELREF_WEAK_LINREG_1
Weak-linreg output tracks VDD_SOC_IN voltage
End of enumeration elements list.
Regulator 1P1 Register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE_LINREG : Control bit to enable the regulator output.
bits : 0 - 0 (1 bit)
access : read-write
ENABLE_BO : Control bit to enable the brownout circuitry in the regulator.
bits : 1 - 1 (1 bit)
access : read-write
ENABLE_ILIMIT : Control bit to enable the current-limit circuitry in the regulator.
bits : 2 - 2 (1 bit)
access : read-write
ENABLE_PULLDOWN : Control bit to enable the pull-down circuitry in the regulator
bits : 3 - 3 (1 bit)
access : read-write
BO_OFFSET : Control bits to adjust the regulator brownout offset voltage in 25mV steps
bits : 4 - 6 (3 bit)
access : read-write
OUTPUT_TRG : Control bits to adjust the regulator output voltage
bits : 8 - 12 (5 bit)
access : read-write
Enumeration:
0x4 : OUTPUT_TRG_4
0.8V
0x10 : OUTPUT_TRG_16
1.1V
End of enumeration elements list.
BO_VDD1P1 : Status bit that signals when a brownout is detected on the regulator output.
bits : 16 - 16 (1 bit)
access : read-only
OK_VDD1P1 : Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target
bits : 17 - 17 (1 bit)
access : read-only
ENABLE_WEAK_LINREG : Enables the weak 1p1 regulator
bits : 18 - 18 (1 bit)
access : read-write
SELREF_WEAK_LINREG : Selects the source for the reference voltage of the weak 1p1 regulator.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : SELREF_WEAK_LINREG_0
Weak-linreg output tracks low-power-bandgap voltage
0x1 : SELREF_WEAK_LINREG_1
Weak-linreg output tracks VDD_SOC_IN voltage
End of enumeration elements list.
Regulator 1P1 Register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE_LINREG : Control bit to enable the regulator output.
bits : 0 - 0 (1 bit)
access : read-write
ENABLE_BO : Control bit to enable the brownout circuitry in the regulator.
bits : 1 - 1 (1 bit)
access : read-write
ENABLE_ILIMIT : Control bit to enable the current-limit circuitry in the regulator.
bits : 2 - 2 (1 bit)
access : read-write
ENABLE_PULLDOWN : Control bit to enable the pull-down circuitry in the regulator
bits : 3 - 3 (1 bit)
access : read-write
BO_OFFSET : Control bits to adjust the regulator brownout offset voltage in 25mV steps
bits : 4 - 6 (3 bit)
access : read-write
OUTPUT_TRG : Control bits to adjust the regulator output voltage
bits : 8 - 12 (5 bit)
access : read-write
Enumeration:
0x4 : OUTPUT_TRG_4
0.8V
0x10 : OUTPUT_TRG_16
1.1V
End of enumeration elements list.
BO_VDD1P1 : Status bit that signals when a brownout is detected on the regulator output.
bits : 16 - 16 (1 bit)
access : read-only
OK_VDD1P1 : Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target
bits : 17 - 17 (1 bit)
access : read-only
ENABLE_WEAK_LINREG : Enables the weak 1p1 regulator
bits : 18 - 18 (1 bit)
access : read-write
SELREF_WEAK_LINREG : Selects the source for the reference voltage of the weak 1p1 regulator.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : SELREF_WEAK_LINREG_0
Weak-linreg output tracks low-power-bandgap voltage
0x1 : SELREF_WEAK_LINREG_1
Weak-linreg output tracks VDD_SOC_IN voltage
End of enumeration elements list.
Regulator 3P0 Register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE_LINREG : Control bit to enable the regulator output to be set by the programmed target voltage setting and internal bandgap reference
bits : 0 - 0 (1 bit)
access : read-write
ENABLE_BO : Control bit to enable the brownout circuitry in the regulator.
bits : 1 - 1 (1 bit)
access : read-write
ENABLE_ILIMIT : Control bit to enable the current-limit circuitry in the regulator.
bits : 2 - 2 (1 bit)
access : read-write
BO_OFFSET : Control bits to adjust the regulator brownout offset voltage in 25mV steps
bits : 4 - 6 (3 bit)
access : read-write
VBUS_SEL : Select input voltage source for LDO_3P0 from either USB_OTG1_VBUS or USB_OTG2_VBUS
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : USB_OTG2_VBUS
Utilize VBUS OTG2 power
0x1 : USB_OTG1_VBUS
Utilize VBUS OTG1 power
End of enumeration elements list.
OUTPUT_TRG : Control bits to adjust the regulator output voltage
bits : 8 - 12 (5 bit)
access : read-write
Enumeration:
0 : OUTPUT_TRG_0
2.625V
0xF : OUTPUT_TRG_15
3.000V
0x1F : OUTPUT_TRG_31
3.400V
End of enumeration elements list.
BO_VDD3P0 : Status bit that signals when a brownout is detected on the regulator output.
bits : 16 - 16 (1 bit)
access : read-only
OK_VDD3P0 : Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target
bits : 17 - 17 (1 bit)
access : read-only
Regulator 3P0 Register
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE_LINREG : Control bit to enable the regulator output to be set by the programmed target voltage setting and internal bandgap reference
bits : 0 - 0 (1 bit)
access : read-write
ENABLE_BO : Control bit to enable the brownout circuitry in the regulator.
bits : 1 - 1 (1 bit)
access : read-write
ENABLE_ILIMIT : Control bit to enable the current-limit circuitry in the regulator.
bits : 2 - 2 (1 bit)
access : read-write
BO_OFFSET : Control bits to adjust the regulator brownout offset voltage in 25mV steps
bits : 4 - 6 (3 bit)
access : read-write
VBUS_SEL : Select input voltage source for LDO_3P0 from either USB_OTG1_VBUS or USB_OTG2_VBUS
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : USB_OTG2_VBUS
Utilize VBUS OTG2 power
0x1 : USB_OTG1_VBUS
Utilize VBUS OTG1 power
End of enumeration elements list.
OUTPUT_TRG : Control bits to adjust the regulator output voltage
bits : 8 - 12 (5 bit)
access : read-write
Enumeration:
0 : OUTPUT_TRG_0
2.625V
0xF : OUTPUT_TRG_15
3.000V
0x1F : OUTPUT_TRG_31
3.400V
End of enumeration elements list.
BO_VDD3P0 : Status bit that signals when a brownout is detected on the regulator output.
bits : 16 - 16 (1 bit)
access : read-only
OK_VDD3P0 : Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target
bits : 17 - 17 (1 bit)
access : read-only
Regulator 3P0 Register
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE_LINREG : Control bit to enable the regulator output to be set by the programmed target voltage setting and internal bandgap reference
bits : 0 - 0 (1 bit)
access : read-write
ENABLE_BO : Control bit to enable the brownout circuitry in the regulator.
bits : 1 - 1 (1 bit)
access : read-write
ENABLE_ILIMIT : Control bit to enable the current-limit circuitry in the regulator.
bits : 2 - 2 (1 bit)
access : read-write
BO_OFFSET : Control bits to adjust the regulator brownout offset voltage in 25mV steps
bits : 4 - 6 (3 bit)
access : read-write
VBUS_SEL : Select input voltage source for LDO_3P0 from either USB_OTG1_VBUS or USB_OTG2_VBUS
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : USB_OTG2_VBUS
Utilize VBUS OTG2 power
0x1 : USB_OTG1_VBUS
Utilize VBUS OTG1 power
End of enumeration elements list.
OUTPUT_TRG : Control bits to adjust the regulator output voltage
bits : 8 - 12 (5 bit)
access : read-write
Enumeration:
0 : OUTPUT_TRG_0
2.625V
0xF : OUTPUT_TRG_15
3.000V
0x1F : OUTPUT_TRG_31
3.400V
End of enumeration elements list.
BO_VDD3P0 : Status bit that signals when a brownout is detected on the regulator output.
bits : 16 - 16 (1 bit)
access : read-only
OK_VDD3P0 : Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target
bits : 17 - 17 (1 bit)
access : read-only
Regulator 3P0 Register
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE_LINREG : Control bit to enable the regulator output to be set by the programmed target voltage setting and internal bandgap reference
bits : 0 - 0 (1 bit)
access : read-write
ENABLE_BO : Control bit to enable the brownout circuitry in the regulator.
bits : 1 - 1 (1 bit)
access : read-write
ENABLE_ILIMIT : Control bit to enable the current-limit circuitry in the regulator.
bits : 2 - 2 (1 bit)
access : read-write
BO_OFFSET : Control bits to adjust the regulator brownout offset voltage in 25mV steps
bits : 4 - 6 (3 bit)
access : read-write
VBUS_SEL : Select input voltage source for LDO_3P0 from either USB_OTG1_VBUS or USB_OTG2_VBUS
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : USB_OTG2_VBUS
Utilize VBUS OTG2 power
0x1 : USB_OTG1_VBUS
Utilize VBUS OTG1 power
End of enumeration elements list.
OUTPUT_TRG : Control bits to adjust the regulator output voltage
bits : 8 - 12 (5 bit)
access : read-write
Enumeration:
0 : OUTPUT_TRG_0
2.625V
0xF : OUTPUT_TRG_15
3.000V
0x1F : OUTPUT_TRG_31
3.400V
End of enumeration elements list.
BO_VDD3P0 : Status bit that signals when a brownout is detected on the regulator output.
bits : 16 - 16 (1 bit)
access : read-only
OK_VDD3P0 : Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target
bits : 17 - 17 (1 bit)
access : read-only
Regulator 2P5 Register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE_LINREG : Control bit to enable the regulator output.
bits : 0 - 0 (1 bit)
access : read-write
ENABLE_BO : Control bit to enable the brownout circuitry in the regulator.
bits : 1 - 1 (1 bit)
access : read-write
ENABLE_ILIMIT : Control bit to enable the current-limit circuitry in the regulator.
bits : 2 - 2 (1 bit)
access : read-write
ENABLE_PULLDOWN : Control bit to enable the pull-down circuitry in the regulator
bits : 3 - 3 (1 bit)
access : read-write
BO_OFFSET : Control bits to adjust the regulator brownout offset voltage in 25mV steps
bits : 4 - 6 (3 bit)
access : read-write
OUTPUT_TRG : Control bits to adjust the regulator output voltage
bits : 8 - 12 (5 bit)
access : read-write
Enumeration:
0 : OUTPUT_TRG_0
2.10V
0x10 : OUTPUT_TRG_16
2.50V
0x1F : OUTPUT_TRG_31
2.875V
End of enumeration elements list.
BO_VDD2P5 : Status bit that signals when a brownout is detected on the regulator output.
bits : 16 - 16 (1 bit)
access : read-only
OK_VDD2P5 : Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target
bits : 17 - 17 (1 bit)
access : read-only
ENABLE_WEAK_LINREG : Enables the weak 2p5 regulator
bits : 18 - 18 (1 bit)
access : read-write
Regulator 2P5 Register
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE_LINREG : Control bit to enable the regulator output.
bits : 0 - 0 (1 bit)
access : read-write
ENABLE_BO : Control bit to enable the brownout circuitry in the regulator.
bits : 1 - 1 (1 bit)
access : read-write
ENABLE_ILIMIT : Control bit to enable the current-limit circuitry in the regulator.
bits : 2 - 2 (1 bit)
access : read-write
ENABLE_PULLDOWN : Control bit to enable the pull-down circuitry in the regulator
bits : 3 - 3 (1 bit)
access : read-write
BO_OFFSET : Control bits to adjust the regulator brownout offset voltage in 25mV steps
bits : 4 - 6 (3 bit)
access : read-write
OUTPUT_TRG : Control bits to adjust the regulator output voltage
bits : 8 - 12 (5 bit)
access : read-write
Enumeration:
0 : OUTPUT_TRG_0
2.10V
0x10 : OUTPUT_TRG_16
2.50V
0x1F : OUTPUT_TRG_31
2.875V
End of enumeration elements list.
BO_VDD2P5 : Status bit that signals when a brownout is detected on the regulator output.
bits : 16 - 16 (1 bit)
access : read-only
OK_VDD2P5 : Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target
bits : 17 - 17 (1 bit)
access : read-only
ENABLE_WEAK_LINREG : Enables the weak 2p5 regulator
bits : 18 - 18 (1 bit)
access : read-write
Regulator 2P5 Register
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE_LINREG : Control bit to enable the regulator output.
bits : 0 - 0 (1 bit)
access : read-write
ENABLE_BO : Control bit to enable the brownout circuitry in the regulator.
bits : 1 - 1 (1 bit)
access : read-write
ENABLE_ILIMIT : Control bit to enable the current-limit circuitry in the regulator.
bits : 2 - 2 (1 bit)
access : read-write
ENABLE_PULLDOWN : Control bit to enable the pull-down circuitry in the regulator
bits : 3 - 3 (1 bit)
access : read-write
BO_OFFSET : Control bits to adjust the regulator brownout offset voltage in 25mV steps
bits : 4 - 6 (3 bit)
access : read-write
OUTPUT_TRG : Control bits to adjust the regulator output voltage
bits : 8 - 12 (5 bit)
access : read-write
Enumeration:
0 : OUTPUT_TRG_0
2.10V
0x10 : OUTPUT_TRG_16
2.50V
0x1F : OUTPUT_TRG_31
2.875V
End of enumeration elements list.
BO_VDD2P5 : Status bit that signals when a brownout is detected on the regulator output.
bits : 16 - 16 (1 bit)
access : read-only
OK_VDD2P5 : Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target
bits : 17 - 17 (1 bit)
access : read-only
ENABLE_WEAK_LINREG : Enables the weak 2p5 regulator
bits : 18 - 18 (1 bit)
access : read-write
Regulator 2P5 Register
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE_LINREG : Control bit to enable the regulator output.
bits : 0 - 0 (1 bit)
access : read-write
ENABLE_BO : Control bit to enable the brownout circuitry in the regulator.
bits : 1 - 1 (1 bit)
access : read-write
ENABLE_ILIMIT : Control bit to enable the current-limit circuitry in the regulator.
bits : 2 - 2 (1 bit)
access : read-write
ENABLE_PULLDOWN : Control bit to enable the pull-down circuitry in the regulator
bits : 3 - 3 (1 bit)
access : read-write
BO_OFFSET : Control bits to adjust the regulator brownout offset voltage in 25mV steps
bits : 4 - 6 (3 bit)
access : read-write
OUTPUT_TRG : Control bits to adjust the regulator output voltage
bits : 8 - 12 (5 bit)
access : read-write
Enumeration:
0 : OUTPUT_TRG_0
2.10V
0x10 : OUTPUT_TRG_16
2.50V
0x1F : OUTPUT_TRG_31
2.875V
End of enumeration elements list.
BO_VDD2P5 : Status bit that signals when a brownout is detected on the regulator output.
bits : 16 - 16 (1 bit)
access : read-only
OK_VDD2P5 : Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target
bits : 17 - 17 (1 bit)
access : read-only
ENABLE_WEAK_LINREG : Enables the weak 2p5 regulator
bits : 18 - 18 (1 bit)
access : read-write
Digital Regulator Core Register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REG0_TARG : This field defines the target voltage for the ARM core power domain
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : REG0_TARG_0
Power gated off
0x1 : REG0_TARG_1
Target core voltage = 0.725V
0x2 : REG0_TARG_2
Target core voltage = 0.750V
0x3 : REG0_TARG_3
Target core voltage = 0.775V
0x10 : REG0_TARG_16
Target core voltage = 1.100V
0x1E : REG0_TARG_30
Target core voltage = 1.450V
0x1F : REG0_TARG_31
Power FET switched full on. No regulation.
End of enumeration elements list.
REG0_ADJ : This bit field defines the adjustment bits to calibrate the target value of Reg0. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register.
bits : 5 - 8 (4 bit)
access : read-write
Enumeration:
0 : REG0_ADJ_0
No adjustment
0x1 : REG0_ADJ_1
+ 0.25%
0x2 : REG0_ADJ_2
+ 0.50%
0x3 : REG0_ADJ_3
+ 0.75%
0x4 : REG0_ADJ_4
+ 1.00%
0x5 : REG0_ADJ_5
+ 1.25%
0x6 : REG0_ADJ_6
+ 1.50%
0x7 : REG0_ADJ_7
+ 1.75%
0x8 : REG0_ADJ_8
- 0.25%
0x9 : REG0_ADJ_9
- 0.50%
0xA : REG0_ADJ_10
- 0.75%
0xB : REG0_ADJ_11
- 1.00%
0xC : REG0_ADJ_12
- 1.25%
0xD : REG0_ADJ_13
- 1.50%
0xE : REG0_ADJ_14
- 1.75%
0xF : REG0_ADJ_15
- 2.00%
End of enumeration elements list.
REG1_TARG : This bit field defines the target voltage for the vpu/gpu power domain. Single bit increments reflect 25mV core voltage steps. Not all steps will make sense to use either because of input supply limitations or load operation.
bits : 9 - 13 (5 bit)
access : read-write
Enumeration:
0 : REG1_TARG_0
Power gated off
0x1 : REG1_TARG_1
Target core voltage = 0.725V
0x2 : REG1_TARG_2
Target core voltage = 0.750V
0x3 : REG1_TARG_3
Target core voltage = 0.775V
0x10 : REG1_TARG_16
Target core voltage = 1.100V
0x1E : REG1_TARG_30
Target core voltage = 1.450V
0x1F : REG1_TARG_31
Power FET switched full on. No regulation.
End of enumeration elements list.
REG1_ADJ : This bit field defines the adjustment bits to calibrate the target value of Reg1. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register.
bits : 14 - 17 (4 bit)
access : read-write
Enumeration:
0 : REG1_ADJ_0
No adjustment
0x1 : REG1_ADJ_1
+ 0.25%
0x2 : REG1_ADJ_2
+ 0.50%
0x3 : REG1_ADJ_3
+ 0.75%
0x4 : REG1_ADJ_4
+ 1.00%
0x5 : REG1_ADJ_5
+ 1.25%
0x6 : REG1_ADJ_6
+ 1.50%
0x7 : REG1_ADJ_7
+ 1.75%
0x8 : REG1_ADJ_8
- 0.25%
0x9 : REG1_ADJ_9
- 0.50%
0xA : REG1_ADJ_10
- 0.75%
0xB : REG1_ADJ_11
- 1.00%
0xC : REG1_ADJ_12
- 1.25%
0xD : REG1_ADJ_13
- 1.50%
0xE : REG1_ADJ_14
- 1.75%
0xF : REG1_ADJ_15
- 2.00%
End of enumeration elements list.
REG2_TARG : This field defines the target voltage for the SOC power domain
bits : 18 - 22 (5 bit)
access : read-write
Enumeration:
0 : REG2_TARG_0
Power gated off
0x1 : REG2_TARG_1
Target core voltage = 0.725V
0x2 : REG2_TARG_2
Target core voltage = 0.750V
0x3 : REG2_TARG_3
Target core voltage = 0.775V
0x10 : REG2_TARG_16
Target core voltage = 1.100V
0x1E : REG2_TARG_30
Target core voltage = 1.450V
0x1F : REG2_TARG_31
Power FET switched full on. No regulation.
End of enumeration elements list.
REG2_ADJ : This bit field defines the adjustment bits to calibrate the target value of Reg2. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register.
bits : 23 - 26 (4 bit)
access : read-write
Enumeration:
0 : REG2_ADJ_0
No adjustment
0x1 : REG2_ADJ_1
+ 0.25%
0x2 : REG2_ADJ_2
+ 0.50%
0x3 : REG2_ADJ_3
+ 0.75%
0x4 : REG2_ADJ_4
+ 1.00%
0x5 : REG2_ADJ_5
+ 1.25%
0x6 : REG2_ADJ_6
+ 1.50%
0x7 : REG2_ADJ_7
+ 1.75%
0x8 : REG2_ADJ_8
- 0.25%
0x9 : REG2_ADJ_9
- 0.50%
0xA : REG2_ADJ_10
- 0.75%
0xB : REG2_ADJ_11
- 1.00%
0xC : REG2_ADJ_12
- 1.25%
0xD : REG2_ADJ_13
- 1.50%
0xE : REG2_ADJ_14
- 1.75%
0xF : REG2_ADJ_15
- 2.00%
End of enumeration elements list.
RAMP_RATE : Regulator voltage ramp rate.
bits : 27 - 28 (2 bit)
access : read-write
Enumeration:
0 : RAMP_RATE_0
Fast
0x1 : RAMP_RATE_1
Medium Fast
0x2 : RAMP_RATE_2
Medium Slow
0x3 : RAMP_RATE_3
Slow
End of enumeration elements list.
FET_ODRIVE : If set, increases the gate drive on power gating FETs to reduce leakage in the off state
bits : 29 - 29 (1 bit)
access : read-write
Digital Regulator Core Register
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REG0_TARG : This field defines the target voltage for the ARM core power domain
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : REG0_TARG_0
Power gated off
0x1 : REG0_TARG_1
Target core voltage = 0.725V
0x2 : REG0_TARG_2
Target core voltage = 0.750V
0x3 : REG0_TARG_3
Target core voltage = 0.775V
0x10 : REG0_TARG_16
Target core voltage = 1.100V
0x1E : REG0_TARG_30
Target core voltage = 1.450V
0x1F : REG0_TARG_31
Power FET switched full on. No regulation.
End of enumeration elements list.
REG0_ADJ : This bit field defines the adjustment bits to calibrate the target value of Reg0. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register.
bits : 5 - 8 (4 bit)
access : read-write
Enumeration:
0 : REG0_ADJ_0
No adjustment
0x1 : REG0_ADJ_1
+ 0.25%
0x2 : REG0_ADJ_2
+ 0.50%
0x3 : REG0_ADJ_3
+ 0.75%
0x4 : REG0_ADJ_4
+ 1.00%
0x5 : REG0_ADJ_5
+ 1.25%
0x6 : REG0_ADJ_6
+ 1.50%
0x7 : REG0_ADJ_7
+ 1.75%
0x8 : REG0_ADJ_8
- 0.25%
0x9 : REG0_ADJ_9
- 0.50%
0xA : REG0_ADJ_10
- 0.75%
0xB : REG0_ADJ_11
- 1.00%
0xC : REG0_ADJ_12
- 1.25%
0xD : REG0_ADJ_13
- 1.50%
0xE : REG0_ADJ_14
- 1.75%
0xF : REG0_ADJ_15
- 2.00%
End of enumeration elements list.
REG1_TARG : This bit field defines the target voltage for the vpu/gpu power domain. Single bit increments reflect 25mV core voltage steps. Not all steps will make sense to use either because of input supply limitations or load operation.
bits : 9 - 13 (5 bit)
access : read-write
Enumeration:
0 : REG1_TARG_0
Power gated off
0x1 : REG1_TARG_1
Target core voltage = 0.725V
0x2 : REG1_TARG_2
Target core voltage = 0.750V
0x3 : REG1_TARG_3
Target core voltage = 0.775V
0x10 : REG1_TARG_16
Target core voltage = 1.100V
0x1E : REG1_TARG_30
Target core voltage = 1.450V
0x1F : REG1_TARG_31
Power FET switched full on. No regulation.
End of enumeration elements list.
REG1_ADJ : This bit field defines the adjustment bits to calibrate the target value of Reg1. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register.
bits : 14 - 17 (4 bit)
access : read-write
Enumeration:
0 : REG1_ADJ_0
No adjustment
0x1 : REG1_ADJ_1
+ 0.25%
0x2 : REG1_ADJ_2
+ 0.50%
0x3 : REG1_ADJ_3
+ 0.75%
0x4 : REG1_ADJ_4
+ 1.00%
0x5 : REG1_ADJ_5
+ 1.25%
0x6 : REG1_ADJ_6
+ 1.50%
0x7 : REG1_ADJ_7
+ 1.75%
0x8 : REG1_ADJ_8
- 0.25%
0x9 : REG1_ADJ_9
- 0.50%
0xA : REG1_ADJ_10
- 0.75%
0xB : REG1_ADJ_11
- 1.00%
0xC : REG1_ADJ_12
- 1.25%
0xD : REG1_ADJ_13
- 1.50%
0xE : REG1_ADJ_14
- 1.75%
0xF : REG1_ADJ_15
- 2.00%
End of enumeration elements list.
REG2_TARG : This field defines the target voltage for the SOC power domain
bits : 18 - 22 (5 bit)
access : read-write
Enumeration:
0 : REG2_TARG_0
Power gated off
0x1 : REG2_TARG_1
Target core voltage = 0.725V
0x2 : REG2_TARG_2
Target core voltage = 0.750V
0x3 : REG2_TARG_3
Target core voltage = 0.775V
0x10 : REG2_TARG_16
Target core voltage = 1.100V
0x1E : REG2_TARG_30
Target core voltage = 1.450V
0x1F : REG2_TARG_31
Power FET switched full on. No regulation.
End of enumeration elements list.
REG2_ADJ : This bit field defines the adjustment bits to calibrate the target value of Reg2. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register.
bits : 23 - 26 (4 bit)
access : read-write
Enumeration:
0 : REG2_ADJ_0
No adjustment
0x1 : REG2_ADJ_1
+ 0.25%
0x2 : REG2_ADJ_2
+ 0.50%
0x3 : REG2_ADJ_3
+ 0.75%
0x4 : REG2_ADJ_4
+ 1.00%
0x5 : REG2_ADJ_5
+ 1.25%
0x6 : REG2_ADJ_6
+ 1.50%
0x7 : REG2_ADJ_7
+ 1.75%
0x8 : REG2_ADJ_8
- 0.25%
0x9 : REG2_ADJ_9
- 0.50%
0xA : REG2_ADJ_10
- 0.75%
0xB : REG2_ADJ_11
- 1.00%
0xC : REG2_ADJ_12
- 1.25%
0xD : REG2_ADJ_13
- 1.50%
0xE : REG2_ADJ_14
- 1.75%
0xF : REG2_ADJ_15
- 2.00%
End of enumeration elements list.
RAMP_RATE : Regulator voltage ramp rate.
bits : 27 - 28 (2 bit)
access : read-write
Enumeration:
0 : RAMP_RATE_0
Fast
0x1 : RAMP_RATE_1
Medium Fast
0x2 : RAMP_RATE_2
Medium Slow
0x3 : RAMP_RATE_3
Slow
End of enumeration elements list.
FET_ODRIVE : If set, increases the gate drive on power gating FETs to reduce leakage in the off state
bits : 29 - 29 (1 bit)
access : read-write
Digital Regulator Core Register
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REG0_TARG : This field defines the target voltage for the ARM core power domain
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : REG0_TARG_0
Power gated off
0x1 : REG0_TARG_1
Target core voltage = 0.725V
0x2 : REG0_TARG_2
Target core voltage = 0.750V
0x3 : REG0_TARG_3
Target core voltage = 0.775V
0x10 : REG0_TARG_16
Target core voltage = 1.100V
0x1E : REG0_TARG_30
Target core voltage = 1.450V
0x1F : REG0_TARG_31
Power FET switched full on. No regulation.
End of enumeration elements list.
REG0_ADJ : This bit field defines the adjustment bits to calibrate the target value of Reg0. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register.
bits : 5 - 8 (4 bit)
access : read-write
Enumeration:
0 : REG0_ADJ_0
No adjustment
0x1 : REG0_ADJ_1
+ 0.25%
0x2 : REG0_ADJ_2
+ 0.50%
0x3 : REG0_ADJ_3
+ 0.75%
0x4 : REG0_ADJ_4
+ 1.00%
0x5 : REG0_ADJ_5
+ 1.25%
0x6 : REG0_ADJ_6
+ 1.50%
0x7 : REG0_ADJ_7
+ 1.75%
0x8 : REG0_ADJ_8
- 0.25%
0x9 : REG0_ADJ_9
- 0.50%
0xA : REG0_ADJ_10
- 0.75%
0xB : REG0_ADJ_11
- 1.00%
0xC : REG0_ADJ_12
- 1.25%
0xD : REG0_ADJ_13
- 1.50%
0xE : REG0_ADJ_14
- 1.75%
0xF : REG0_ADJ_15
- 2.00%
End of enumeration elements list.
REG1_TARG : This bit field defines the target voltage for the vpu/gpu power domain. Single bit increments reflect 25mV core voltage steps. Not all steps will make sense to use either because of input supply limitations or load operation.
bits : 9 - 13 (5 bit)
access : read-write
Enumeration:
0 : REG1_TARG_0
Power gated off
0x1 : REG1_TARG_1
Target core voltage = 0.725V
0x2 : REG1_TARG_2
Target core voltage = 0.750V
0x3 : REG1_TARG_3
Target core voltage = 0.775V
0x10 : REG1_TARG_16
Target core voltage = 1.100V
0x1E : REG1_TARG_30
Target core voltage = 1.450V
0x1F : REG1_TARG_31
Power FET switched full on. No regulation.
End of enumeration elements list.
REG1_ADJ : This bit field defines the adjustment bits to calibrate the target value of Reg1. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register.
bits : 14 - 17 (4 bit)
access : read-write
Enumeration:
0 : REG1_ADJ_0
No adjustment
0x1 : REG1_ADJ_1
+ 0.25%
0x2 : REG1_ADJ_2
+ 0.50%
0x3 : REG1_ADJ_3
+ 0.75%
0x4 : REG1_ADJ_4
+ 1.00%
0x5 : REG1_ADJ_5
+ 1.25%
0x6 : REG1_ADJ_6
+ 1.50%
0x7 : REG1_ADJ_7
+ 1.75%
0x8 : REG1_ADJ_8
- 0.25%
0x9 : REG1_ADJ_9
- 0.50%
0xA : REG1_ADJ_10
- 0.75%
0xB : REG1_ADJ_11
- 1.00%
0xC : REG1_ADJ_12
- 1.25%
0xD : REG1_ADJ_13
- 1.50%
0xE : REG1_ADJ_14
- 1.75%
0xF : REG1_ADJ_15
- 2.00%
End of enumeration elements list.
REG2_TARG : This field defines the target voltage for the SOC power domain
bits : 18 - 22 (5 bit)
access : read-write
Enumeration:
0 : REG2_TARG_0
Power gated off
0x1 : REG2_TARG_1
Target core voltage = 0.725V
0x2 : REG2_TARG_2
Target core voltage = 0.750V
0x3 : REG2_TARG_3
Target core voltage = 0.775V
0x10 : REG2_TARG_16
Target core voltage = 1.100V
0x1E : REG2_TARG_30
Target core voltage = 1.450V
0x1F : REG2_TARG_31
Power FET switched full on. No regulation.
End of enumeration elements list.
REG2_ADJ : This bit field defines the adjustment bits to calibrate the target value of Reg2. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register.
bits : 23 - 26 (4 bit)
access : read-write
Enumeration:
0 : REG2_ADJ_0
No adjustment
0x1 : REG2_ADJ_1
+ 0.25%
0x2 : REG2_ADJ_2
+ 0.50%
0x3 : REG2_ADJ_3
+ 0.75%
0x4 : REG2_ADJ_4
+ 1.00%
0x5 : REG2_ADJ_5
+ 1.25%
0x6 : REG2_ADJ_6
+ 1.50%
0x7 : REG2_ADJ_7
+ 1.75%
0x8 : REG2_ADJ_8
- 0.25%
0x9 : REG2_ADJ_9
- 0.50%
0xA : REG2_ADJ_10
- 0.75%
0xB : REG2_ADJ_11
- 1.00%
0xC : REG2_ADJ_12
- 1.25%
0xD : REG2_ADJ_13
- 1.50%
0xE : REG2_ADJ_14
- 1.75%
0xF : REG2_ADJ_15
- 2.00%
End of enumeration elements list.
RAMP_RATE : Regulator voltage ramp rate.
bits : 27 - 28 (2 bit)
access : read-write
Enumeration:
0 : RAMP_RATE_0
Fast
0x1 : RAMP_RATE_1
Medium Fast
0x2 : RAMP_RATE_2
Medium Slow
0x3 : RAMP_RATE_3
Slow
End of enumeration elements list.
FET_ODRIVE : If set, increases the gate drive on power gating FETs to reduce leakage in the off state
bits : 29 - 29 (1 bit)
access : read-write
Digital Regulator Core Register
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REG0_TARG : This field defines the target voltage for the ARM core power domain
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : REG0_TARG_0
Power gated off
0x1 : REG0_TARG_1
Target core voltage = 0.725V
0x2 : REG0_TARG_2
Target core voltage = 0.750V
0x3 : REG0_TARG_3
Target core voltage = 0.775V
0x10 : REG0_TARG_16
Target core voltage = 1.100V
0x1E : REG0_TARG_30
Target core voltage = 1.450V
0x1F : REG0_TARG_31
Power FET switched full on. No regulation.
End of enumeration elements list.
REG0_ADJ : This bit field defines the adjustment bits to calibrate the target value of Reg0. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register.
bits : 5 - 8 (4 bit)
access : read-write
Enumeration:
0 : REG0_ADJ_0
No adjustment
0x1 : REG0_ADJ_1
+ 0.25%
0x2 : REG0_ADJ_2
+ 0.50%
0x3 : REG0_ADJ_3
+ 0.75%
0x4 : REG0_ADJ_4
+ 1.00%
0x5 : REG0_ADJ_5
+ 1.25%
0x6 : REG0_ADJ_6
+ 1.50%
0x7 : REG0_ADJ_7
+ 1.75%
0x8 : REG0_ADJ_8
- 0.25%
0x9 : REG0_ADJ_9
- 0.50%
0xA : REG0_ADJ_10
- 0.75%
0xB : REG0_ADJ_11
- 1.00%
0xC : REG0_ADJ_12
- 1.25%
0xD : REG0_ADJ_13
- 1.50%
0xE : REG0_ADJ_14
- 1.75%
0xF : REG0_ADJ_15
- 2.00%
End of enumeration elements list.
REG1_TARG : This bit field defines the target voltage for the vpu/gpu power domain. Single bit increments reflect 25mV core voltage steps. Not all steps will make sense to use either because of input supply limitations or load operation.
bits : 9 - 13 (5 bit)
access : read-write
Enumeration:
0 : REG1_TARG_0
Power gated off
0x1 : REG1_TARG_1
Target core voltage = 0.725V
0x2 : REG1_TARG_2
Target core voltage = 0.750V
0x3 : REG1_TARG_3
Target core voltage = 0.775V
0x10 : REG1_TARG_16
Target core voltage = 1.100V
0x1E : REG1_TARG_30
Target core voltage = 1.450V
0x1F : REG1_TARG_31
Power FET switched full on. No regulation.
End of enumeration elements list.
REG1_ADJ : This bit field defines the adjustment bits to calibrate the target value of Reg1. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register.
bits : 14 - 17 (4 bit)
access : read-write
Enumeration:
0 : REG1_ADJ_0
No adjustment
0x1 : REG1_ADJ_1
+ 0.25%
0x2 : REG1_ADJ_2
+ 0.50%
0x3 : REG1_ADJ_3
+ 0.75%
0x4 : REG1_ADJ_4
+ 1.00%
0x5 : REG1_ADJ_5
+ 1.25%
0x6 : REG1_ADJ_6
+ 1.50%
0x7 : REG1_ADJ_7
+ 1.75%
0x8 : REG1_ADJ_8
- 0.25%
0x9 : REG1_ADJ_9
- 0.50%
0xA : REG1_ADJ_10
- 0.75%
0xB : REG1_ADJ_11
- 1.00%
0xC : REG1_ADJ_12
- 1.25%
0xD : REG1_ADJ_13
- 1.50%
0xE : REG1_ADJ_14
- 1.75%
0xF : REG1_ADJ_15
- 2.00%
End of enumeration elements list.
REG2_TARG : This field defines the target voltage for the SOC power domain
bits : 18 - 22 (5 bit)
access : read-write
Enumeration:
0 : REG2_TARG_0
Power gated off
0x1 : REG2_TARG_1
Target core voltage = 0.725V
0x2 : REG2_TARG_2
Target core voltage = 0.750V
0x3 : REG2_TARG_3
Target core voltage = 0.775V
0x10 : REG2_TARG_16
Target core voltage = 1.100V
0x1E : REG2_TARG_30
Target core voltage = 1.450V
0x1F : REG2_TARG_31
Power FET switched full on. No regulation.
End of enumeration elements list.
REG2_ADJ : This bit field defines the adjustment bits to calibrate the target value of Reg2. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register.
bits : 23 - 26 (4 bit)
access : read-write
Enumeration:
0 : REG2_ADJ_0
No adjustment
0x1 : REG2_ADJ_1
+ 0.25%
0x2 : REG2_ADJ_2
+ 0.50%
0x3 : REG2_ADJ_3
+ 0.75%
0x4 : REG2_ADJ_4
+ 1.00%
0x5 : REG2_ADJ_5
+ 1.25%
0x6 : REG2_ADJ_6
+ 1.50%
0x7 : REG2_ADJ_7
+ 1.75%
0x8 : REG2_ADJ_8
- 0.25%
0x9 : REG2_ADJ_9
- 0.50%
0xA : REG2_ADJ_10
- 0.75%
0xB : REG2_ADJ_11
- 1.00%
0xC : REG2_ADJ_12
- 1.25%
0xD : REG2_ADJ_13
- 1.50%
0xE : REG2_ADJ_14
- 1.75%
0xF : REG2_ADJ_15
- 2.00%
End of enumeration elements list.
RAMP_RATE : Regulator voltage ramp rate.
bits : 27 - 28 (2 bit)
access : read-write
Enumeration:
0 : RAMP_RATE_0
Fast
0x1 : RAMP_RATE_1
Medium Fast
0x2 : RAMP_RATE_2
Medium Slow
0x3 : RAMP_RATE_3
Slow
End of enumeration elements list.
FET_ODRIVE : If set, increases the gate drive on power gating FETs to reduce leakage in the off state
bits : 29 - 29 (1 bit)
access : read-write
Miscellaneous Register 0
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REFTOP_PWD : Control bit to power-down the analog bandgap reference circuitry
bits : 0 - 0 (1 bit)
access : read-write
REFTOP_SELFBIASOFF : Control bit to disable the self-bias circuit in the analog bandgap
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : REFTOP_SELFBIASOFF_0
Uses coarse bias currents for startup
0x1 : REFTOP_SELFBIASOFF_1
Uses bandgap-based bias currents for best performance.
End of enumeration elements list.
REFTOP_VBGADJ : no description available
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0 : REFTOP_VBGADJ_0
Nominal VBG
0x1 : REFTOP_VBGADJ_1
VBG+0.78%
0x2 : REFTOP_VBGADJ_2
VBG+1.56%
0x3 : REFTOP_VBGADJ_3
VBG+2.34%
0x4 : REFTOP_VBGADJ_4
VBG-0.78%
0x5 : REFTOP_VBGADJ_5
VBG-1.56%
0x6 : REFTOP_VBGADJ_6
VBG-2.34%
0x7 : REFTOP_VBGADJ_7
VBG-3.12%
End of enumeration elements list.
REFTOP_VBGUP : Status bit that signals the analog bandgap voltage is up and stable. 1 - Stable.
bits : 7 - 7 (1 bit)
access : read-write
STOP_MODE_CONFIG : Configure the analog behavior in stop mode.
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0 : STOP_MODE_CONFIG_0
SUSPEND (DSM)
0x1 : STANDBY
Analog regulators are ON.
0x2 : STOP_MODE_CONFIG_2
STOP (lower power)
0x3 : STOP_MODE_CONFIG_3
STOP (very lower power)
End of enumeration elements list.
DISCON_HIGH_SNVS : This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : DISCON_HIGH_SNVS_0
Turn on the switch
0x1 : DISCON_HIGH_SNVS_1
Turn off the switch
End of enumeration elements list.
OSC_I : This field determines the bias current in the 24MHz oscillator
bits : 13 - 14 (2 bit)
access : read-write
Enumeration:
0 : NOMINAL
Nominal
0x1 : MINUS_12_5_PERCENT
Decrease current by 12.5%
0x2 : MINUS_25_PERCENT
Decrease current by 25.0%
0x3 : MINUS_37_5_PERCENT
Decrease current by 37.5%
End of enumeration elements list.
OSC_XTALOK : Status bit that signals that the output of the 24-MHz crystal oscillator is stable
bits : 15 - 15 (1 bit)
access : read-only
OSC_XTALOK_EN : This bit enables the detector that signals when the 24MHz crystal oscillator is stable
bits : 16 - 16 (1 bit)
access : read-write
CLKGATE_CTRL : This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : ALLOW_AUTO_GATE
Allow the logic to automatically gate the clock when the XTAL is powered down.
0x1 : NO_AUTO_GATE
Prevent the logic from ever gating off the clock.
End of enumeration elements list.
CLKGATE_DELAY : This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block
bits : 26 - 28 (3 bit)
access : read-write
Enumeration:
0 : CLKGATE_DELAY_0
0.5ms
0x1 : CLKGATE_DELAY_1
1.0ms
0x2 : CLKGATE_DELAY_2
2.0ms
0x3 : CLKGATE_DELAY_3
3.0ms
0x4 : CLKGATE_DELAY_4
4.0ms
0x5 : CLKGATE_DELAY_5
5.0ms
0x6 : CLKGATE_DELAY_6
6.0ms
0x7 : CLKGATE_DELAY_7
7.0ms
End of enumeration elements list.
RTC_XTAL_SOURCE : This field indicates which chip source is being used for the rtc clock.
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : RTC_XTAL_SOURCE_0
Internal ring oscillator
0x1 : RTC_XTAL_SOURCE_1
RTC_XTAL
End of enumeration elements list.
XTAL_24M_PWD : This field powers down the 24M crystal oscillator if set true.
bits : 30 - 30 (1 bit)
access : read-write
VID_PLL_PREDIV : Predivider for the source clock of the PLL's.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VID_PLL_PREDIV_0
Divide by 1
0x1 : VID_PLL_PREDIV_1
Divide by 2
End of enumeration elements list.
Miscellaneous Register 0
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REFTOP_PWD : Control bit to power-down the analog bandgap reference circuitry
bits : 0 - 0 (1 bit)
access : read-write
REFTOP_SELFBIASOFF : Control bit to disable the self-bias circuit in the analog bandgap
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : REFTOP_SELFBIASOFF_0
Uses coarse bias currents for startup
0x1 : REFTOP_SELFBIASOFF_1
Uses bandgap-based bias currents for best performance.
End of enumeration elements list.
REFTOP_VBGADJ : no description available
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0 : REFTOP_VBGADJ_0
Nominal VBG
0x1 : REFTOP_VBGADJ_1
VBG+0.78%
0x2 : REFTOP_VBGADJ_2
VBG+1.56%
0x3 : REFTOP_VBGADJ_3
VBG+2.34%
0x4 : REFTOP_VBGADJ_4
VBG-0.78%
0x5 : REFTOP_VBGADJ_5
VBG-1.56%
0x6 : REFTOP_VBGADJ_6
VBG-2.34%
0x7 : REFTOP_VBGADJ_7
VBG-3.12%
End of enumeration elements list.
REFTOP_VBGUP : Status bit that signals the analog bandgap voltage is up and stable. 1 - Stable.
bits : 7 - 7 (1 bit)
access : read-write
STOP_MODE_CONFIG : Configure the analog behavior in stop mode.
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0 : STOP_MODE_CONFIG_0
SUSPEND (DSM)
0x1 : STANDBY
Analog regulators are ON.
0x2 : STOP_MODE_CONFIG_2
STOP (lower power)
0x3 : STOP_MODE_CONFIG_3
STOP (very lower power)
End of enumeration elements list.
DISCON_HIGH_SNVS : This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : DISCON_HIGH_SNVS_0
Turn on the switch
0x1 : DISCON_HIGH_SNVS_1
Turn off the switch
End of enumeration elements list.
OSC_I : This field determines the bias current in the 24MHz oscillator
bits : 13 - 14 (2 bit)
access : read-write
Enumeration:
0 : NOMINAL
Nominal
0x1 : MINUS_12_5_PERCENT
Decrease current by 12.5%
0x2 : MINUS_25_PERCENT
Decrease current by 25.0%
0x3 : MINUS_37_5_PERCENT
Decrease current by 37.5%
End of enumeration elements list.
OSC_XTALOK : Status bit that signals that the output of the 24-MHz crystal oscillator is stable
bits : 15 - 15 (1 bit)
access : read-only
OSC_XTALOK_EN : This bit enables the detector that signals when the 24MHz crystal oscillator is stable
bits : 16 - 16 (1 bit)
access : read-write
CLKGATE_CTRL : This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : ALLOW_AUTO_GATE
Allow the logic to automatically gate the clock when the XTAL is powered down.
0x1 : NO_AUTO_GATE
Prevent the logic from ever gating off the clock.
End of enumeration elements list.
CLKGATE_DELAY : This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block
bits : 26 - 28 (3 bit)
access : read-write
Enumeration:
0 : CLKGATE_DELAY_0
0.5ms
0x1 : CLKGATE_DELAY_1
1.0ms
0x2 : CLKGATE_DELAY_2
2.0ms
0x3 : CLKGATE_DELAY_3
3.0ms
0x4 : CLKGATE_DELAY_4
4.0ms
0x5 : CLKGATE_DELAY_5
5.0ms
0x6 : CLKGATE_DELAY_6
6.0ms
0x7 : CLKGATE_DELAY_7
7.0ms
End of enumeration elements list.
RTC_XTAL_SOURCE : This field indicates which chip source is being used for the rtc clock.
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : RTC_XTAL_SOURCE_0
Internal ring oscillator
0x1 : RTC_XTAL_SOURCE_1
RTC_XTAL
End of enumeration elements list.
XTAL_24M_PWD : This field powers down the 24M crystal oscillator if set true.
bits : 30 - 30 (1 bit)
access : read-write
VID_PLL_PREDIV : Predivider for the source clock of the PLL's.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VID_PLL_PREDIV_0
Divide by 1
0x1 : VID_PLL_PREDIV_1
Divide by 2
End of enumeration elements list.
Miscellaneous Register 0
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REFTOP_PWD : Control bit to power-down the analog bandgap reference circuitry
bits : 0 - 0 (1 bit)
access : read-write
REFTOP_SELFBIASOFF : Control bit to disable the self-bias circuit in the analog bandgap
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : REFTOP_SELFBIASOFF_0
Uses coarse bias currents for startup
0x1 : REFTOP_SELFBIASOFF_1
Uses bandgap-based bias currents for best performance.
End of enumeration elements list.
REFTOP_VBGADJ : no description available
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0 : REFTOP_VBGADJ_0
Nominal VBG
0x1 : REFTOP_VBGADJ_1
VBG+0.78%
0x2 : REFTOP_VBGADJ_2
VBG+1.56%
0x3 : REFTOP_VBGADJ_3
VBG+2.34%
0x4 : REFTOP_VBGADJ_4
VBG-0.78%
0x5 : REFTOP_VBGADJ_5
VBG-1.56%
0x6 : REFTOP_VBGADJ_6
VBG-2.34%
0x7 : REFTOP_VBGADJ_7
VBG-3.12%
End of enumeration elements list.
REFTOP_VBGUP : Status bit that signals the analog bandgap voltage is up and stable. 1 - Stable.
bits : 7 - 7 (1 bit)
access : read-write
STOP_MODE_CONFIG : Configure the analog behavior in stop mode.
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0 : STOP_MODE_CONFIG_0
SUSPEND (DSM)
0x1 : STANDBY
Analog regulators are ON.
0x2 : STOP_MODE_CONFIG_2
STOP (lower power)
0x3 : STOP_MODE_CONFIG_3
STOP (very lower power)
End of enumeration elements list.
DISCON_HIGH_SNVS : This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : DISCON_HIGH_SNVS_0
Turn on the switch
0x1 : DISCON_HIGH_SNVS_1
Turn off the switch
End of enumeration elements list.
OSC_I : This field determines the bias current in the 24MHz oscillator
bits : 13 - 14 (2 bit)
access : read-write
Enumeration:
0 : NOMINAL
Nominal
0x1 : MINUS_12_5_PERCENT
Decrease current by 12.5%
0x2 : MINUS_25_PERCENT
Decrease current by 25.0%
0x3 : MINUS_37_5_PERCENT
Decrease current by 37.5%
End of enumeration elements list.
OSC_XTALOK : Status bit that signals that the output of the 24-MHz crystal oscillator is stable
bits : 15 - 15 (1 bit)
access : read-only
OSC_XTALOK_EN : This bit enables the detector that signals when the 24MHz crystal oscillator is stable
bits : 16 - 16 (1 bit)
access : read-write
CLKGATE_CTRL : This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : ALLOW_AUTO_GATE
Allow the logic to automatically gate the clock when the XTAL is powered down.
0x1 : NO_AUTO_GATE
Prevent the logic from ever gating off the clock.
End of enumeration elements list.
CLKGATE_DELAY : This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block
bits : 26 - 28 (3 bit)
access : read-write
Enumeration:
0 : CLKGATE_DELAY_0
0.5ms
0x1 : CLKGATE_DELAY_1
1.0ms
0x2 : CLKGATE_DELAY_2
2.0ms
0x3 : CLKGATE_DELAY_3
3.0ms
0x4 : CLKGATE_DELAY_4
4.0ms
0x5 : CLKGATE_DELAY_5
5.0ms
0x6 : CLKGATE_DELAY_6
6.0ms
0x7 : CLKGATE_DELAY_7
7.0ms
End of enumeration elements list.
RTC_XTAL_SOURCE : This field indicates which chip source is being used for the rtc clock.
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : RTC_XTAL_SOURCE_0
Internal ring oscillator
0x1 : RTC_XTAL_SOURCE_1
RTC_XTAL
End of enumeration elements list.
XTAL_24M_PWD : This field powers down the 24M crystal oscillator if set true.
bits : 30 - 30 (1 bit)
access : read-write
VID_PLL_PREDIV : Predivider for the source clock of the PLL's.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VID_PLL_PREDIV_0
Divide by 1
0x1 : VID_PLL_PREDIV_1
Divide by 2
End of enumeration elements list.
Miscellaneous Register 0
address_offset : 0x15C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REFTOP_PWD : Control bit to power-down the analog bandgap reference circuitry
bits : 0 - 0 (1 bit)
access : read-write
REFTOP_SELFBIASOFF : Control bit to disable the self-bias circuit in the analog bandgap
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : REFTOP_SELFBIASOFF_0
Uses coarse bias currents for startup
0x1 : REFTOP_SELFBIASOFF_1
Uses bandgap-based bias currents for best performance.
End of enumeration elements list.
REFTOP_VBGADJ : no description available
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0 : REFTOP_VBGADJ_0
Nominal VBG
0x1 : REFTOP_VBGADJ_1
VBG+0.78%
0x2 : REFTOP_VBGADJ_2
VBG+1.56%
0x3 : REFTOP_VBGADJ_3
VBG+2.34%
0x4 : REFTOP_VBGADJ_4
VBG-0.78%
0x5 : REFTOP_VBGADJ_5
VBG-1.56%
0x6 : REFTOP_VBGADJ_6
VBG-2.34%
0x7 : REFTOP_VBGADJ_7
VBG-3.12%
End of enumeration elements list.
REFTOP_VBGUP : Status bit that signals the analog bandgap voltage is up and stable. 1 - Stable.
bits : 7 - 7 (1 bit)
access : read-write
STOP_MODE_CONFIG : Configure the analog behavior in stop mode.
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0 : STOP_MODE_CONFIG_0
SUSPEND (DSM)
0x1 : STANDBY
Analog regulators are ON.
0x2 : STOP_MODE_CONFIG_2
STOP (lower power)
0x3 : STOP_MODE_CONFIG_3
STOP (very lower power)
End of enumeration elements list.
DISCON_HIGH_SNVS : This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : DISCON_HIGH_SNVS_0
Turn on the switch
0x1 : DISCON_HIGH_SNVS_1
Turn off the switch
End of enumeration elements list.
OSC_I : This field determines the bias current in the 24MHz oscillator
bits : 13 - 14 (2 bit)
access : read-write
Enumeration:
0 : NOMINAL
Nominal
0x1 : MINUS_12_5_PERCENT
Decrease current by 12.5%
0x2 : MINUS_25_PERCENT
Decrease current by 25.0%
0x3 : MINUS_37_5_PERCENT
Decrease current by 37.5%
End of enumeration elements list.
OSC_XTALOK : Status bit that signals that the output of the 24-MHz crystal oscillator is stable
bits : 15 - 15 (1 bit)
access : read-only
OSC_XTALOK_EN : This bit enables the detector that signals when the 24MHz crystal oscillator is stable
bits : 16 - 16 (1 bit)
access : read-write
CLKGATE_CTRL : This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : ALLOW_AUTO_GATE
Allow the logic to automatically gate the clock when the XTAL is powered down.
0x1 : NO_AUTO_GATE
Prevent the logic from ever gating off the clock.
End of enumeration elements list.
CLKGATE_DELAY : This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block
bits : 26 - 28 (3 bit)
access : read-write
Enumeration:
0 : CLKGATE_DELAY_0
0.5ms
0x1 : CLKGATE_DELAY_1
1.0ms
0x2 : CLKGATE_DELAY_2
2.0ms
0x3 : CLKGATE_DELAY_3
3.0ms
0x4 : CLKGATE_DELAY_4
4.0ms
0x5 : CLKGATE_DELAY_5
5.0ms
0x6 : CLKGATE_DELAY_6
6.0ms
0x7 : CLKGATE_DELAY_7
7.0ms
End of enumeration elements list.
RTC_XTAL_SOURCE : This field indicates which chip source is being used for the rtc clock.
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : RTC_XTAL_SOURCE_0
Internal ring oscillator
0x1 : RTC_XTAL_SOURCE_1
RTC_XTAL
End of enumeration elements list.
XTAL_24M_PWD : This field powers down the 24M crystal oscillator if set true.
bits : 30 - 30 (1 bit)
access : read-write
VID_PLL_PREDIV : Predivider for the source clock of the PLL's.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VID_PLL_PREDIV_0
Divide by 1
0x1 : VID_PLL_PREDIV_1
Divide by 2
End of enumeration elements list.
Miscellaneous Register 1
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LVDS1_CLK_SEL : This field selects the clk to be routed to anaclk1/1b.Not related to PMU.
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : ARM_PLL
Arm PLL
0x1 : SYS_PLL
System PLL
0x2 : PFD4
ref_pfd4_clk == pll2_pfd0_clk
0x3 : PFD5
ref_pfd5_clk == pll2_pfd1_clk
0x4 : PFD6
ref_pfd6_clk == pll2_pfd2_clk
0x5 : PFD7
ref_pfd7_clk == pll2_pfd3_clk
0x6 : AUDIO_PLL
Audio PLL
0x7 : VIDEO_PLL
Video PLL
0x9 : ETHERNET_REF
ethernet ref clock (ENET_PLL)
0xC : USB1_PLL
USB1 PLL clock
0xD : USB2_PLL
USB2 PLL clock
0xE : PFD0
ref_pfd0_clk == pll3_pfd0_clk
0xF : PFD1
ref_pfd1_clk == pll3_pfd1_clk
0x10 : PFD2
ref_pfd2_clk == pll3_pfd2_clk
0x11 : PFD3
ref_pfd3_clk == pll3_pfd3_clk
0x12 : XTAL
xtal (24M)
End of enumeration elements list.
LVDS2_CLK_SEL : This field selects the clk to be routed to anaclk2/2b.Not related to PMU.
bits : 5 - 9 (5 bit)
access : read-write
Enumeration:
0 : ARM_PLL
Arm PLL
0x1 : SYS_PLL
System PLL
0x2 : PFD4
ref_pfd4_clk == pll2_pfd0_clk
0x3 : PFD5
ref_pfd5_clk == pll2_pfd1_clk
0x4 : PFD6
ref_pfd6_clk == pll2_pfd2_clk
0x5 : PFD7
ref_pfd7_clk == pll2_pfd3_clk
0x6 : AUDIO_PLL
Audio PLL
0x7 : VIDEO_PLL
Video PLL
0x8 : MLB_PLL
MLB PLL
0x9 : ETHERNET_REF
ethernet ref clock (ENET_PLL)
0xA : PCIE_REF
PCIe ref clock (125M)
0xB : SATA_REF
SATA ref clock (100M)
0xC : USB1_PLL
USB1 PLL clock
0xD : USB2_PLL
USB2 PLL clock
0xE : PFD0
ref_pfd0_clk == pll3_pfd0_clk
0xF : PFD1
ref_pfd1_clk == pll3_pfd1_clk
0x10 : PFD2
ref_pfd2_clk == pll3_pfd2_clk
0x11 : PFD3
ref_pfd3_clk == pll3_pfd3_clk
0x12 : XTAL
xtal (24M)
0x13 : LVDS1
LVDS1 (loopback)
0x14 : LVDS2
LVDS2 (not useful)
End of enumeration elements list.
LVDSCLK1_OBEN : This enables the LVDS output buffer for anaclk1/1b
bits : 10 - 10 (1 bit)
access : read-write
LVDSCLK2_OBEN : This enables the LVDS output buffer for anaclk2/2b
bits : 11 - 11 (1 bit)
access : read-write
LVDSCLK1_IBEN : This enables the LVDS input buffer for anaclk1/1b
bits : 12 - 12 (1 bit)
access : read-write
LVDSCLK2_IBEN : This enables the LVDS input buffer for anaclk2/2b
bits : 13 - 13 (1 bit)
access : read-write
PFD_480_AUTOGATE_EN : This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off
bits : 16 - 16 (1 bit)
access : read-write
PFD_528_AUTOGATE_EN : This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off
bits : 17 - 17 (1 bit)
access : read-write
IRQ_TEMPPANIC : This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature
bits : 27 - 27 (1 bit)
access : read-write
IRQ_TEMPLOW : This status bit is set to one when the temperature sensor low interrupt asserts for low temperature
bits : 28 - 28 (1 bit)
access : read-write
IRQ_TEMPHIGH : This status bit is set to one when the temperature sensor high interrupt asserts for high temperature
bits : 29 - 29 (1 bit)
access : read-write
IRQ_ANA_BO : This status bit is set to one when when any of the analog regulator brownout interrupts assert
bits : 30 - 30 (1 bit)
access : read-write
IRQ_DIG_BO : This status bit is set to one when when any of the digital regulator brownout interrupts assert
bits : 31 - 31 (1 bit)
access : read-write
Miscellaneous Register 1
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LVDS1_CLK_SEL : This field selects the clk to be routed to anaclk1/1b.Not related to PMU.
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : ARM_PLL
Arm PLL
0x1 : SYS_PLL
System PLL
0x2 : PFD4
ref_pfd4_clk == pll2_pfd0_clk
0x3 : PFD5
ref_pfd5_clk == pll2_pfd1_clk
0x4 : PFD6
ref_pfd6_clk == pll2_pfd2_clk
0x5 : PFD7
ref_pfd7_clk == pll2_pfd3_clk
0x6 : AUDIO_PLL
Audio PLL
0x7 : VIDEO_PLL
Video PLL
0x9 : ETHERNET_REF
ethernet ref clock (ENET_PLL)
0xC : USB1_PLL
USB1 PLL clock
0xD : USB2_PLL
USB2 PLL clock
0xE : PFD0
ref_pfd0_clk == pll3_pfd0_clk
0xF : PFD1
ref_pfd1_clk == pll3_pfd1_clk
0x10 : PFD2
ref_pfd2_clk == pll3_pfd2_clk
0x11 : PFD3
ref_pfd3_clk == pll3_pfd3_clk
0x12 : XTAL
xtal (24M)
End of enumeration elements list.
LVDS2_CLK_SEL : This field selects the clk to be routed to anaclk2/2b.Not related to PMU.
bits : 5 - 9 (5 bit)
access : read-write
Enumeration:
0 : ARM_PLL
Arm PLL
0x1 : SYS_PLL
System PLL
0x2 : PFD4
ref_pfd4_clk == pll2_pfd0_clk
0x3 : PFD5
ref_pfd5_clk == pll2_pfd1_clk
0x4 : PFD6
ref_pfd6_clk == pll2_pfd2_clk
0x5 : PFD7
ref_pfd7_clk == pll2_pfd3_clk
0x6 : AUDIO_PLL
Audio PLL
0x7 : VIDEO_PLL
Video PLL
0x8 : MLB_PLL
MLB PLL
0x9 : ETHERNET_REF
ethernet ref clock (ENET_PLL)
0xA : PCIE_REF
PCIe ref clock (125M)
0xB : SATA_REF
SATA ref clock (100M)
0xC : USB1_PLL
USB1 PLL clock
0xD : USB2_PLL
USB2 PLL clock
0xE : PFD0
ref_pfd0_clk == pll3_pfd0_clk
0xF : PFD1
ref_pfd1_clk == pll3_pfd1_clk
0x10 : PFD2
ref_pfd2_clk == pll3_pfd2_clk
0x11 : PFD3
ref_pfd3_clk == pll3_pfd3_clk
0x12 : XTAL
xtal (24M)
0x13 : LVDS1
LVDS1 (loopback)
0x14 : LVDS2
LVDS2 (not useful)
End of enumeration elements list.
LVDSCLK1_OBEN : This enables the LVDS output buffer for anaclk1/1b
bits : 10 - 10 (1 bit)
access : read-write
LVDSCLK2_OBEN : This enables the LVDS output buffer for anaclk2/2b
bits : 11 - 11 (1 bit)
access : read-write
LVDSCLK1_IBEN : This enables the LVDS input buffer for anaclk1/1b
bits : 12 - 12 (1 bit)
access : read-write
LVDSCLK2_IBEN : This enables the LVDS input buffer for anaclk2/2b
bits : 13 - 13 (1 bit)
access : read-write
PFD_480_AUTOGATE_EN : This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off
bits : 16 - 16 (1 bit)
access : read-write
PFD_528_AUTOGATE_EN : This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off
bits : 17 - 17 (1 bit)
access : read-write
IRQ_TEMPPANIC : This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature
bits : 27 - 27 (1 bit)
access : read-write
IRQ_TEMPLOW : This status bit is set to one when the temperature sensor low interrupt asserts for low temperature
bits : 28 - 28 (1 bit)
access : read-write
IRQ_TEMPHIGH : This status bit is set to one when the temperature sensor high interrupt asserts for high temperature
bits : 29 - 29 (1 bit)
access : read-write
IRQ_ANA_BO : This status bit is set to one when when any of the analog regulator brownout interrupts assert
bits : 30 - 30 (1 bit)
access : read-write
IRQ_DIG_BO : This status bit is set to one when when any of the digital regulator brownout interrupts assert
bits : 31 - 31 (1 bit)
access : read-write
Miscellaneous Register 1
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LVDS1_CLK_SEL : This field selects the clk to be routed to anaclk1/1b.Not related to PMU.
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : ARM_PLL
Arm PLL
0x1 : SYS_PLL
System PLL
0x2 : PFD4
ref_pfd4_clk == pll2_pfd0_clk
0x3 : PFD5
ref_pfd5_clk == pll2_pfd1_clk
0x4 : PFD6
ref_pfd6_clk == pll2_pfd2_clk
0x5 : PFD7
ref_pfd7_clk == pll2_pfd3_clk
0x6 : AUDIO_PLL
Audio PLL
0x7 : VIDEO_PLL
Video PLL
0x9 : ETHERNET_REF
ethernet ref clock (ENET_PLL)
0xC : USB1_PLL
USB1 PLL clock
0xD : USB2_PLL
USB2 PLL clock
0xE : PFD0
ref_pfd0_clk == pll3_pfd0_clk
0xF : PFD1
ref_pfd1_clk == pll3_pfd1_clk
0x10 : PFD2
ref_pfd2_clk == pll3_pfd2_clk
0x11 : PFD3
ref_pfd3_clk == pll3_pfd3_clk
0x12 : XTAL
xtal (24M)
End of enumeration elements list.
LVDS2_CLK_SEL : This field selects the clk to be routed to anaclk2/2b.Not related to PMU.
bits : 5 - 9 (5 bit)
access : read-write
Enumeration:
0 : ARM_PLL
Arm PLL
0x1 : SYS_PLL
System PLL
0x2 : PFD4
ref_pfd4_clk == pll2_pfd0_clk
0x3 : PFD5
ref_pfd5_clk == pll2_pfd1_clk
0x4 : PFD6
ref_pfd6_clk == pll2_pfd2_clk
0x5 : PFD7
ref_pfd7_clk == pll2_pfd3_clk
0x6 : AUDIO_PLL
Audio PLL
0x7 : VIDEO_PLL
Video PLL
0x8 : MLB_PLL
MLB PLL
0x9 : ETHERNET_REF
ethernet ref clock (ENET_PLL)
0xA : PCIE_REF
PCIe ref clock (125M)
0xB : SATA_REF
SATA ref clock (100M)
0xC : USB1_PLL
USB1 PLL clock
0xD : USB2_PLL
USB2 PLL clock
0xE : PFD0
ref_pfd0_clk == pll3_pfd0_clk
0xF : PFD1
ref_pfd1_clk == pll3_pfd1_clk
0x10 : PFD2
ref_pfd2_clk == pll3_pfd2_clk
0x11 : PFD3
ref_pfd3_clk == pll3_pfd3_clk
0x12 : XTAL
xtal (24M)
0x13 : LVDS1
LVDS1 (loopback)
0x14 : LVDS2
LVDS2 (not useful)
End of enumeration elements list.
LVDSCLK1_OBEN : This enables the LVDS output buffer for anaclk1/1b
bits : 10 - 10 (1 bit)
access : read-write
LVDSCLK2_OBEN : This enables the LVDS output buffer for anaclk2/2b
bits : 11 - 11 (1 bit)
access : read-write
LVDSCLK1_IBEN : This enables the LVDS input buffer for anaclk1/1b
bits : 12 - 12 (1 bit)
access : read-write
LVDSCLK2_IBEN : This enables the LVDS input buffer for anaclk2/2b
bits : 13 - 13 (1 bit)
access : read-write
PFD_480_AUTOGATE_EN : This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off
bits : 16 - 16 (1 bit)
access : read-write
PFD_528_AUTOGATE_EN : This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off
bits : 17 - 17 (1 bit)
access : read-write
IRQ_TEMPPANIC : This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature
bits : 27 - 27 (1 bit)
access : read-write
IRQ_TEMPLOW : This status bit is set to one when the temperature sensor low interrupt asserts for low temperature
bits : 28 - 28 (1 bit)
access : read-write
IRQ_TEMPHIGH : This status bit is set to one when the temperature sensor high interrupt asserts for high temperature
bits : 29 - 29 (1 bit)
access : read-write
IRQ_ANA_BO : This status bit is set to one when when any of the analog regulator brownout interrupts assert
bits : 30 - 30 (1 bit)
access : read-write
IRQ_DIG_BO : This status bit is set to one when when any of the digital regulator brownout interrupts assert
bits : 31 - 31 (1 bit)
access : read-write
Miscellaneous Register 1
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LVDS1_CLK_SEL : This field selects the clk to be routed to anaclk1/1b.Not related to PMU.
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : ARM_PLL
Arm PLL
0x1 : SYS_PLL
System PLL
0x2 : PFD4
ref_pfd4_clk == pll2_pfd0_clk
0x3 : PFD5
ref_pfd5_clk == pll2_pfd1_clk
0x4 : PFD6
ref_pfd6_clk == pll2_pfd2_clk
0x5 : PFD7
ref_pfd7_clk == pll2_pfd3_clk
0x6 : AUDIO_PLL
Audio PLL
0x7 : VIDEO_PLL
Video PLL
0x9 : ETHERNET_REF
ethernet ref clock (ENET_PLL)
0xC : USB1_PLL
USB1 PLL clock
0xD : USB2_PLL
USB2 PLL clock
0xE : PFD0
ref_pfd0_clk == pll3_pfd0_clk
0xF : PFD1
ref_pfd1_clk == pll3_pfd1_clk
0x10 : PFD2
ref_pfd2_clk == pll3_pfd2_clk
0x11 : PFD3
ref_pfd3_clk == pll3_pfd3_clk
0x12 : XTAL
xtal (24M)
End of enumeration elements list.
LVDS2_CLK_SEL : This field selects the clk to be routed to anaclk2/2b.Not related to PMU.
bits : 5 - 9 (5 bit)
access : read-write
Enumeration:
0 : ARM_PLL
Arm PLL
0x1 : SYS_PLL
System PLL
0x2 : PFD4
ref_pfd4_clk == pll2_pfd0_clk
0x3 : PFD5
ref_pfd5_clk == pll2_pfd1_clk
0x4 : PFD6
ref_pfd6_clk == pll2_pfd2_clk
0x5 : PFD7
ref_pfd7_clk == pll2_pfd3_clk
0x6 : AUDIO_PLL
Audio PLL
0x7 : VIDEO_PLL
Video PLL
0x8 : MLB_PLL
MLB PLL
0x9 : ETHERNET_REF
ethernet ref clock (ENET_PLL)
0xA : PCIE_REF
PCIe ref clock (125M)
0xB : SATA_REF
SATA ref clock (100M)
0xC : USB1_PLL
USB1 PLL clock
0xD : USB2_PLL
USB2 PLL clock
0xE : PFD0
ref_pfd0_clk == pll3_pfd0_clk
0xF : PFD1
ref_pfd1_clk == pll3_pfd1_clk
0x10 : PFD2
ref_pfd2_clk == pll3_pfd2_clk
0x11 : PFD3
ref_pfd3_clk == pll3_pfd3_clk
0x12 : XTAL
xtal (24M)
0x13 : LVDS1
LVDS1 (loopback)
0x14 : LVDS2
LVDS2 (not useful)
End of enumeration elements list.
LVDSCLK1_OBEN : This enables the LVDS output buffer for anaclk1/1b
bits : 10 - 10 (1 bit)
access : read-write
LVDSCLK2_OBEN : This enables the LVDS output buffer for anaclk2/2b
bits : 11 - 11 (1 bit)
access : read-write
LVDSCLK1_IBEN : This enables the LVDS input buffer for anaclk1/1b
bits : 12 - 12 (1 bit)
access : read-write
LVDSCLK2_IBEN : This enables the LVDS input buffer for anaclk2/2b
bits : 13 - 13 (1 bit)
access : read-write
PFD_480_AUTOGATE_EN : This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off
bits : 16 - 16 (1 bit)
access : read-write
PFD_528_AUTOGATE_EN : This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off
bits : 17 - 17 (1 bit)
access : read-write
IRQ_TEMPPANIC : This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature
bits : 27 - 27 (1 bit)
access : read-write
IRQ_TEMPLOW : This status bit is set to one when the temperature sensor low interrupt asserts for low temperature
bits : 28 - 28 (1 bit)
access : read-write
IRQ_TEMPHIGH : This status bit is set to one when the temperature sensor high interrupt asserts for high temperature
bits : 29 - 29 (1 bit)
access : read-write
IRQ_ANA_BO : This status bit is set to one when when any of the analog regulator brownout interrupts assert
bits : 30 - 30 (1 bit)
access : read-write
IRQ_DIG_BO : This status bit is set to one when when any of the digital regulator brownout interrupts assert
bits : 31 - 31 (1 bit)
access : read-write
Miscellaneous Control Register
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REG0_BO_OFFSET : This field defines the brown out voltage offset for the CORE power domain
bits : 0 - 2 (3 bit)
access : read-only
Enumeration:
0x4 : REG0_BO_OFFSET_4
Brownout offset = 0.100V
0x7 : REG0_BO_OFFSET_7
Brownout offset = 0.175V
End of enumeration elements list.
REG0_BO_STATUS : Reg0 brownout status bit.
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0x1 : REG0_BO_STATUS_1
Brownout, supply is below target minus brownout offset.
End of enumeration elements list.
REG0_ENABLE_BO : Enables the brownout detection.
bits : 5 - 5 (1 bit)
access : read-write
PLL3_disable : Default value of "0"
bits : 7 - 7 (1 bit)
access : read-write
REG1_BO_OFFSET : This field defines the brown out voltage offset for the xPU power domain
bits : 8 - 10 (3 bit)
access : read-only
Enumeration:
0x4 : REG1_BO_OFFSET_4
Brownout offset = 0.100V
0x7 : REG1_BO_OFFSET_7
Brownout offset = 0.175V
End of enumeration elements list.
REG1_BO_STATUS : Reg1 brownout status bit.
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
0x1 : REG1_BO_STATUS_1
Brownout, supply is below target minus brownout offset.
End of enumeration elements list.
REG1_ENABLE_BO : Enables the brownout detection.
bits : 13 - 13 (1 bit)
access : read-write
AUDIO_DIV_LSB : LSB of Post-divider for Audio PLL
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : AUDIO_DIV_LSB_0
divide by 1 (Default)
0x1 : AUDIO_DIV_LSB_1
divide by 2
End of enumeration elements list.
REG2_BO_OFFSET : This field defines the brown out voltage offset for the xPU power domain
bits : 16 - 18 (3 bit)
access : read-only
Enumeration:
0x4 : REG2_BO_OFFSET_4
Brownout offset = 0.100V
0x7 : REG2_BO_OFFSET_7
Brownout offset = 0.175V
End of enumeration elements list.
REG2_BO_STATUS : Reg2 brownout status bit.
bits : 19 - 19 (1 bit)
access : read-only
REG2_ENABLE_BO : Enables the brownout detection.
bits : 21 - 21 (1 bit)
access : read-write
REG2_OK : Signals that the voltage is above the brownout level for the SOC supply
bits : 22 - 22 (1 bit)
access : read-only
AUDIO_DIV_MSB : MSB of Post-divider for Audio PLL
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : AUDIO_DIV_MSB_0
divide by 1 (Default)
0x1 : AUDIO_DIV_MSB_1
divide by 2
End of enumeration elements list.
REG0_STEP_TIME : Number of clock periods (24MHz clock).
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : 64_CLOCKS
64
0x1 : 128_CLOCKS
128
0x2 : 256_CLOCKS
256
0x3 : 512_CLOCKS
512
End of enumeration elements list.
REG1_STEP_TIME : Number of clock periods (24MHz clock).
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
0 : 64_CLOCKS
64
0x1 : 128_CLOCKS
128
0x2 : 256_CLOCKS
256
0x3 : 512_CLOCKS
512
End of enumeration elements list.
REG2_STEP_TIME : Number of clock periods (24MHz clock).
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0 : 64_CLOCKS
64
0x1 : 128_CLOCKS
128
0x2 : 256_CLOCKS
256
0x3 : 512_CLOCKS
512
End of enumeration elements list.
VIDEO_DIV : Post-divider for video
bits : 30 - 31 (2 bit)
access : read-write
Enumeration:
0 : VIDEO_DIV_0
divide by 1 (Default)
0x1 : VIDEO_DIV_1
divide by 2
0x2 : VIDEO_DIV_2
divide by 1
0x3 : VIDEO_DIV_3
divide by 4
End of enumeration elements list.
Miscellaneous Control Register
address_offset : 0x174 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REG0_BO_OFFSET : This field defines the brown out voltage offset for the CORE power domain
bits : 0 - 2 (3 bit)
access : read-only
Enumeration:
0x4 : REG0_BO_OFFSET_4
Brownout offset = 0.100V
0x7 : REG0_BO_OFFSET_7
Brownout offset = 0.175V
End of enumeration elements list.
REG0_BO_STATUS : Reg0 brownout status bit.
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0x1 : REG0_BO_STATUS_1
Brownout, supply is below target minus brownout offset.
End of enumeration elements list.
REG0_ENABLE_BO : Enables the brownout detection.
bits : 5 - 5 (1 bit)
access : read-write
PLL3_disable : Default value of "0"
bits : 7 - 7 (1 bit)
access : read-write
REG1_BO_OFFSET : This field defines the brown out voltage offset for the xPU power domain
bits : 8 - 10 (3 bit)
access : read-only
Enumeration:
0x4 : REG1_BO_OFFSET_4
Brownout offset = 0.100V
0x7 : REG1_BO_OFFSET_7
Brownout offset = 0.175V
End of enumeration elements list.
REG1_BO_STATUS : Reg1 brownout status bit.
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
0x1 : REG1_BO_STATUS_1
Brownout, supply is below target minus brownout offset.
End of enumeration elements list.
REG1_ENABLE_BO : Enables the brownout detection.
bits : 13 - 13 (1 bit)
access : read-write
AUDIO_DIV_LSB : LSB of Post-divider for Audio PLL
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : AUDIO_DIV_LSB_0
divide by 1 (Default)
0x1 : AUDIO_DIV_LSB_1
divide by 2
End of enumeration elements list.
REG2_BO_OFFSET : This field defines the brown out voltage offset for the xPU power domain
bits : 16 - 18 (3 bit)
access : read-only
Enumeration:
0x4 : REG2_BO_OFFSET_4
Brownout offset = 0.100V
0x7 : REG2_BO_OFFSET_7
Brownout offset = 0.175V
End of enumeration elements list.
REG2_BO_STATUS : Reg2 brownout status bit.
bits : 19 - 19 (1 bit)
access : read-only
REG2_ENABLE_BO : Enables the brownout detection.
bits : 21 - 21 (1 bit)
access : read-write
REG2_OK : Signals that the voltage is above the brownout level for the SOC supply
bits : 22 - 22 (1 bit)
access : read-only
AUDIO_DIV_MSB : MSB of Post-divider for Audio PLL
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : AUDIO_DIV_MSB_0
divide by 1 (Default)
0x1 : AUDIO_DIV_MSB_1
divide by 2
End of enumeration elements list.
REG0_STEP_TIME : Number of clock periods (24MHz clock).
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : 64_CLOCKS
64
0x1 : 128_CLOCKS
128
0x2 : 256_CLOCKS
256
0x3 : 512_CLOCKS
512
End of enumeration elements list.
REG1_STEP_TIME : Number of clock periods (24MHz clock).
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
0 : 64_CLOCKS
64
0x1 : 128_CLOCKS
128
0x2 : 256_CLOCKS
256
0x3 : 512_CLOCKS
512
End of enumeration elements list.
REG2_STEP_TIME : Number of clock periods (24MHz clock).
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0 : 64_CLOCKS
64
0x1 : 128_CLOCKS
128
0x2 : 256_CLOCKS
256
0x3 : 512_CLOCKS
512
End of enumeration elements list.
VIDEO_DIV : Post-divider for video
bits : 30 - 31 (2 bit)
access : read-write
Enumeration:
0 : VIDEO_DIV_0
divide by 1 (Default)
0x1 : VIDEO_DIV_1
divide by 2
0x2 : VIDEO_DIV_2
divide by 1
0x3 : VIDEO_DIV_3
divide by 4
End of enumeration elements list.
Miscellaneous Control Register
address_offset : 0x178 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REG0_BO_OFFSET : This field defines the brown out voltage offset for the CORE power domain
bits : 0 - 2 (3 bit)
access : read-only
Enumeration:
0x4 : REG0_BO_OFFSET_4
Brownout offset = 0.100V
0x7 : REG0_BO_OFFSET_7
Brownout offset = 0.175V
End of enumeration elements list.
REG0_BO_STATUS : Reg0 brownout status bit.
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0x1 : REG0_BO_STATUS_1
Brownout, supply is below target minus brownout offset.
End of enumeration elements list.
REG0_ENABLE_BO : Enables the brownout detection.
bits : 5 - 5 (1 bit)
access : read-write
PLL3_disable : Default value of "0"
bits : 7 - 7 (1 bit)
access : read-write
REG1_BO_OFFSET : This field defines the brown out voltage offset for the xPU power domain
bits : 8 - 10 (3 bit)
access : read-only
Enumeration:
0x4 : REG1_BO_OFFSET_4
Brownout offset = 0.100V
0x7 : REG1_BO_OFFSET_7
Brownout offset = 0.175V
End of enumeration elements list.
REG1_BO_STATUS : Reg1 brownout status bit.
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
0x1 : REG1_BO_STATUS_1
Brownout, supply is below target minus brownout offset.
End of enumeration elements list.
REG1_ENABLE_BO : Enables the brownout detection.
bits : 13 - 13 (1 bit)
access : read-write
AUDIO_DIV_LSB : LSB of Post-divider for Audio PLL
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : AUDIO_DIV_LSB_0
divide by 1 (Default)
0x1 : AUDIO_DIV_LSB_1
divide by 2
End of enumeration elements list.
REG2_BO_OFFSET : This field defines the brown out voltage offset for the xPU power domain
bits : 16 - 18 (3 bit)
access : read-only
Enumeration:
0x4 : REG2_BO_OFFSET_4
Brownout offset = 0.100V
0x7 : REG2_BO_OFFSET_7
Brownout offset = 0.175V
End of enumeration elements list.
REG2_BO_STATUS : Reg2 brownout status bit.
bits : 19 - 19 (1 bit)
access : read-only
REG2_ENABLE_BO : Enables the brownout detection.
bits : 21 - 21 (1 bit)
access : read-write
REG2_OK : Signals that the voltage is above the brownout level for the SOC supply
bits : 22 - 22 (1 bit)
access : read-only
AUDIO_DIV_MSB : MSB of Post-divider for Audio PLL
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : AUDIO_DIV_MSB_0
divide by 1 (Default)
0x1 : AUDIO_DIV_MSB_1
divide by 2
End of enumeration elements list.
REG0_STEP_TIME : Number of clock periods (24MHz clock).
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : 64_CLOCKS
64
0x1 : 128_CLOCKS
128
0x2 : 256_CLOCKS
256
0x3 : 512_CLOCKS
512
End of enumeration elements list.
REG1_STEP_TIME : Number of clock periods (24MHz clock).
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
0 : 64_CLOCKS
64
0x1 : 128_CLOCKS
128
0x2 : 256_CLOCKS
256
0x3 : 512_CLOCKS
512
End of enumeration elements list.
REG2_STEP_TIME : Number of clock periods (24MHz clock).
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0 : 64_CLOCKS
64
0x1 : 128_CLOCKS
128
0x2 : 256_CLOCKS
256
0x3 : 512_CLOCKS
512
End of enumeration elements list.
VIDEO_DIV : Post-divider for video
bits : 30 - 31 (2 bit)
access : read-write
Enumeration:
0 : VIDEO_DIV_0
divide by 1 (Default)
0x1 : VIDEO_DIV_1
divide by 2
0x2 : VIDEO_DIV_2
divide by 1
0x3 : VIDEO_DIV_3
divide by 4
End of enumeration elements list.
Miscellaneous Control Register
address_offset : 0x17C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REG0_BO_OFFSET : This field defines the brown out voltage offset for the CORE power domain
bits : 0 - 2 (3 bit)
access : read-only
Enumeration:
0x4 : REG0_BO_OFFSET_4
Brownout offset = 0.100V
0x7 : REG0_BO_OFFSET_7
Brownout offset = 0.175V
End of enumeration elements list.
REG0_BO_STATUS : Reg0 brownout status bit.
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0x1 : REG0_BO_STATUS_1
Brownout, supply is below target minus brownout offset.
End of enumeration elements list.
REG0_ENABLE_BO : Enables the brownout detection.
bits : 5 - 5 (1 bit)
access : read-write
PLL3_disable : Default value of "0"
bits : 7 - 7 (1 bit)
access : read-write
REG1_BO_OFFSET : This field defines the brown out voltage offset for the xPU power domain
bits : 8 - 10 (3 bit)
access : read-only
Enumeration:
0x4 : REG1_BO_OFFSET_4
Brownout offset = 0.100V
0x7 : REG1_BO_OFFSET_7
Brownout offset = 0.175V
End of enumeration elements list.
REG1_BO_STATUS : Reg1 brownout status bit.
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
0x1 : REG1_BO_STATUS_1
Brownout, supply is below target minus brownout offset.
End of enumeration elements list.
REG1_ENABLE_BO : Enables the brownout detection.
bits : 13 - 13 (1 bit)
access : read-write
AUDIO_DIV_LSB : LSB of Post-divider for Audio PLL
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : AUDIO_DIV_LSB_0
divide by 1 (Default)
0x1 : AUDIO_DIV_LSB_1
divide by 2
End of enumeration elements list.
REG2_BO_OFFSET : This field defines the brown out voltage offset for the xPU power domain
bits : 16 - 18 (3 bit)
access : read-only
Enumeration:
0x4 : REG2_BO_OFFSET_4
Brownout offset = 0.100V
0x7 : REG2_BO_OFFSET_7
Brownout offset = 0.175V
End of enumeration elements list.
REG2_BO_STATUS : Reg2 brownout status bit.
bits : 19 - 19 (1 bit)
access : read-only
REG2_ENABLE_BO : Enables the brownout detection.
bits : 21 - 21 (1 bit)
access : read-write
REG2_OK : Signals that the voltage is above the brownout level for the SOC supply
bits : 22 - 22 (1 bit)
access : read-only
AUDIO_DIV_MSB : MSB of Post-divider for Audio PLL
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : AUDIO_DIV_MSB_0
divide by 1 (Default)
0x1 : AUDIO_DIV_MSB_1
divide by 2
End of enumeration elements list.
REG0_STEP_TIME : Number of clock periods (24MHz clock).
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : 64_CLOCKS
64
0x1 : 128_CLOCKS
128
0x2 : 256_CLOCKS
256
0x3 : 512_CLOCKS
512
End of enumeration elements list.
REG1_STEP_TIME : Number of clock periods (24MHz clock).
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
0 : 64_CLOCKS
64
0x1 : 128_CLOCKS
128
0x2 : 256_CLOCKS
256
0x3 : 512_CLOCKS
512
End of enumeration elements list.
REG2_STEP_TIME : Number of clock periods (24MHz clock).
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0 : 64_CLOCKS
64
0x1 : 128_CLOCKS
128
0x2 : 256_CLOCKS
256
0x3 : 512_CLOCKS
512
End of enumeration elements list.
VIDEO_DIV : Post-divider for video
bits : 30 - 31 (2 bit)
access : read-write
Enumeration:
0 : VIDEO_DIV_0
divide by 1 (Default)
0x1 : VIDEO_DIV_1
divide by 2
0x2 : VIDEO_DIV_2
divide by 1
0x3 : VIDEO_DIV_3
divide by 4
End of enumeration elements list.
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