CTRL

CTR_ACC

STREAM_ADDR

STREAM_CTR

STREAM_FIFO

FLUSH

STAT

CTR_HIT

EN : When 1, enable the cache. When the cache is disabled, all XIP accesses will go straight to the flash, without querying the cache. When enabled, cacheable XIP accesses will query the cache, and the flash will not be accessed if the tag matches and the valid bit is set. If the cache is enabled, cache-as-SRAM accesses have no effect on the cache data RAM, and will produce a bus error response.
bits : 0 - 0 (1 bit)
access : read-write

ERR_BADWRITE : When 1, writes to any alias other than 0x0 (caching, allocating) will produce a bus fault. When 0, these writes are silently ignored. In either case, writes to the 0x0 alias will deallocate on tag match, as usual.
bits : 1 - 1 (1 bit)
access : read-write

POWER_DOWN : When 1, the cache memories are powered down. They retain state, but can not be accessed. This reduces static power dissipation. Writing 1 to this bit forces CTRL_EN to 0, i.e. the cache cannot be enabled when powered down. Cache-as-SRAM accesses will produce a bus error response when the cache is powered down.
bits : 3 - 3 (1 bit)
access : read-write

STREAM_ADDR : The address of the next word to be streamed from flash to the streaming FIFO. Increments automatically after each flash access. Write the initial access address here before starting a streaming read.
bits : 2 - 31 (30 bit)
access : read-write

STREAM_CTR : Write a nonzero value to start a streaming read. This will then progress in the background, using flash idle cycles to transfer a linear data block from flash to the streaming FIFO. Decrements automatically (1 at a time) as the stream progresses, and halts on reaching 0. Write 0 to halt an in-progress stream, and discard any in-flight read, so that a new stream can immediately be started (after draining the FIFO and reinitialising STREAM_ADDR)
bits : 0 - 21 (22 bit)
access : read-write

FLUSH : Write 1 to flush the cache. This clears the tag memory, but the data memory retains its contents. (This means cache-as-SRAM contents is not affected by flush or reset.) Reading will hold the bus (stall the processor) until the flush completes. Alternatively STAT can be polled until completion.
bits : 0 - 0 (1 bit)
access : read-write

FLUSH_READY : Reads as 0 while a cache flush is in progress, and 1 otherwise. The cache is flushed whenever the XIP block is reset, and also when requested via the FLUSH register.
bits : 0 - 0 (1 bit)
access : read-only

FIFO_EMPTY : When 1, indicates the XIP streaming FIFO is completely empty.
bits : 1 - 1 (1 bit)
access : read-only

FIFO_FULL : When 1, indicates the XIP streaming FIFO is completely full. The streaming FIFO is 2 entries deep, so the full and empty flag allow its level to be ascertained.
bits : 2 - 2 (1 bit)
access : read-only