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XIP_SSI

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CTRLR0

SER

BAUDR

TXFTLR

RXFTLR

TXFLR

RXFLR

SR

IMR

ISR

RISR

TXOICR

RXOICR

CTRLR1

RXUICR

MSTICR

ICR

DMACR

DMATDLR

DMARDLR

IDR

SSI_VERSION_ID

DR0

SSIENR

MWCR

RX_SAMPLE_DLY

SPI_CTRLR0

TXD_DRIVE_EDGE


CTRLR0

Control register 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRLR0 CTRLR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DFS FRF SCPH SCPOL TMOD SLV_OE SRL CFS DFS_32 SPI_FRF SSTE

DFS : Data frame size
bits : 0 - 3 (4 bit)
access : read-write

FRF : Frame format
bits : 4 - 5 (2 bit)
access : read-write

SCPH : Serial clock phase
bits : 6 - 6 (1 bit)
access : read-write

SCPOL : Serial clock polarity
bits : 7 - 7 (1 bit)
access : read-write

TMOD : Transfer mode
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : TX_AND_RX

Both transmit and receive

1 : TX_ONLY

Transmit only (not for FRF == 0, standard SPI mode)

2 : RX_ONLY

Receive only (not for FRF == 0, standard SPI mode)

3 : EEPROM_READ

EEPROM read mode (TX then RX RX starts after control data TX'd)

End of enumeration elements list.

SLV_OE : Slave output enable
bits : 10 - 10 (1 bit)
access : read-write

SRL : Shift register loop (test mode)
bits : 11 - 11 (1 bit)
access : read-write

CFS : Control frame size Value of n -> n+1 clocks per frame.
bits : 12 - 15 (4 bit)
access : read-write

DFS_32 : Data frame size in 32b transfer mode Value of n -> n+1 clocks per frame.
bits : 16 - 20 (5 bit)
access : read-write

SPI_FRF : SPI frame format
bits : 21 - 22 (2 bit)
access : read-write

Enumeration:

0 : STD

Standard 1-bit SPI frame format 1 bit per SCK, full-duplex

1 : DUAL

Dual-SPI frame format two bits per SCK, half-duplex

2 : QUAD

Quad-SPI frame format four bits per SCK, half-duplex

End of enumeration elements list.

SSTE : Slave select toggle enable
bits : 24 - 24 (1 bit)
access : read-write


SER

Slave enable
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SER SER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SER

SER : For each bit: 0 -> slave not selected 1 -> slave selected
bits : 0 - 0 (1 bit)
access : read-write


BAUDR

Baud rate
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BAUDR BAUDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCKDV

SCKDV : SSI clock divider
bits : 0 - 15 (16 bit)
access : read-write


TXFTLR

TX FIFO threshold level
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXFTLR TXFTLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TFT

TFT : Transmit FIFO threshold
bits : 0 - 7 (8 bit)
access : read-write


RXFTLR

RX FIFO threshold level
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXFTLR RXFTLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RFT

RFT : Receive FIFO threshold
bits : 0 - 7 (8 bit)
access : read-write


TXFLR

TX FIFO level
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXFLR TXFLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TFTFL

TFTFL : Transmit FIFO level
bits : 0 - 7 (8 bit)
access : read-only


RXFLR

RX FIFO level
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXFLR RXFLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXTFL

RXTFL : Receive FIFO level
bits : 0 - 7 (8 bit)
access : read-only


SR

Status register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SR SR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUSY TFNF TFE RFNE RFF TXE DCOL

BUSY : SSI busy flag
bits : 0 - 0 (1 bit)
access : read-only

TFNF : Transmit FIFO not full
bits : 1 - 1 (1 bit)
access : read-only

TFE : Transmit FIFO empty
bits : 2 - 2 (1 bit)
access : read-only

RFNE : Receive FIFO not empty
bits : 3 - 3 (1 bit)
access : read-only

RFF : Receive FIFO full
bits : 4 - 4 (1 bit)
access : read-only

TXE : Transmission error
bits : 5 - 5 (1 bit)
access : read-only

DCOL : Data collision error
bits : 6 - 6 (1 bit)
access : read-only


IMR

Interrupt mask
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMR IMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXEIM TXOIM RXUIM RXOIM RXFIM MSTIM

TXEIM : Transmit FIFO empty interrupt mask
bits : 0 - 0 (1 bit)
access : read-write

TXOIM : Transmit FIFO overflow interrupt mask
bits : 1 - 1 (1 bit)
access : read-write

RXUIM : Receive FIFO underflow interrupt mask
bits : 2 - 2 (1 bit)
access : read-write

RXOIM : Receive FIFO overflow interrupt mask
bits : 3 - 3 (1 bit)
access : read-write

RXFIM : Receive FIFO full interrupt mask
bits : 4 - 4 (1 bit)
access : read-write

MSTIM : Multi-master contention interrupt mask
bits : 5 - 5 (1 bit)
access : read-write


ISR

Interrupt status
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISR ISR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXEIS TXOIS RXUIS RXOIS RXFIS MSTIS

TXEIS : Transmit FIFO empty interrupt status
bits : 0 - 0 (1 bit)
access : read-only

TXOIS : Transmit FIFO overflow interrupt status
bits : 1 - 1 (1 bit)
access : read-only

RXUIS : Receive FIFO underflow interrupt status
bits : 2 - 2 (1 bit)
access : read-only

RXOIS : Receive FIFO overflow interrupt status
bits : 3 - 3 (1 bit)
access : read-only

RXFIS : Receive FIFO full interrupt status
bits : 4 - 4 (1 bit)
access : read-only

MSTIS : Multi-master contention interrupt status
bits : 5 - 5 (1 bit)
access : read-only


RISR

Raw interrupt status
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RISR RISR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXEIR TXOIR RXUIR RXOIR RXFIR MSTIR

TXEIR : Transmit FIFO empty raw interrupt status
bits : 0 - 0 (1 bit)
access : read-only

TXOIR : Transmit FIFO overflow raw interrupt status
bits : 1 - 1 (1 bit)
access : read-only

RXUIR : Receive FIFO underflow raw interrupt status
bits : 2 - 2 (1 bit)
access : read-only

RXOIR : Receive FIFO overflow raw interrupt status
bits : 3 - 3 (1 bit)
access : read-only

RXFIR : Receive FIFO full raw interrupt status
bits : 4 - 4 (1 bit)
access : read-only

MSTIR : Multi-master contention raw interrupt status
bits : 5 - 5 (1 bit)
access : read-only


TXOICR

TX FIFO overflow interrupt clear
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXOICR TXOICR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXOICR

TXOICR : Clear-on-read transmit FIFO overflow interrupt
bits : 0 - 0 (1 bit)
access : read-only


RXOICR

RX FIFO overflow interrupt clear
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXOICR RXOICR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXOICR

RXOICR : Clear-on-read receive FIFO overflow interrupt
bits : 0 - 0 (1 bit)
access : read-only


CTRLR1

Master Control register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRLR1 CTRLR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDF

NDF : Number of data frames
bits : 0 - 15 (16 bit)
access : read-write


RXUICR

RX FIFO underflow interrupt clear
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXUICR RXUICR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXUICR

RXUICR : Clear-on-read receive FIFO underflow interrupt
bits : 0 - 0 (1 bit)
access : read-only


MSTICR

Multi-master interrupt clear
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MSTICR MSTICR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MSTICR

MSTICR : Clear-on-read multi-master contention interrupt
bits : 0 - 0 (1 bit)
access : read-only


ICR

Interrupt clear
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICR ICR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ICR

ICR : Clear-on-read all active interrupts
bits : 0 - 0 (1 bit)
access : read-only


DMACR

DMA control
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMACR DMACR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDMAE TDMAE

RDMAE : Receive DMA enable
bits : 0 - 0 (1 bit)
access : read-write

TDMAE : Transmit DMA enable
bits : 1 - 1 (1 bit)
access : read-write


DMATDLR

DMA TX data level
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMATDLR DMATDLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMATDL

DMATDL : Transmit data watermark level
bits : 0 - 7 (8 bit)
access : read-write


DMARDLR

DMA RX data level
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMARDLR DMARDLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMARDL

DMARDL : Receive data watermark level (DMARDLR+1)
bits : 0 - 7 (8 bit)
access : read-write


IDR

Identification register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IDR IDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDCODE

IDCODE : Peripheral dentification code
bits : 0 - 31 (32 bit)
access : read-only


SSI_VERSION_ID

Version ID
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSI_VERSION_ID SSI_VERSION_ID read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SSI_COMP_VERSION

SSI_COMP_VERSION : SNPS component version (format X.YY)
bits : 0 - 31 (32 bit)
access : read-only


DR0

Data Register 0 (of 36)
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DR0 DR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DR

DR : First data register of 36
bits : 0 - 31 (32 bit)
access : read-write


SSIENR

SSI Enable
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSIENR SSIENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SSI_EN

SSI_EN : SSI enable
bits : 0 - 0 (1 bit)
access : read-write


MWCR

Microwire Control
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MWCR MWCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MWMOD MDD MHS

MWMOD : Microwire transfer mode
bits : 0 - 0 (1 bit)
access : read-write

MDD : Microwire control
bits : 1 - 1 (1 bit)
access : read-write

MHS : Microwire handshaking
bits : 2 - 2 (1 bit)
access : read-write


RX_SAMPLE_DLY

RX sample delay
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RX_SAMPLE_DLY RX_SAMPLE_DLY read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSD

RSD : RXD sample delay (in SCLK cycles)
bits : 0 - 7 (8 bit)
access : read-write


SPI_CTRLR0

SPI control
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPI_CTRLR0 SPI_CTRLR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRANS_TYPE ADDR_L INST_L WAIT_CYCLES SPI_DDR_EN INST_DDR_EN SPI_RXDS_EN XIP_CMD

TRANS_TYPE : Address and instruction transfer format
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : 1C1A

Command and address both in standard SPI frame format

1 : 1C2A

Command in standard SPI format, address in format specified by FRF

2 : 2C2A

Command and address both in format specified by FRF (e.g. Dual-SPI)

End of enumeration elements list.

ADDR_L : Address length (0b-60b in 4b increments)
bits : 2 - 5 (4 bit)
access : read-write

INST_L : Instruction length (0/4/8/16b)
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : NONE

No instruction

1 : 4B

4-bit instruction

2 : 8B

8-bit instruction

3 : 16B

16-bit instruction

End of enumeration elements list.

WAIT_CYCLES : Wait cycles between control frame transmit and data reception (in SCLK cycles)
bits : 11 - 15 (5 bit)
access : read-write

SPI_DDR_EN : SPI DDR transfer enable
bits : 16 - 16 (1 bit)
access : read-write

INST_DDR_EN : Instruction DDR transfer enable
bits : 17 - 17 (1 bit)
access : read-write

SPI_RXDS_EN : Read data strobe enable
bits : 18 - 18 (1 bit)
access : read-write

XIP_CMD : SPI Command to send in XIP mode (INST_L = 8-bit) or to append to Address (INST_L = 0-bit)
bits : 24 - 31 (8 bit)
access : read-write


TXD_DRIVE_EDGE

TX drive edge
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXD_DRIVE_EDGE TXD_DRIVE_EDGE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TDE

TDE : TXD drive edge
bits : 0 - 7 (8 bit)
access : read-write



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