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SYSCFG

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

PROC0_NMI_MASK

PROC_IN_SYNC_BYPASS_HI

DBGFORCE

MEMPOWERDOWN

PROC1_NMI_MASK

PROC_CONFIG

PROC_IN_SYNC_BYPASS


PROC0_NMI_MASK

Processor core 0 NMI source mask Set a bit high to enable NMI from that IRQ
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PROC0_NMI_MASK PROC0_NMI_MASK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PROC_IN_SYNC_BYPASS_HI

For each bit, if 1, bypass the input synchronizer between that GPIO and the GPIO input register in the SIO. The input synchronizers should generally be unbypassed, to avoid injecting metastabilities into processors. If you're feeling brave, you can bypass to save two cycles of input latency. This register applies to GPIO 30...35 (the QSPI IOs).
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PROC_IN_SYNC_BYPASS_HI PROC_IN_SYNC_BYPASS_HI read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROC_IN_SYNC_BYPASS_HI

PROC_IN_SYNC_BYPASS_HI :
bits : 0 - 5 (6 bit)
access : read-write


DBGFORCE

Directly control the SWD debug port of either processor
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DBGFORCE DBGFORCE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROC0_SWDO PROC0_SWDI PROC0_SWCLK PROC0_ATTACH PROC1_SWDO PROC1_SWDI PROC1_SWCLK PROC1_ATTACH

PROC0_SWDO : Observe the value of processor 0 SWDIO output.
bits : 0 - 0 (1 bit)
access : read-only

PROC0_SWDI : Directly drive processor 0 SWDIO input, if PROC0_ATTACH is set
bits : 1 - 1 (1 bit)
access : read-write

PROC0_SWCLK : Directly drive processor 0 SWCLK, if PROC0_ATTACH is set
bits : 2 - 2 (1 bit)
access : read-write

PROC0_ATTACH : Attach processor 0 debug port to syscfg controls, and disconnect it from external SWD pads.
bits : 3 - 3 (1 bit)
access : read-write

PROC1_SWDO : Observe the value of processor 1 SWDIO output.
bits : 4 - 4 (1 bit)
access : read-only

PROC1_SWDI : Directly drive processor 1 SWDIO input, if PROC1_ATTACH is set
bits : 5 - 5 (1 bit)
access : read-write

PROC1_SWCLK : Directly drive processor 1 SWCLK, if PROC1_ATTACH is set
bits : 6 - 6 (1 bit)
access : read-write

PROC1_ATTACH : Attach processor 1 debug port to syscfg controls, and disconnect it from external SWD pads.
bits : 7 - 7 (1 bit)
access : read-write


MEMPOWERDOWN

Control power downs to memories. Set high to power down memories. Use with extreme caution
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MEMPOWERDOWN MEMPOWERDOWN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRAM0 SRAM1 SRAM2 SRAM3 SRAM4 SRAM5 USB ROM

SRAM0 :
bits : 0 - 0 (1 bit)
access : read-write

SRAM1 :
bits : 1 - 1 (1 bit)
access : read-write

SRAM2 :
bits : 2 - 2 (1 bit)
access : read-write

SRAM3 :
bits : 3 - 3 (1 bit)
access : read-write

SRAM4 :
bits : 4 - 4 (1 bit)
access : read-write

SRAM5 :
bits : 5 - 5 (1 bit)
access : read-write

USB :
bits : 6 - 6 (1 bit)
access : read-write

ROM :
bits : 7 - 7 (1 bit)
access : read-write


PROC1_NMI_MASK

Processor core 1 NMI source mask Set a bit high to enable NMI from that IRQ
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PROC1_NMI_MASK PROC1_NMI_MASK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PROC_CONFIG

Configuration for processors
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PROC_CONFIG PROC_CONFIG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROC0_HALTED PROC1_HALTED PROC0_DAP_INSTID PROC1_DAP_INSTID

PROC0_HALTED : Indication that proc0 has halted
bits : 0 - 0 (1 bit)
access : read-only

PROC1_HALTED : Indication that proc1 has halted
bits : 1 - 1 (1 bit)
access : read-only

PROC0_DAP_INSTID : Configure proc0 DAP instance ID. Recommend that this is NOT changed until you require debug access in multi-chip environment WARNING: do not set to 15 as this is reserved for RescueDP
bits : 24 - 27 (4 bit)
access : read-write

PROC1_DAP_INSTID : Configure proc1 DAP instance ID. Recommend that this is NOT changed until you require debug access in multi-chip environment WARNING: do not set to 15 as this is reserved for RescueDP
bits : 28 - 31 (4 bit)
access : read-write


PROC_IN_SYNC_BYPASS

For each bit, if 1, bypass the input synchronizer between that GPIO and the GPIO input register in the SIO. The input synchronizers should generally be unbypassed, to avoid injecting metastabilities into processors. If you're feeling brave, you can bypass to save two cycles of input latency. This register applies to GPIO 0...29.
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PROC_IN_SYNC_BYPASS PROC_IN_SYNC_BYPASS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROC_IN_SYNC_BYPASS

PROC_IN_SYNC_BYPASS :
bits : 0 - 29 (30 bit)
access : read-write



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