Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
Clock control, can be changed on-the-fly (except for auxsrc)
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AUXSRC : Selects the auxiliary clock source, will glitch when switching
bits : 5 - 8 (4 bit)
access : read-write
Enumeration:
0 : clksrc_pll_sys
None
1 : clksrc_gpin0
None
2 : clksrc_gpin1
None
3 : clksrc_pll_usb
None
4 : rosc_clksrc
None
5 : xosc_clksrc
None
6 : clk_sys
None
7 : clk_usb
None
8 : clk_adc
None
9 : clk_rtc
None
10 : clk_ref
None
End of enumeration elements list.
KILL : Asynchronously kills the clock generator
bits : 10 - 10 (1 bit)
access : read-write
ENABLE : Starts and stops the clock generator cleanly
bits : 11 - 11 (1 bit)
access : read-write
DC50 : Enables duty cycle correction for odd divisors
bits : 12 - 12 (1 bit)
access : read-write
PHASE : This delays the enable signal by up to 3 cycles of the input clock
This must be set before the clock is enabled to have any effect
bits : 16 - 17 (2 bit)
access : read-write
NUDGE : An edge on this signal shifts the phase of the output by 1 cycle of the input clock
This can be done at any time
bits : 20 - 20 (1 bit)
access : read-write
Clock divisor, can be changed on-the-fly
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRAC : Fractional component of the divisor
bits : 0 - 7 (8 bit)
access : read-write
INT : Integer component of the divisor, 0 -> divide by 2^16
bits : 8 - 31 (24 bit)
access : read-write
Indicates which SRC is currently selected by the glitchless mux (one-hot).
This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Clock control, can be changed on-the-fly (except for auxsrc)
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AUXSRC : Selects the auxiliary clock source, will glitch when switching
bits : 5 - 8 (4 bit)
access : read-write
Enumeration:
0 : clksrc_pll_sys
None
1 : clksrc_gpin0
None
2 : clksrc_gpin1
None
3 : clksrc_pll_usb
None
4 : rosc_clksrc_ph
None
5 : xosc_clksrc
None
6 : clk_sys
None
7 : clk_usb
None
8 : clk_adc
None
9 : clk_rtc
None
10 : clk_ref
None
End of enumeration elements list.
KILL : Asynchronously kills the clock generator
bits : 10 - 10 (1 bit)
access : read-write
ENABLE : Starts and stops the clock generator cleanly
bits : 11 - 11 (1 bit)
access : read-write
DC50 : Enables duty cycle correction for odd divisors
bits : 12 - 12 (1 bit)
access : read-write
PHASE : This delays the enable signal by up to 3 cycles of the input clock
This must be set before the clock is enabled to have any effect
bits : 16 - 17 (2 bit)
access : read-write
NUDGE : An edge on this signal shifts the phase of the output by 1 cycle of the input clock
This can be done at any time
bits : 20 - 20 (1 bit)
access : read-write
Clock divisor, can be changed on-the-fly
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRAC : Fractional component of the divisor
bits : 0 - 7 (8 bit)
access : read-write
INT : Integer component of the divisor, 0 -> divide by 2^16
bits : 8 - 31 (24 bit)
access : read-write
Indicates which SRC is currently selected by the glitchless mux (one-hot).
This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Clock control, can be changed on-the-fly (except for auxsrc)
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AUXSRC : Selects the auxiliary clock source, will glitch when switching
bits : 5 - 8 (4 bit)
access : read-write
Enumeration:
0 : clksrc_pll_sys
None
1 : clksrc_gpin0
None
2 : clksrc_gpin1
None
3 : clksrc_pll_usb
None
4 : rosc_clksrc_ph
None
5 : xosc_clksrc
None
6 : clk_sys
None
7 : clk_usb
None
8 : clk_adc
None
9 : clk_rtc
None
10 : clk_ref
None
End of enumeration elements list.
KILL : Asynchronously kills the clock generator
bits : 10 - 10 (1 bit)
access : read-write
ENABLE : Starts and stops the clock generator cleanly
bits : 11 - 11 (1 bit)
access : read-write
DC50 : Enables duty cycle correction for odd divisors
bits : 12 - 12 (1 bit)
access : read-write
PHASE : This delays the enable signal by up to 3 cycles of the input clock
This must be set before the clock is enabled to have any effect
bits : 16 - 17 (2 bit)
access : read-write
NUDGE : An edge on this signal shifts the phase of the output by 1 cycle of the input clock
This can be done at any time
bits : 20 - 20 (1 bit)
access : read-write
Clock divisor, can be changed on-the-fly
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRAC : Fractional component of the divisor
bits : 0 - 7 (8 bit)
access : read-write
INT : Integer component of the divisor, 0 -> divide by 2^16
bits : 8 - 31 (24 bit)
access : read-write
Indicates which SRC is currently selected by the glitchless mux (one-hot).
This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Clock control, can be changed on-the-fly (except for auxsrc)
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRC : Selects the clock source glitchlessly, can be changed on-the-fly
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : rosc_clksrc_ph
None
1 : clksrc_clk_ref_aux
None
2 : xosc_clksrc
None
End of enumeration elements list.
AUXSRC : Selects the auxiliary clock source, will glitch when switching
bits : 5 - 6 (2 bit)
access : read-write
Enumeration:
0 : clksrc_pll_usb
None
1 : clksrc_gpin0
None
2 : clksrc_gpin1
None
End of enumeration elements list.
Clock divisor, can be changed on-the-fly
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT : Integer component of the divisor, 0 -> divide by 2^16
bits : 8 - 9 (2 bit)
access : read-write
Indicates which SRC is currently selected by the glitchless mux (one-hot).
The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s.
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Clock control, can be changed on-the-fly (except for auxsrc)
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRC : Selects the clock source glitchlessly, can be changed on-the-fly
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : clk_ref
None
1 : clksrc_clk_sys_aux
None
End of enumeration elements list.
AUXSRC : Selects the auxiliary clock source, will glitch when switching
bits : 5 - 7 (3 bit)
access : read-write
Enumeration:
0 : clksrc_pll_sys
None
1 : clksrc_pll_usb
None
2 : rosc_clksrc
None
3 : xosc_clksrc
None
4 : clksrc_gpin0
None
5 : clksrc_gpin1
None
End of enumeration elements list.
Clock divisor, can be changed on-the-fly
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRAC : Fractional component of the divisor
bits : 0 - 7 (8 bit)
access : read-write
INT : Integer component of the divisor, 0 -> divide by 2^16
bits : 8 - 31 (24 bit)
access : read-write
Clock divisor, can be changed on-the-fly
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRAC : Fractional component of the divisor
bits : 0 - 7 (8 bit)
access : read-write
INT : Integer component of the divisor, 0 -> divide by 2^16
bits : 8 - 31 (24 bit)
access : read-write
Indicates which SRC is currently selected by the glitchless mux (one-hot).
The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s.
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Clock control, can be changed on-the-fly (except for auxsrc)
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AUXSRC : Selects the auxiliary clock source, will glitch when switching
bits : 5 - 7 (3 bit)
access : read-write
Enumeration:
0 : clk_sys
None
1 : clksrc_pll_sys
None
2 : clksrc_pll_usb
None
3 : rosc_clksrc_ph
None
4 : xosc_clksrc
None
5 : clksrc_gpin0
None
6 : clksrc_gpin1
None
End of enumeration elements list.
KILL : Asynchronously kills the clock generator
bits : 10 - 10 (1 bit)
access : read-write
ENABLE : Starts and stops the clock generator cleanly
bits : 11 - 11 (1 bit)
access : read-write
Indicates which SRC is currently selected by the glitchless mux (one-hot).
This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Clock control, can be changed on-the-fly (except for auxsrc)
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AUXSRC : Selects the auxiliary clock source, will glitch when switching
bits : 5 - 7 (3 bit)
access : read-write
Enumeration:
0 : clksrc_pll_usb
None
1 : clksrc_pll_sys
None
2 : rosc_clksrc_ph
None
3 : xosc_clksrc
None
4 : clksrc_gpin0
None
5 : clksrc_gpin1
None
End of enumeration elements list.
KILL : Asynchronously kills the clock generator
bits : 10 - 10 (1 bit)
access : read-write
ENABLE : Starts and stops the clock generator cleanly
bits : 11 - 11 (1 bit)
access : read-write
PHASE : This delays the enable signal by up to 3 cycles of the input clock
This must be set before the clock is enabled to have any effect
bits : 16 - 17 (2 bit)
access : read-write
NUDGE : An edge on this signal shifts the phase of the output by 1 cycle of the input clock
This can be done at any time
bits : 20 - 20 (1 bit)
access : read-write
Clock divisor, can be changed on-the-fly
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT : Integer component of the divisor, 0 -> divide by 2^16
bits : 8 - 9 (2 bit)
access : read-write
Indicates which SRC is currently selected by the glitchless mux (one-hot).
This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Clock control, can be changed on-the-fly (except for auxsrc)
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AUXSRC : Selects the auxiliary clock source, will glitch when switching
bits : 5 - 7 (3 bit)
access : read-write
Enumeration:
0 : clksrc_pll_usb
None
1 : clksrc_pll_sys
None
2 : rosc_clksrc_ph
None
3 : xosc_clksrc
None
4 : clksrc_gpin0
None
5 : clksrc_gpin1
None
End of enumeration elements list.
KILL : Asynchronously kills the clock generator
bits : 10 - 10 (1 bit)
access : read-write
ENABLE : Starts and stops the clock generator cleanly
bits : 11 - 11 (1 bit)
access : read-write
PHASE : This delays the enable signal by up to 3 cycles of the input clock
This must be set before the clock is enabled to have any effect
bits : 16 - 17 (2 bit)
access : read-write
NUDGE : An edge on this signal shifts the phase of the output by 1 cycle of the input clock
This can be done at any time
bits : 20 - 20 (1 bit)
access : read-write
Clock divisor, can be changed on-the-fly
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT : Integer component of the divisor, 0 -> divide by 2^16
bits : 8 - 9 (2 bit)
access : read-write
Indicates which SRC is currently selected by the glitchless mux (one-hot).
This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Clock control, can be changed on-the-fly (except for auxsrc)
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AUXSRC : Selects the auxiliary clock source, will glitch when switching
bits : 5 - 7 (3 bit)
access : read-write
Enumeration:
0 : clksrc_pll_usb
None
1 : clksrc_pll_sys
None
2 : rosc_clksrc_ph
None
3 : xosc_clksrc
None
4 : clksrc_gpin0
None
5 : clksrc_gpin1
None
End of enumeration elements list.
KILL : Asynchronously kills the clock generator
bits : 10 - 10 (1 bit)
access : read-write
ENABLE : Starts and stops the clock generator cleanly
bits : 11 - 11 (1 bit)
access : read-write
PHASE : This delays the enable signal by up to 3 cycles of the input clock
This must be set before the clock is enabled to have any effect
bits : 16 - 17 (2 bit)
access : read-write
NUDGE : An edge on this signal shifts the phase of the output by 1 cycle of the input clock
This can be done at any time
bits : 20 - 20 (1 bit)
access : read-write
Clock divisor, can be changed on-the-fly
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRAC : Fractional component of the divisor
bits : 0 - 7 (8 bit)
access : read-write
INT : Integer component of the divisor, 0 -> divide by 2^16
bits : 8 - 31 (24 bit)
access : read-write
Indicates which SRC is currently selected by the glitchless mux (one-hot).
This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIMEOUT : This is expressed as a number of clk_ref cycles
and must be >= 2x clk_ref_freq/min_clk_tst_freq
bits : 0 - 7 (8 bit)
access : read-write
ENABLE : Enable resus
bits : 8 - 8 (1 bit)
access : read-write
FRCE : Force a resus, for test purposes only
bits : 12 - 12 (1 bit)
access : read-write
CLEAR : For clearing the resus after the fault that triggered it has been corrected
bits : 16 - 16 (1 bit)
access : read-write
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESUSSED : Clock has been resuscitated, correct the error then send ctrl_clear=1
bits : 0 - 0 (1 bit)
access : read-only
Indicates which SRC is currently selected by the glitchless mux (one-hot).
This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Reference clock frequency in kHz
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FC0_REF_KHZ :
bits : 0 - 19 (20 bit)
access : read-write
Minimum pass frequency in kHz. This is optional. Set to 0 if you are not using the pass/fail flags
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FC0_MIN_KHZ :
bits : 0 - 24 (25 bit)
access : read-write
Maximum pass frequency in kHz. This is optional. Set to 0x1ffffff if you are not using the pass/fail flags
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FC0_MAX_KHZ :
bits : 0 - 24 (25 bit)
access : read-write
Delays the start of frequency counting to allow the mux to settle
Delay is measured in multiples of the reference clock period
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FC0_DELAY :
bits : 0 - 2 (3 bit)
access : read-write
The test interval is 0.98us * 2**interval, but let's call it 1us * 2**interval
The default gives a test interval of 250us
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FC0_INTERVAL :
bits : 0 - 3 (4 bit)
access : read-write
Clock sent to frequency counter, set to 0 when not required
Writing to this register initiates the frequency count
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FC0_SRC :
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0 : NULL
None
1 : pll_sys_clksrc_primary
None
2 : pll_usb_clksrc_primary
None
3 : rosc_clksrc
None
4 : rosc_clksrc_ph
None
5 : xosc_clksrc
None
6 : clksrc_gpin0
None
7 : clksrc_gpin1
None
8 : clk_ref
None
9 : clk_sys
None
10 : clk_peri
None
11 : clk_usb
None
12 : clk_adc
None
13 : clk_rtc
None
End of enumeration elements list.
Frequency counter status
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PASS : Test passed
bits : 0 - 0 (1 bit)
access : read-only
DONE : Test complete
bits : 4 - 4 (1 bit)
access : read-only
RUNNING : Test running
bits : 8 - 8 (1 bit)
access : read-only
WAITING : Waiting for test clock to start
bits : 12 - 12 (1 bit)
access : read-only
FAIL : Test failed
bits : 16 - 16 (1 bit)
access : read-only
SLOW : Test clock slower than expected, only valid when status_done=1
bits : 20 - 20 (1 bit)
access : read-only
FAST : Test clock faster than expected, only valid when status_done=1
bits : 24 - 24 (1 bit)
access : read-only
DIED : Test clock stopped during test
bits : 28 - 28 (1 bit)
access : read-only
Result of frequency measurement, only valid when status_done=1
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRAC :
bits : 0 - 4 (5 bit)
access : read-only
KHZ :
bits : 5 - 29 (25 bit)
access : read-only
enable clock in wake mode
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
clk_sys_clocks :
bits : 0 - 0 (1 bit)
access : read-write
clk_adc_adc :
bits : 1 - 1 (1 bit)
access : read-write
clk_sys_adc :
bits : 2 - 2 (1 bit)
access : read-write
clk_sys_busctrl :
bits : 3 - 3 (1 bit)
access : read-write
clk_sys_busfabric :
bits : 4 - 4 (1 bit)
access : read-write
clk_sys_dma :
bits : 5 - 5 (1 bit)
access : read-write
clk_sys_i2c0 :
bits : 6 - 6 (1 bit)
access : read-write
clk_sys_i2c1 :
bits : 7 - 7 (1 bit)
access : read-write
clk_sys_io :
bits : 8 - 8 (1 bit)
access : read-write
clk_sys_jtag :
bits : 9 - 9 (1 bit)
access : read-write
clk_sys_vreg_and_chip_reset :
bits : 10 - 10 (1 bit)
access : read-write
clk_sys_pads :
bits : 11 - 11 (1 bit)
access : read-write
clk_sys_pio0 :
bits : 12 - 12 (1 bit)
access : read-write
clk_sys_pio1 :
bits : 13 - 13 (1 bit)
access : read-write
clk_sys_pll_sys :
bits : 14 - 14 (1 bit)
access : read-write
clk_sys_pll_usb :
bits : 15 - 15 (1 bit)
access : read-write
clk_sys_psm :
bits : 16 - 16 (1 bit)
access : read-write
clk_sys_pwm :
bits : 17 - 17 (1 bit)
access : read-write
clk_sys_resets :
bits : 18 - 18 (1 bit)
access : read-write
clk_sys_rom :
bits : 19 - 19 (1 bit)
access : read-write
clk_sys_rosc :
bits : 20 - 20 (1 bit)
access : read-write
clk_rtc_rtc :
bits : 21 - 21 (1 bit)
access : read-write
clk_sys_rtc :
bits : 22 - 22 (1 bit)
access : read-write
clk_sys_sio :
bits : 23 - 23 (1 bit)
access : read-write
clk_peri_spi0 :
bits : 24 - 24 (1 bit)
access : read-write
clk_sys_spi0 :
bits : 25 - 25 (1 bit)
access : read-write
clk_peri_spi1 :
bits : 26 - 26 (1 bit)
access : read-write
clk_sys_spi1 :
bits : 27 - 27 (1 bit)
access : read-write
clk_sys_sram0 :
bits : 28 - 28 (1 bit)
access : read-write
clk_sys_sram1 :
bits : 29 - 29 (1 bit)
access : read-write
clk_sys_sram2 :
bits : 30 - 30 (1 bit)
access : read-write
clk_sys_sram3 :
bits : 31 - 31 (1 bit)
access : read-write
enable clock in wake mode
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
clk_sys_sram4 :
bits : 0 - 0 (1 bit)
access : read-write
clk_sys_sram5 :
bits : 1 - 1 (1 bit)
access : read-write
clk_sys_syscfg :
bits : 2 - 2 (1 bit)
access : read-write
clk_sys_sysinfo :
bits : 3 - 3 (1 bit)
access : read-write
clk_sys_tbman :
bits : 4 - 4 (1 bit)
access : read-write
clk_sys_timer :
bits : 5 - 5 (1 bit)
access : read-write
clk_peri_uart0 :
bits : 6 - 6 (1 bit)
access : read-write
clk_sys_uart0 :
bits : 7 - 7 (1 bit)
access : read-write
clk_peri_uart1 :
bits : 8 - 8 (1 bit)
access : read-write
clk_sys_uart1 :
bits : 9 - 9 (1 bit)
access : read-write
clk_sys_usbctrl :
bits : 10 - 10 (1 bit)
access : read-write
clk_usb_usbctrl :
bits : 11 - 11 (1 bit)
access : read-write
clk_sys_watchdog :
bits : 12 - 12 (1 bit)
access : read-write
clk_sys_xip :
bits : 13 - 13 (1 bit)
access : read-write
clk_sys_xosc :
bits : 14 - 14 (1 bit)
access : read-write
enable clock in sleep mode
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
clk_sys_clocks :
bits : 0 - 0 (1 bit)
access : read-write
clk_adc_adc :
bits : 1 - 1 (1 bit)
access : read-write
clk_sys_adc :
bits : 2 - 2 (1 bit)
access : read-write
clk_sys_busctrl :
bits : 3 - 3 (1 bit)
access : read-write
clk_sys_busfabric :
bits : 4 - 4 (1 bit)
access : read-write
clk_sys_dma :
bits : 5 - 5 (1 bit)
access : read-write
clk_sys_i2c0 :
bits : 6 - 6 (1 bit)
access : read-write
clk_sys_i2c1 :
bits : 7 - 7 (1 bit)
access : read-write
clk_sys_io :
bits : 8 - 8 (1 bit)
access : read-write
clk_sys_jtag :
bits : 9 - 9 (1 bit)
access : read-write
clk_sys_vreg_and_chip_reset :
bits : 10 - 10 (1 bit)
access : read-write
clk_sys_pads :
bits : 11 - 11 (1 bit)
access : read-write
clk_sys_pio0 :
bits : 12 - 12 (1 bit)
access : read-write
clk_sys_pio1 :
bits : 13 - 13 (1 bit)
access : read-write
clk_sys_pll_sys :
bits : 14 - 14 (1 bit)
access : read-write
clk_sys_pll_usb :
bits : 15 - 15 (1 bit)
access : read-write
clk_sys_psm :
bits : 16 - 16 (1 bit)
access : read-write
clk_sys_pwm :
bits : 17 - 17 (1 bit)
access : read-write
clk_sys_resets :
bits : 18 - 18 (1 bit)
access : read-write
clk_sys_rom :
bits : 19 - 19 (1 bit)
access : read-write
clk_sys_rosc :
bits : 20 - 20 (1 bit)
access : read-write
clk_rtc_rtc :
bits : 21 - 21 (1 bit)
access : read-write
clk_sys_rtc :
bits : 22 - 22 (1 bit)
access : read-write
clk_sys_sio :
bits : 23 - 23 (1 bit)
access : read-write
clk_peri_spi0 :
bits : 24 - 24 (1 bit)
access : read-write
clk_sys_spi0 :
bits : 25 - 25 (1 bit)
access : read-write
clk_peri_spi1 :
bits : 26 - 26 (1 bit)
access : read-write
clk_sys_spi1 :
bits : 27 - 27 (1 bit)
access : read-write
clk_sys_sram0 :
bits : 28 - 28 (1 bit)
access : read-write
clk_sys_sram1 :
bits : 29 - 29 (1 bit)
access : read-write
clk_sys_sram2 :
bits : 30 - 30 (1 bit)
access : read-write
clk_sys_sram3 :
bits : 31 - 31 (1 bit)
access : read-write
enable clock in sleep mode
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
clk_sys_sram4 :
bits : 0 - 0 (1 bit)
access : read-write
clk_sys_sram5 :
bits : 1 - 1 (1 bit)
access : read-write
clk_sys_syscfg :
bits : 2 - 2 (1 bit)
access : read-write
clk_sys_sysinfo :
bits : 3 - 3 (1 bit)
access : read-write
clk_sys_tbman :
bits : 4 - 4 (1 bit)
access : read-write
clk_sys_timer :
bits : 5 - 5 (1 bit)
access : read-write
clk_peri_uart0 :
bits : 6 - 6 (1 bit)
access : read-write
clk_sys_uart0 :
bits : 7 - 7 (1 bit)
access : read-write
clk_peri_uart1 :
bits : 8 - 8 (1 bit)
access : read-write
clk_sys_uart1 :
bits : 9 - 9 (1 bit)
access : read-write
clk_sys_usbctrl :
bits : 10 - 10 (1 bit)
access : read-write
clk_usb_usbctrl :
bits : 11 - 11 (1 bit)
access : read-write
clk_sys_watchdog :
bits : 12 - 12 (1 bit)
access : read-write
clk_sys_xip :
bits : 13 - 13 (1 bit)
access : read-write
clk_sys_xosc :
bits : 14 - 14 (1 bit)
access : read-write
indicates the state of the clock enable
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
clk_sys_clocks :
bits : 0 - 0 (1 bit)
access : read-only
clk_adc_adc :
bits : 1 - 1 (1 bit)
access : read-only
clk_sys_adc :
bits : 2 - 2 (1 bit)
access : read-only
clk_sys_busctrl :
bits : 3 - 3 (1 bit)
access : read-only
clk_sys_busfabric :
bits : 4 - 4 (1 bit)
access : read-only
clk_sys_dma :
bits : 5 - 5 (1 bit)
access : read-only
clk_sys_i2c0 :
bits : 6 - 6 (1 bit)
access : read-only
clk_sys_i2c1 :
bits : 7 - 7 (1 bit)
access : read-only
clk_sys_io :
bits : 8 - 8 (1 bit)
access : read-only
clk_sys_jtag :
bits : 9 - 9 (1 bit)
access : read-only
clk_sys_vreg_and_chip_reset :
bits : 10 - 10 (1 bit)
access : read-only
clk_sys_pads :
bits : 11 - 11 (1 bit)
access : read-only
clk_sys_pio0 :
bits : 12 - 12 (1 bit)
access : read-only
clk_sys_pio1 :
bits : 13 - 13 (1 bit)
access : read-only
clk_sys_pll_sys :
bits : 14 - 14 (1 bit)
access : read-only
clk_sys_pll_usb :
bits : 15 - 15 (1 bit)
access : read-only
clk_sys_psm :
bits : 16 - 16 (1 bit)
access : read-only
clk_sys_pwm :
bits : 17 - 17 (1 bit)
access : read-only
clk_sys_resets :
bits : 18 - 18 (1 bit)
access : read-only
clk_sys_rom :
bits : 19 - 19 (1 bit)
access : read-only
clk_sys_rosc :
bits : 20 - 20 (1 bit)
access : read-only
clk_rtc_rtc :
bits : 21 - 21 (1 bit)
access : read-only
clk_sys_rtc :
bits : 22 - 22 (1 bit)
access : read-only
clk_sys_sio :
bits : 23 - 23 (1 bit)
access : read-only
clk_peri_spi0 :
bits : 24 - 24 (1 bit)
access : read-only
clk_sys_spi0 :
bits : 25 - 25 (1 bit)
access : read-only
clk_peri_spi1 :
bits : 26 - 26 (1 bit)
access : read-only
clk_sys_spi1 :
bits : 27 - 27 (1 bit)
access : read-only
clk_sys_sram0 :
bits : 28 - 28 (1 bit)
access : read-only
clk_sys_sram1 :
bits : 29 - 29 (1 bit)
access : read-only
clk_sys_sram2 :
bits : 30 - 30 (1 bit)
access : read-only
clk_sys_sram3 :
bits : 31 - 31 (1 bit)
access : read-only
indicates the state of the clock enable
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
clk_sys_sram4 :
bits : 0 - 0 (1 bit)
access : read-only
clk_sys_sram5 :
bits : 1 - 1 (1 bit)
access : read-only
clk_sys_syscfg :
bits : 2 - 2 (1 bit)
access : read-only
clk_sys_sysinfo :
bits : 3 - 3 (1 bit)
access : read-only
clk_sys_tbman :
bits : 4 - 4 (1 bit)
access : read-only
clk_sys_timer :
bits : 5 - 5 (1 bit)
access : read-only
clk_peri_uart0 :
bits : 6 - 6 (1 bit)
access : read-only
clk_sys_uart0 :
bits : 7 - 7 (1 bit)
access : read-only
clk_peri_uart1 :
bits : 8 - 8 (1 bit)
access : read-only
clk_sys_uart1 :
bits : 9 - 9 (1 bit)
access : read-only
clk_sys_usbctrl :
bits : 10 - 10 (1 bit)
access : read-only
clk_usb_usbctrl :
bits : 11 - 11 (1 bit)
access : read-only
clk_sys_watchdog :
bits : 12 - 12 (1 bit)
access : read-only
clk_sys_xip :
bits : 13 - 13 (1 bit)
access : read-only
clk_sys_xosc :
bits : 14 - 14 (1 bit)
access : read-only
Raw Interrupts
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLK_SYS_RESUS :
bits : 0 - 0 (1 bit)
access : read-only
Interrupt Enable
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLK_SYS_RESUS :
bits : 0 - 0 (1 bit)
access : read-write
Clock control, can be changed on-the-fly (except for auxsrc)
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AUXSRC : Selects the auxiliary clock source, will glitch when switching
bits : 5 - 8 (4 bit)
access : read-write
Enumeration:
0 : clksrc_pll_sys
None
1 : clksrc_gpin0
None
2 : clksrc_gpin1
None
3 : clksrc_pll_usb
None
4 : rosc_clksrc
None
5 : xosc_clksrc
None
6 : clk_sys
None
7 : clk_usb
None
8 : clk_adc
None
9 : clk_rtc
None
10 : clk_ref
None
End of enumeration elements list.
KILL : Asynchronously kills the clock generator
bits : 10 - 10 (1 bit)
access : read-write
ENABLE : Starts and stops the clock generator cleanly
bits : 11 - 11 (1 bit)
access : read-write
DC50 : Enables duty cycle correction for odd divisors
bits : 12 - 12 (1 bit)
access : read-write
PHASE : This delays the enable signal by up to 3 cycles of the input clock
This must be set before the clock is enabled to have any effect
bits : 16 - 17 (2 bit)
access : read-write
NUDGE : An edge on this signal shifts the phase of the output by 1 cycle of the input clock
This can be done at any time
bits : 20 - 20 (1 bit)
access : read-write
Interrupt Force
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLK_SYS_RESUS :
bits : 0 - 0 (1 bit)
access : read-write
Interrupt status after masking & forcing
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLK_SYS_RESUS :
bits : 0 - 0 (1 bit)
access : read-only
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