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PSM

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

FRCE_ON

FRCE_OFF

WDSEL

DONE


FRCE_ON

Force block out of reset (i.e. power it on)
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FRCE_ON FRCE_ON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rosc xosc clocks resets busfabric rom sram0 sram1 sram2 sram3 sram4 sram5 xip vreg_and_chip_reset sio proc0 proc1

rosc :
bits : 0 - 0 (1 bit)
access : read-write

xosc :
bits : 1 - 1 (1 bit)
access : read-write

clocks :
bits : 2 - 2 (1 bit)
access : read-write

resets :
bits : 3 - 3 (1 bit)
access : read-write

busfabric :
bits : 4 - 4 (1 bit)
access : read-write

rom :
bits : 5 - 5 (1 bit)
access : read-write

sram0 :
bits : 6 - 6 (1 bit)
access : read-write

sram1 :
bits : 7 - 7 (1 bit)
access : read-write

sram2 :
bits : 8 - 8 (1 bit)
access : read-write

sram3 :
bits : 9 - 9 (1 bit)
access : read-write

sram4 :
bits : 10 - 10 (1 bit)
access : read-write

sram5 :
bits : 11 - 11 (1 bit)
access : read-write

xip :
bits : 12 - 12 (1 bit)
access : read-write

vreg_and_chip_reset :
bits : 13 - 13 (1 bit)
access : read-write

sio :
bits : 14 - 14 (1 bit)
access : read-write

proc0 :
bits : 15 - 15 (1 bit)
access : read-write

proc1 :
bits : 16 - 16 (1 bit)
access : read-write


FRCE_OFF

Force into reset (i.e. power it off)
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FRCE_OFF FRCE_OFF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rosc xosc clocks resets busfabric rom sram0 sram1 sram2 sram3 sram4 sram5 xip vreg_and_chip_reset sio proc0 proc1

rosc :
bits : 0 - 0 (1 bit)
access : read-write

xosc :
bits : 1 - 1 (1 bit)
access : read-write

clocks :
bits : 2 - 2 (1 bit)
access : read-write

resets :
bits : 3 - 3 (1 bit)
access : read-write

busfabric :
bits : 4 - 4 (1 bit)
access : read-write

rom :
bits : 5 - 5 (1 bit)
access : read-write

sram0 :
bits : 6 - 6 (1 bit)
access : read-write

sram1 :
bits : 7 - 7 (1 bit)
access : read-write

sram2 :
bits : 8 - 8 (1 bit)
access : read-write

sram3 :
bits : 9 - 9 (1 bit)
access : read-write

sram4 :
bits : 10 - 10 (1 bit)
access : read-write

sram5 :
bits : 11 - 11 (1 bit)
access : read-write

xip :
bits : 12 - 12 (1 bit)
access : read-write

vreg_and_chip_reset :
bits : 13 - 13 (1 bit)
access : read-write

sio :
bits : 14 - 14 (1 bit)
access : read-write

proc0 :
bits : 15 - 15 (1 bit)
access : read-write

proc1 :
bits : 16 - 16 (1 bit)
access : read-write


WDSEL

Set to 1 if this peripheral should be reset when the watchdog fires.
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WDSEL WDSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rosc xosc clocks resets busfabric rom sram0 sram1 sram2 sram3 sram4 sram5 xip vreg_and_chip_reset sio proc0 proc1

rosc :
bits : 0 - 0 (1 bit)
access : read-write

xosc :
bits : 1 - 1 (1 bit)
access : read-write

clocks :
bits : 2 - 2 (1 bit)
access : read-write

resets :
bits : 3 - 3 (1 bit)
access : read-write

busfabric :
bits : 4 - 4 (1 bit)
access : read-write

rom :
bits : 5 - 5 (1 bit)
access : read-write

sram0 :
bits : 6 - 6 (1 bit)
access : read-write

sram1 :
bits : 7 - 7 (1 bit)
access : read-write

sram2 :
bits : 8 - 8 (1 bit)
access : read-write

sram3 :
bits : 9 - 9 (1 bit)
access : read-write

sram4 :
bits : 10 - 10 (1 bit)
access : read-write

sram5 :
bits : 11 - 11 (1 bit)
access : read-write

xip :
bits : 12 - 12 (1 bit)
access : read-write

vreg_and_chip_reset :
bits : 13 - 13 (1 bit)
access : read-write

sio :
bits : 14 - 14 (1 bit)
access : read-write

proc0 :
bits : 15 - 15 (1 bit)
access : read-write

proc1 :
bits : 16 - 16 (1 bit)
access : read-write


DONE

Indicates the peripheral's registers are ready to access.
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DONE DONE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rosc xosc clocks resets busfabric rom sram0 sram1 sram2 sram3 sram4 sram5 xip vreg_and_chip_reset sio proc0 proc1

rosc :
bits : 0 - 0 (1 bit)
access : read-only

xosc :
bits : 1 - 1 (1 bit)
access : read-only

clocks :
bits : 2 - 2 (1 bit)
access : read-only

resets :
bits : 3 - 3 (1 bit)
access : read-only

busfabric :
bits : 4 - 4 (1 bit)
access : read-only

rom :
bits : 5 - 5 (1 bit)
access : read-only

sram0 :
bits : 6 - 6 (1 bit)
access : read-only

sram1 :
bits : 7 - 7 (1 bit)
access : read-only

sram2 :
bits : 8 - 8 (1 bit)
access : read-only

sram3 :
bits : 9 - 9 (1 bit)
access : read-only

sram4 :
bits : 10 - 10 (1 bit)
access : read-only

sram5 :
bits : 11 - 11 (1 bit)
access : read-only

xip :
bits : 12 - 12 (1 bit)
access : read-only

vreg_and_chip_reset :
bits : 13 - 13 (1 bit)
access : read-only

sio :
bits : 14 - 14 (1 bit)
access : read-only

proc0 :
bits : 15 - 15 (1 bit)
access : read-only

proc1 :
bits : 16 - 16 (1 bit)
access : read-only



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