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IO_QSPI

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

GPIO_QSPI_SCLK_STATUS

GPIO_QSPI_SD0_STATUS

GPIO_QSPI_SD0_CTRL

GPIO_QSPI_SD1_STATUS

GPIO_QSPI_SD1_CTRL

GPIO_QSPI_SD2_STATUS

GPIO_QSPI_SD2_CTRL

GPIO_QSPI_SD3_STATUS

GPIO_QSPI_SD3_CTRL

INTR

PROC0_INTE

PROC0_INTF

PROC0_INTS

GPIO_QSPI_SCLK_CTRL

PROC1_INTE

PROC1_INTF

PROC1_INTS

DORMANT_WAKE_INTE

DORMANT_WAKE_INTF

DORMANT_WAKE_INTS

GPIO_QSPI_SS_STATUS

GPIO_QSPI_SS_CTRL


GPIO_QSPI_SCLK_STATUS

GPIO status
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO_QSPI_SCLK_STATUS GPIO_QSPI_SCLK_STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUTFROMPERI OUTTOPAD OEFROMPERI OETOPAD INFROMPAD INTOPERI IRQFROMPAD IRQTOPROC

OUTFROMPERI : output signal from selected peripheral, before register override is applied
bits : 8 - 8 (1 bit)
access : read-only

OUTTOPAD : output signal to pad after register override is applied
bits : 9 - 9 (1 bit)
access : read-only

OEFROMPERI : output enable from selected peripheral, before register override is applied
bits : 12 - 12 (1 bit)
access : read-only

OETOPAD : output enable to pad after register override is applied
bits : 13 - 13 (1 bit)
access : read-only

INFROMPAD : input signal from pad, before override is applied
bits : 17 - 17 (1 bit)
access : read-only

INTOPERI : input signal to peripheral, after override is applied
bits : 19 - 19 (1 bit)
access : read-only

IRQFROMPAD : interrupt from pad before override is applied
bits : 24 - 24 (1 bit)
access : read-only

IRQTOPROC : interrupt to processors, after override is applied
bits : 26 - 26 (1 bit)
access : read-only


GPIO_QSPI_SD0_STATUS

GPIO status
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO_QSPI_SD0_STATUS GPIO_QSPI_SD0_STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUTFROMPERI OUTTOPAD OEFROMPERI OETOPAD INFROMPAD INTOPERI IRQFROMPAD IRQTOPROC

OUTFROMPERI : output signal from selected peripheral, before register override is applied
bits : 8 - 8 (1 bit)
access : read-only

OUTTOPAD : output signal to pad after register override is applied
bits : 9 - 9 (1 bit)
access : read-only

OEFROMPERI : output enable from selected peripheral, before register override is applied
bits : 12 - 12 (1 bit)
access : read-only

OETOPAD : output enable to pad after register override is applied
bits : 13 - 13 (1 bit)
access : read-only

INFROMPAD : input signal from pad, before override is applied
bits : 17 - 17 (1 bit)
access : read-only

INTOPERI : input signal to peripheral, after override is applied
bits : 19 - 19 (1 bit)
access : read-only

IRQFROMPAD : interrupt from pad before override is applied
bits : 24 - 24 (1 bit)
access : read-only

IRQTOPROC : interrupt to processors, after override is applied
bits : 26 - 26 (1 bit)
access : read-only


GPIO_QSPI_SD0_CTRL

GPIO control including function select and overrides.
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO_QSPI_SD0_CTRL GPIO_QSPI_SD0_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FUNCSEL OUTOVER OEOVER INOVER IRQOVER

FUNCSEL : 0-31 -> selects pin function according to the gpio table 31 == NULL
bits : 0 - 4 (5 bit)
access : read-write

Enumeration:

0 : xip_sd0

None

5 : sio_32

None

31 : null

None

End of enumeration elements list.

OUTOVER :
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : NORMAL

drive output from peripheral signal selected by funcsel

1 : INVERT

drive output from inverse of peripheral signal selected by funcsel

2 : LOW

drive output low

3 : HIGH

drive output high

End of enumeration elements list.

OEOVER :
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : NORMAL

drive output enable from peripheral signal selected by funcsel

1 : INVERT

drive output enable from inverse of peripheral signal selected by funcsel

2 : DISABLE

disable output

3 : ENABLE

enable output

End of enumeration elements list.

INOVER :
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0 : NORMAL

don't invert the peri input

1 : INVERT

invert the peri input

2 : LOW

drive peri input low

3 : HIGH

drive peri input high

End of enumeration elements list.

IRQOVER :
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

0 : NORMAL

don't invert the interrupt

1 : INVERT

invert the interrupt

2 : LOW

drive interrupt low

3 : HIGH

drive interrupt high

End of enumeration elements list.


GPIO_QSPI_SD1_STATUS

GPIO status
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO_QSPI_SD1_STATUS GPIO_QSPI_SD1_STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUTFROMPERI OUTTOPAD OEFROMPERI OETOPAD INFROMPAD INTOPERI IRQFROMPAD IRQTOPROC

OUTFROMPERI : output signal from selected peripheral, before register override is applied
bits : 8 - 8 (1 bit)
access : read-only

OUTTOPAD : output signal to pad after register override is applied
bits : 9 - 9 (1 bit)
access : read-only

OEFROMPERI : output enable from selected peripheral, before register override is applied
bits : 12 - 12 (1 bit)
access : read-only

OETOPAD : output enable to pad after register override is applied
bits : 13 - 13 (1 bit)
access : read-only

INFROMPAD : input signal from pad, before override is applied
bits : 17 - 17 (1 bit)
access : read-only

INTOPERI : input signal to peripheral, after override is applied
bits : 19 - 19 (1 bit)
access : read-only

IRQFROMPAD : interrupt from pad before override is applied
bits : 24 - 24 (1 bit)
access : read-only

IRQTOPROC : interrupt to processors, after override is applied
bits : 26 - 26 (1 bit)
access : read-only


GPIO_QSPI_SD1_CTRL

GPIO control including function select and overrides.
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO_QSPI_SD1_CTRL GPIO_QSPI_SD1_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FUNCSEL OUTOVER OEOVER INOVER IRQOVER

FUNCSEL : 0-31 -> selects pin function according to the gpio table 31 == NULL
bits : 0 - 4 (5 bit)
access : read-write

Enumeration:

0 : xip_sd1

None

5 : sio_33

None

31 : null

None

End of enumeration elements list.

OUTOVER :
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : NORMAL

drive output from peripheral signal selected by funcsel

1 : INVERT

drive output from inverse of peripheral signal selected by funcsel

2 : LOW

drive output low

3 : HIGH

drive output high

End of enumeration elements list.

OEOVER :
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : NORMAL

drive output enable from peripheral signal selected by funcsel

1 : INVERT

drive output enable from inverse of peripheral signal selected by funcsel

2 : DISABLE

disable output

3 : ENABLE

enable output

End of enumeration elements list.

INOVER :
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0 : NORMAL

don't invert the peri input

1 : INVERT

invert the peri input

2 : LOW

drive peri input low

3 : HIGH

drive peri input high

End of enumeration elements list.

IRQOVER :
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

0 : NORMAL

don't invert the interrupt

1 : INVERT

invert the interrupt

2 : LOW

drive interrupt low

3 : HIGH

drive interrupt high

End of enumeration elements list.


GPIO_QSPI_SD2_STATUS

GPIO status
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO_QSPI_SD2_STATUS GPIO_QSPI_SD2_STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUTFROMPERI OUTTOPAD OEFROMPERI OETOPAD INFROMPAD INTOPERI IRQFROMPAD IRQTOPROC

OUTFROMPERI : output signal from selected peripheral, before register override is applied
bits : 8 - 8 (1 bit)
access : read-only

OUTTOPAD : output signal to pad after register override is applied
bits : 9 - 9 (1 bit)
access : read-only

OEFROMPERI : output enable from selected peripheral, before register override is applied
bits : 12 - 12 (1 bit)
access : read-only

OETOPAD : output enable to pad after register override is applied
bits : 13 - 13 (1 bit)
access : read-only

INFROMPAD : input signal from pad, before override is applied
bits : 17 - 17 (1 bit)
access : read-only

INTOPERI : input signal to peripheral, after override is applied
bits : 19 - 19 (1 bit)
access : read-only

IRQFROMPAD : interrupt from pad before override is applied
bits : 24 - 24 (1 bit)
access : read-only

IRQTOPROC : interrupt to processors, after override is applied
bits : 26 - 26 (1 bit)
access : read-only


GPIO_QSPI_SD2_CTRL

GPIO control including function select and overrides.
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO_QSPI_SD2_CTRL GPIO_QSPI_SD2_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FUNCSEL OUTOVER OEOVER INOVER IRQOVER

FUNCSEL : 0-31 -> selects pin function according to the gpio table 31 == NULL
bits : 0 - 4 (5 bit)
access : read-write

Enumeration:

0 : xip_sd2

None

5 : sio_34

None

31 : null

None

End of enumeration elements list.

OUTOVER :
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : NORMAL

drive output from peripheral signal selected by funcsel

1 : INVERT

drive output from inverse of peripheral signal selected by funcsel

2 : LOW

drive output low

3 : HIGH

drive output high

End of enumeration elements list.

OEOVER :
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : NORMAL

drive output enable from peripheral signal selected by funcsel

1 : INVERT

drive output enable from inverse of peripheral signal selected by funcsel

2 : DISABLE

disable output

3 : ENABLE

enable output

End of enumeration elements list.

INOVER :
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0 : NORMAL

don't invert the peri input

1 : INVERT

invert the peri input

2 : LOW

drive peri input low

3 : HIGH

drive peri input high

End of enumeration elements list.

IRQOVER :
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

0 : NORMAL

don't invert the interrupt

1 : INVERT

invert the interrupt

2 : LOW

drive interrupt low

3 : HIGH

drive interrupt high

End of enumeration elements list.


GPIO_QSPI_SD3_STATUS

GPIO status
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO_QSPI_SD3_STATUS GPIO_QSPI_SD3_STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUTFROMPERI OUTTOPAD OEFROMPERI OETOPAD INFROMPAD INTOPERI IRQFROMPAD IRQTOPROC

OUTFROMPERI : output signal from selected peripheral, before register override is applied
bits : 8 - 8 (1 bit)
access : read-only

OUTTOPAD : output signal to pad after register override is applied
bits : 9 - 9 (1 bit)
access : read-only

OEFROMPERI : output enable from selected peripheral, before register override is applied
bits : 12 - 12 (1 bit)
access : read-only

OETOPAD : output enable to pad after register override is applied
bits : 13 - 13 (1 bit)
access : read-only

INFROMPAD : input signal from pad, before override is applied
bits : 17 - 17 (1 bit)
access : read-only

INTOPERI : input signal to peripheral, after override is applied
bits : 19 - 19 (1 bit)
access : read-only

IRQFROMPAD : interrupt from pad before override is applied
bits : 24 - 24 (1 bit)
access : read-only

IRQTOPROC : interrupt to processors, after override is applied
bits : 26 - 26 (1 bit)
access : read-only


GPIO_QSPI_SD3_CTRL

GPIO control including function select and overrides.
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO_QSPI_SD3_CTRL GPIO_QSPI_SD3_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FUNCSEL OUTOVER OEOVER INOVER IRQOVER

FUNCSEL : 0-31 -> selects pin function according to the gpio table 31 == NULL
bits : 0 - 4 (5 bit)
access : read-write

Enumeration:

0 : xip_sd3

None

5 : sio_35

None

31 : null

None

End of enumeration elements list.

OUTOVER :
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : NORMAL

drive output from peripheral signal selected by funcsel

1 : INVERT

drive output from inverse of peripheral signal selected by funcsel

2 : LOW

drive output low

3 : HIGH

drive output high

End of enumeration elements list.

OEOVER :
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : NORMAL

drive output enable from peripheral signal selected by funcsel

1 : INVERT

drive output enable from inverse of peripheral signal selected by funcsel

2 : DISABLE

disable output

3 : ENABLE

enable output

End of enumeration elements list.

INOVER :
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0 : NORMAL

don't invert the peri input

1 : INVERT

invert the peri input

2 : LOW

drive peri input low

3 : HIGH

drive peri input high

End of enumeration elements list.

IRQOVER :
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

0 : NORMAL

don't invert the interrupt

1 : INVERT

invert the interrupt

2 : LOW

drive interrupt low

3 : HIGH

drive interrupt high

End of enumeration elements list.


INTR

Raw Interrupts
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTR INTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIO_QSPI_SCLK_LEVEL_LOW GPIO_QSPI_SCLK_LEVEL_HIGH GPIO_QSPI_SCLK_EDGE_LOW GPIO_QSPI_SCLK_EDGE_HIGH GPIO_QSPI_SS_LEVEL_LOW GPIO_QSPI_SS_LEVEL_HIGH GPIO_QSPI_SS_EDGE_LOW GPIO_QSPI_SS_EDGE_HIGH GPIO_QSPI_SD0_LEVEL_LOW GPIO_QSPI_SD0_LEVEL_HIGH GPIO_QSPI_SD0_EDGE_LOW GPIO_QSPI_SD0_EDGE_HIGH GPIO_QSPI_SD1_LEVEL_LOW GPIO_QSPI_SD1_LEVEL_HIGH GPIO_QSPI_SD1_EDGE_LOW GPIO_QSPI_SD1_EDGE_HIGH GPIO_QSPI_SD2_LEVEL_LOW GPIO_QSPI_SD2_LEVEL_HIGH GPIO_QSPI_SD2_EDGE_LOW GPIO_QSPI_SD2_EDGE_HIGH GPIO_QSPI_SD3_LEVEL_LOW GPIO_QSPI_SD3_LEVEL_HIGH GPIO_QSPI_SD3_EDGE_LOW GPIO_QSPI_SD3_EDGE_HIGH

GPIO_QSPI_SCLK_LEVEL_LOW :
bits : 0 - 0 (1 bit)
access : read-only

GPIO_QSPI_SCLK_LEVEL_HIGH :
bits : 1 - 1 (1 bit)
access : read-only

GPIO_QSPI_SCLK_EDGE_LOW :
bits : 2 - 2 (1 bit)
access : read-write

GPIO_QSPI_SCLK_EDGE_HIGH :
bits : 3 - 3 (1 bit)
access : read-write

GPIO_QSPI_SS_LEVEL_LOW :
bits : 4 - 4 (1 bit)
access : read-only

GPIO_QSPI_SS_LEVEL_HIGH :
bits : 5 - 5 (1 bit)
access : read-only

GPIO_QSPI_SS_EDGE_LOW :
bits : 6 - 6 (1 bit)
access : read-write

GPIO_QSPI_SS_EDGE_HIGH :
bits : 7 - 7 (1 bit)
access : read-write

GPIO_QSPI_SD0_LEVEL_LOW :
bits : 8 - 8 (1 bit)
access : read-only

GPIO_QSPI_SD0_LEVEL_HIGH :
bits : 9 - 9 (1 bit)
access : read-only

GPIO_QSPI_SD0_EDGE_LOW :
bits : 10 - 10 (1 bit)
access : read-write

GPIO_QSPI_SD0_EDGE_HIGH :
bits : 11 - 11 (1 bit)
access : read-write

GPIO_QSPI_SD1_LEVEL_LOW :
bits : 12 - 12 (1 bit)
access : read-only

GPIO_QSPI_SD1_LEVEL_HIGH :
bits : 13 - 13 (1 bit)
access : read-only

GPIO_QSPI_SD1_EDGE_LOW :
bits : 14 - 14 (1 bit)
access : read-write

GPIO_QSPI_SD1_EDGE_HIGH :
bits : 15 - 15 (1 bit)
access : read-write

GPIO_QSPI_SD2_LEVEL_LOW :
bits : 16 - 16 (1 bit)
access : read-only

GPIO_QSPI_SD2_LEVEL_HIGH :
bits : 17 - 17 (1 bit)
access : read-only

GPIO_QSPI_SD2_EDGE_LOW :
bits : 18 - 18 (1 bit)
access : read-write

GPIO_QSPI_SD2_EDGE_HIGH :
bits : 19 - 19 (1 bit)
access : read-write

GPIO_QSPI_SD3_LEVEL_LOW :
bits : 20 - 20 (1 bit)
access : read-only

GPIO_QSPI_SD3_LEVEL_HIGH :
bits : 21 - 21 (1 bit)
access : read-only

GPIO_QSPI_SD3_EDGE_LOW :
bits : 22 - 22 (1 bit)
access : read-write

GPIO_QSPI_SD3_EDGE_HIGH :
bits : 23 - 23 (1 bit)
access : read-write


PROC0_INTE

Interrupt Enable for proc0
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PROC0_INTE PROC0_INTE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIO_QSPI_SCLK_LEVEL_LOW GPIO_QSPI_SCLK_LEVEL_HIGH GPIO_QSPI_SCLK_EDGE_LOW GPIO_QSPI_SCLK_EDGE_HIGH GPIO_QSPI_SS_LEVEL_LOW GPIO_QSPI_SS_LEVEL_HIGH GPIO_QSPI_SS_EDGE_LOW GPIO_QSPI_SS_EDGE_HIGH GPIO_QSPI_SD0_LEVEL_LOW GPIO_QSPI_SD0_LEVEL_HIGH GPIO_QSPI_SD0_EDGE_LOW GPIO_QSPI_SD0_EDGE_HIGH GPIO_QSPI_SD1_LEVEL_LOW GPIO_QSPI_SD1_LEVEL_HIGH GPIO_QSPI_SD1_EDGE_LOW GPIO_QSPI_SD1_EDGE_HIGH GPIO_QSPI_SD2_LEVEL_LOW GPIO_QSPI_SD2_LEVEL_HIGH GPIO_QSPI_SD2_EDGE_LOW GPIO_QSPI_SD2_EDGE_HIGH GPIO_QSPI_SD3_LEVEL_LOW GPIO_QSPI_SD3_LEVEL_HIGH GPIO_QSPI_SD3_EDGE_LOW GPIO_QSPI_SD3_EDGE_HIGH

GPIO_QSPI_SCLK_LEVEL_LOW :
bits : 0 - 0 (1 bit)
access : read-write

GPIO_QSPI_SCLK_LEVEL_HIGH :
bits : 1 - 1 (1 bit)
access : read-write

GPIO_QSPI_SCLK_EDGE_LOW :
bits : 2 - 2 (1 bit)
access : read-write

GPIO_QSPI_SCLK_EDGE_HIGH :
bits : 3 - 3 (1 bit)
access : read-write

GPIO_QSPI_SS_LEVEL_LOW :
bits : 4 - 4 (1 bit)
access : read-write

GPIO_QSPI_SS_LEVEL_HIGH :
bits : 5 - 5 (1 bit)
access : read-write

GPIO_QSPI_SS_EDGE_LOW :
bits : 6 - 6 (1 bit)
access : read-write

GPIO_QSPI_SS_EDGE_HIGH :
bits : 7 - 7 (1 bit)
access : read-write

GPIO_QSPI_SD0_LEVEL_LOW :
bits : 8 - 8 (1 bit)
access : read-write

GPIO_QSPI_SD0_LEVEL_HIGH :
bits : 9 - 9 (1 bit)
access : read-write

GPIO_QSPI_SD0_EDGE_LOW :
bits : 10 - 10 (1 bit)
access : read-write

GPIO_QSPI_SD0_EDGE_HIGH :
bits : 11 - 11 (1 bit)
access : read-write

GPIO_QSPI_SD1_LEVEL_LOW :
bits : 12 - 12 (1 bit)
access : read-write

GPIO_QSPI_SD1_LEVEL_HIGH :
bits : 13 - 13 (1 bit)
access : read-write

GPIO_QSPI_SD1_EDGE_LOW :
bits : 14 - 14 (1 bit)
access : read-write

GPIO_QSPI_SD1_EDGE_HIGH :
bits : 15 - 15 (1 bit)
access : read-write

GPIO_QSPI_SD2_LEVEL_LOW :
bits : 16 - 16 (1 bit)
access : read-write

GPIO_QSPI_SD2_LEVEL_HIGH :
bits : 17 - 17 (1 bit)
access : read-write

GPIO_QSPI_SD2_EDGE_LOW :
bits : 18 - 18 (1 bit)
access : read-write

GPIO_QSPI_SD2_EDGE_HIGH :
bits : 19 - 19 (1 bit)
access : read-write

GPIO_QSPI_SD3_LEVEL_LOW :
bits : 20 - 20 (1 bit)
access : read-write

GPIO_QSPI_SD3_LEVEL_HIGH :
bits : 21 - 21 (1 bit)
access : read-write

GPIO_QSPI_SD3_EDGE_LOW :
bits : 22 - 22 (1 bit)
access : read-write

GPIO_QSPI_SD3_EDGE_HIGH :
bits : 23 - 23 (1 bit)
access : read-write


PROC0_INTF

Interrupt Force for proc0
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PROC0_INTF PROC0_INTF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIO_QSPI_SCLK_LEVEL_LOW GPIO_QSPI_SCLK_LEVEL_HIGH GPIO_QSPI_SCLK_EDGE_LOW GPIO_QSPI_SCLK_EDGE_HIGH GPIO_QSPI_SS_LEVEL_LOW GPIO_QSPI_SS_LEVEL_HIGH GPIO_QSPI_SS_EDGE_LOW GPIO_QSPI_SS_EDGE_HIGH GPIO_QSPI_SD0_LEVEL_LOW GPIO_QSPI_SD0_LEVEL_HIGH GPIO_QSPI_SD0_EDGE_LOW GPIO_QSPI_SD0_EDGE_HIGH GPIO_QSPI_SD1_LEVEL_LOW GPIO_QSPI_SD1_LEVEL_HIGH GPIO_QSPI_SD1_EDGE_LOW GPIO_QSPI_SD1_EDGE_HIGH GPIO_QSPI_SD2_LEVEL_LOW GPIO_QSPI_SD2_LEVEL_HIGH GPIO_QSPI_SD2_EDGE_LOW GPIO_QSPI_SD2_EDGE_HIGH GPIO_QSPI_SD3_LEVEL_LOW GPIO_QSPI_SD3_LEVEL_HIGH GPIO_QSPI_SD3_EDGE_LOW GPIO_QSPI_SD3_EDGE_HIGH

GPIO_QSPI_SCLK_LEVEL_LOW :
bits : 0 - 0 (1 bit)
access : read-write

GPIO_QSPI_SCLK_LEVEL_HIGH :
bits : 1 - 1 (1 bit)
access : read-write

GPIO_QSPI_SCLK_EDGE_LOW :
bits : 2 - 2 (1 bit)
access : read-write

GPIO_QSPI_SCLK_EDGE_HIGH :
bits : 3 - 3 (1 bit)
access : read-write

GPIO_QSPI_SS_LEVEL_LOW :
bits : 4 - 4 (1 bit)
access : read-write

GPIO_QSPI_SS_LEVEL_HIGH :
bits : 5 - 5 (1 bit)
access : read-write

GPIO_QSPI_SS_EDGE_LOW :
bits : 6 - 6 (1 bit)
access : read-write

GPIO_QSPI_SS_EDGE_HIGH :
bits : 7 - 7 (1 bit)
access : read-write

GPIO_QSPI_SD0_LEVEL_LOW :
bits : 8 - 8 (1 bit)
access : read-write

GPIO_QSPI_SD0_LEVEL_HIGH :
bits : 9 - 9 (1 bit)
access : read-write

GPIO_QSPI_SD0_EDGE_LOW :
bits : 10 - 10 (1 bit)
access : read-write

GPIO_QSPI_SD0_EDGE_HIGH :
bits : 11 - 11 (1 bit)
access : read-write

GPIO_QSPI_SD1_LEVEL_LOW :
bits : 12 - 12 (1 bit)
access : read-write

GPIO_QSPI_SD1_LEVEL_HIGH :
bits : 13 - 13 (1 bit)
access : read-write

GPIO_QSPI_SD1_EDGE_LOW :
bits : 14 - 14 (1 bit)
access : read-write

GPIO_QSPI_SD1_EDGE_HIGH :
bits : 15 - 15 (1 bit)
access : read-write

GPIO_QSPI_SD2_LEVEL_LOW :
bits : 16 - 16 (1 bit)
access : read-write

GPIO_QSPI_SD2_LEVEL_HIGH :
bits : 17 - 17 (1 bit)
access : read-write

GPIO_QSPI_SD2_EDGE_LOW :
bits : 18 - 18 (1 bit)
access : read-write

GPIO_QSPI_SD2_EDGE_HIGH :
bits : 19 - 19 (1 bit)
access : read-write

GPIO_QSPI_SD3_LEVEL_LOW :
bits : 20 - 20 (1 bit)
access : read-write

GPIO_QSPI_SD3_LEVEL_HIGH :
bits : 21 - 21 (1 bit)
access : read-write

GPIO_QSPI_SD3_EDGE_LOW :
bits : 22 - 22 (1 bit)
access : read-write

GPIO_QSPI_SD3_EDGE_HIGH :
bits : 23 - 23 (1 bit)
access : read-write


PROC0_INTS

Interrupt status after masking & forcing for proc0
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PROC0_INTS PROC0_INTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIO_QSPI_SCLK_LEVEL_LOW GPIO_QSPI_SCLK_LEVEL_HIGH GPIO_QSPI_SCLK_EDGE_LOW GPIO_QSPI_SCLK_EDGE_HIGH GPIO_QSPI_SS_LEVEL_LOW GPIO_QSPI_SS_LEVEL_HIGH GPIO_QSPI_SS_EDGE_LOW GPIO_QSPI_SS_EDGE_HIGH GPIO_QSPI_SD0_LEVEL_LOW GPIO_QSPI_SD0_LEVEL_HIGH GPIO_QSPI_SD0_EDGE_LOW GPIO_QSPI_SD0_EDGE_HIGH GPIO_QSPI_SD1_LEVEL_LOW GPIO_QSPI_SD1_LEVEL_HIGH GPIO_QSPI_SD1_EDGE_LOW GPIO_QSPI_SD1_EDGE_HIGH GPIO_QSPI_SD2_LEVEL_LOW GPIO_QSPI_SD2_LEVEL_HIGH GPIO_QSPI_SD2_EDGE_LOW GPIO_QSPI_SD2_EDGE_HIGH GPIO_QSPI_SD3_LEVEL_LOW GPIO_QSPI_SD3_LEVEL_HIGH GPIO_QSPI_SD3_EDGE_LOW GPIO_QSPI_SD3_EDGE_HIGH

GPIO_QSPI_SCLK_LEVEL_LOW :
bits : 0 - 0 (1 bit)
access : read-only

GPIO_QSPI_SCLK_LEVEL_HIGH :
bits : 1 - 1 (1 bit)
access : read-only

GPIO_QSPI_SCLK_EDGE_LOW :
bits : 2 - 2 (1 bit)
access : read-only

GPIO_QSPI_SCLK_EDGE_HIGH :
bits : 3 - 3 (1 bit)
access : read-only

GPIO_QSPI_SS_LEVEL_LOW :
bits : 4 - 4 (1 bit)
access : read-only

GPIO_QSPI_SS_LEVEL_HIGH :
bits : 5 - 5 (1 bit)
access : read-only

GPIO_QSPI_SS_EDGE_LOW :
bits : 6 - 6 (1 bit)
access : read-only

GPIO_QSPI_SS_EDGE_HIGH :
bits : 7 - 7 (1 bit)
access : read-only

GPIO_QSPI_SD0_LEVEL_LOW :
bits : 8 - 8 (1 bit)
access : read-only

GPIO_QSPI_SD0_LEVEL_HIGH :
bits : 9 - 9 (1 bit)
access : read-only

GPIO_QSPI_SD0_EDGE_LOW :
bits : 10 - 10 (1 bit)
access : read-only

GPIO_QSPI_SD0_EDGE_HIGH :
bits : 11 - 11 (1 bit)
access : read-only

GPIO_QSPI_SD1_LEVEL_LOW :
bits : 12 - 12 (1 bit)
access : read-only

GPIO_QSPI_SD1_LEVEL_HIGH :
bits : 13 - 13 (1 bit)
access : read-only

GPIO_QSPI_SD1_EDGE_LOW :
bits : 14 - 14 (1 bit)
access : read-only

GPIO_QSPI_SD1_EDGE_HIGH :
bits : 15 - 15 (1 bit)
access : read-only

GPIO_QSPI_SD2_LEVEL_LOW :
bits : 16 - 16 (1 bit)
access : read-only

GPIO_QSPI_SD2_LEVEL_HIGH :
bits : 17 - 17 (1 bit)
access : read-only

GPIO_QSPI_SD2_EDGE_LOW :
bits : 18 - 18 (1 bit)
access : read-only

GPIO_QSPI_SD2_EDGE_HIGH :
bits : 19 - 19 (1 bit)
access : read-only

GPIO_QSPI_SD3_LEVEL_LOW :
bits : 20 - 20 (1 bit)
access : read-only

GPIO_QSPI_SD3_LEVEL_HIGH :
bits : 21 - 21 (1 bit)
access : read-only

GPIO_QSPI_SD3_EDGE_LOW :
bits : 22 - 22 (1 bit)
access : read-only

GPIO_QSPI_SD3_EDGE_HIGH :
bits : 23 - 23 (1 bit)
access : read-only


GPIO_QSPI_SCLK_CTRL

GPIO control including function select and overrides.
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO_QSPI_SCLK_CTRL GPIO_QSPI_SCLK_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FUNCSEL OUTOVER OEOVER INOVER IRQOVER

FUNCSEL : 0-31 -> selects pin function according to the gpio table 31 == NULL
bits : 0 - 4 (5 bit)
access : read-write

Enumeration:

0 : xip_sclk

None

5 : sio_30

None

31 : null

None

End of enumeration elements list.

OUTOVER :
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : NORMAL

drive output from peripheral signal selected by funcsel

1 : INVERT

drive output from inverse of peripheral signal selected by funcsel

2 : LOW

drive output low

3 : HIGH

drive output high

End of enumeration elements list.

OEOVER :
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : NORMAL

drive output enable from peripheral signal selected by funcsel

1 : INVERT

drive output enable from inverse of peripheral signal selected by funcsel

2 : DISABLE

disable output

3 : ENABLE

enable output

End of enumeration elements list.

INOVER :
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0 : NORMAL

don't invert the peri input

1 : INVERT

invert the peri input

2 : LOW

drive peri input low

3 : HIGH

drive peri input high

End of enumeration elements list.

IRQOVER :
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

0 : NORMAL

don't invert the interrupt

1 : INVERT

invert the interrupt

2 : LOW

drive interrupt low

3 : HIGH

drive interrupt high

End of enumeration elements list.


PROC1_INTE

Interrupt Enable for proc1
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PROC1_INTE PROC1_INTE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIO_QSPI_SCLK_LEVEL_LOW GPIO_QSPI_SCLK_LEVEL_HIGH GPIO_QSPI_SCLK_EDGE_LOW GPIO_QSPI_SCLK_EDGE_HIGH GPIO_QSPI_SS_LEVEL_LOW GPIO_QSPI_SS_LEVEL_HIGH GPIO_QSPI_SS_EDGE_LOW GPIO_QSPI_SS_EDGE_HIGH GPIO_QSPI_SD0_LEVEL_LOW GPIO_QSPI_SD0_LEVEL_HIGH GPIO_QSPI_SD0_EDGE_LOW GPIO_QSPI_SD0_EDGE_HIGH GPIO_QSPI_SD1_LEVEL_LOW GPIO_QSPI_SD1_LEVEL_HIGH GPIO_QSPI_SD1_EDGE_LOW GPIO_QSPI_SD1_EDGE_HIGH GPIO_QSPI_SD2_LEVEL_LOW GPIO_QSPI_SD2_LEVEL_HIGH GPIO_QSPI_SD2_EDGE_LOW GPIO_QSPI_SD2_EDGE_HIGH GPIO_QSPI_SD3_LEVEL_LOW GPIO_QSPI_SD3_LEVEL_HIGH GPIO_QSPI_SD3_EDGE_LOW GPIO_QSPI_SD3_EDGE_HIGH

GPIO_QSPI_SCLK_LEVEL_LOW :
bits : 0 - 0 (1 bit)
access : read-write

GPIO_QSPI_SCLK_LEVEL_HIGH :
bits : 1 - 1 (1 bit)
access : read-write

GPIO_QSPI_SCLK_EDGE_LOW :
bits : 2 - 2 (1 bit)
access : read-write

GPIO_QSPI_SCLK_EDGE_HIGH :
bits : 3 - 3 (1 bit)
access : read-write

GPIO_QSPI_SS_LEVEL_LOW :
bits : 4 - 4 (1 bit)
access : read-write

GPIO_QSPI_SS_LEVEL_HIGH :
bits : 5 - 5 (1 bit)
access : read-write

GPIO_QSPI_SS_EDGE_LOW :
bits : 6 - 6 (1 bit)
access : read-write

GPIO_QSPI_SS_EDGE_HIGH :
bits : 7 - 7 (1 bit)
access : read-write

GPIO_QSPI_SD0_LEVEL_LOW :
bits : 8 - 8 (1 bit)
access : read-write

GPIO_QSPI_SD0_LEVEL_HIGH :
bits : 9 - 9 (1 bit)
access : read-write

GPIO_QSPI_SD0_EDGE_LOW :
bits : 10 - 10 (1 bit)
access : read-write

GPIO_QSPI_SD0_EDGE_HIGH :
bits : 11 - 11 (1 bit)
access : read-write

GPIO_QSPI_SD1_LEVEL_LOW :
bits : 12 - 12 (1 bit)
access : read-write

GPIO_QSPI_SD1_LEVEL_HIGH :
bits : 13 - 13 (1 bit)
access : read-write

GPIO_QSPI_SD1_EDGE_LOW :
bits : 14 - 14 (1 bit)
access : read-write

GPIO_QSPI_SD1_EDGE_HIGH :
bits : 15 - 15 (1 bit)
access : read-write

GPIO_QSPI_SD2_LEVEL_LOW :
bits : 16 - 16 (1 bit)
access : read-write

GPIO_QSPI_SD2_LEVEL_HIGH :
bits : 17 - 17 (1 bit)
access : read-write

GPIO_QSPI_SD2_EDGE_LOW :
bits : 18 - 18 (1 bit)
access : read-write

GPIO_QSPI_SD2_EDGE_HIGH :
bits : 19 - 19 (1 bit)
access : read-write

GPIO_QSPI_SD3_LEVEL_LOW :
bits : 20 - 20 (1 bit)
access : read-write

GPIO_QSPI_SD3_LEVEL_HIGH :
bits : 21 - 21 (1 bit)
access : read-write

GPIO_QSPI_SD3_EDGE_LOW :
bits : 22 - 22 (1 bit)
access : read-write

GPIO_QSPI_SD3_EDGE_HIGH :
bits : 23 - 23 (1 bit)
access : read-write


PROC1_INTF

Interrupt Force for proc1
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PROC1_INTF PROC1_INTF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIO_QSPI_SCLK_LEVEL_LOW GPIO_QSPI_SCLK_LEVEL_HIGH GPIO_QSPI_SCLK_EDGE_LOW GPIO_QSPI_SCLK_EDGE_HIGH GPIO_QSPI_SS_LEVEL_LOW GPIO_QSPI_SS_LEVEL_HIGH GPIO_QSPI_SS_EDGE_LOW GPIO_QSPI_SS_EDGE_HIGH GPIO_QSPI_SD0_LEVEL_LOW GPIO_QSPI_SD0_LEVEL_HIGH GPIO_QSPI_SD0_EDGE_LOW GPIO_QSPI_SD0_EDGE_HIGH GPIO_QSPI_SD1_LEVEL_LOW GPIO_QSPI_SD1_LEVEL_HIGH GPIO_QSPI_SD1_EDGE_LOW GPIO_QSPI_SD1_EDGE_HIGH GPIO_QSPI_SD2_LEVEL_LOW GPIO_QSPI_SD2_LEVEL_HIGH GPIO_QSPI_SD2_EDGE_LOW GPIO_QSPI_SD2_EDGE_HIGH GPIO_QSPI_SD3_LEVEL_LOW GPIO_QSPI_SD3_LEVEL_HIGH GPIO_QSPI_SD3_EDGE_LOW GPIO_QSPI_SD3_EDGE_HIGH

GPIO_QSPI_SCLK_LEVEL_LOW :
bits : 0 - 0 (1 bit)
access : read-write

GPIO_QSPI_SCLK_LEVEL_HIGH :
bits : 1 - 1 (1 bit)
access : read-write

GPIO_QSPI_SCLK_EDGE_LOW :
bits : 2 - 2 (1 bit)
access : read-write

GPIO_QSPI_SCLK_EDGE_HIGH :
bits : 3 - 3 (1 bit)
access : read-write

GPIO_QSPI_SS_LEVEL_LOW :
bits : 4 - 4 (1 bit)
access : read-write

GPIO_QSPI_SS_LEVEL_HIGH :
bits : 5 - 5 (1 bit)
access : read-write

GPIO_QSPI_SS_EDGE_LOW :
bits : 6 - 6 (1 bit)
access : read-write

GPIO_QSPI_SS_EDGE_HIGH :
bits : 7 - 7 (1 bit)
access : read-write

GPIO_QSPI_SD0_LEVEL_LOW :
bits : 8 - 8 (1 bit)
access : read-write

GPIO_QSPI_SD0_LEVEL_HIGH :
bits : 9 - 9 (1 bit)
access : read-write

GPIO_QSPI_SD0_EDGE_LOW :
bits : 10 - 10 (1 bit)
access : read-write

GPIO_QSPI_SD0_EDGE_HIGH :
bits : 11 - 11 (1 bit)
access : read-write

GPIO_QSPI_SD1_LEVEL_LOW :
bits : 12 - 12 (1 bit)
access : read-write

GPIO_QSPI_SD1_LEVEL_HIGH :
bits : 13 - 13 (1 bit)
access : read-write

GPIO_QSPI_SD1_EDGE_LOW :
bits : 14 - 14 (1 bit)
access : read-write

GPIO_QSPI_SD1_EDGE_HIGH :
bits : 15 - 15 (1 bit)
access : read-write

GPIO_QSPI_SD2_LEVEL_LOW :
bits : 16 - 16 (1 bit)
access : read-write

GPIO_QSPI_SD2_LEVEL_HIGH :
bits : 17 - 17 (1 bit)
access : read-write

GPIO_QSPI_SD2_EDGE_LOW :
bits : 18 - 18 (1 bit)
access : read-write

GPIO_QSPI_SD2_EDGE_HIGH :
bits : 19 - 19 (1 bit)
access : read-write

GPIO_QSPI_SD3_LEVEL_LOW :
bits : 20 - 20 (1 bit)
access : read-write

GPIO_QSPI_SD3_LEVEL_HIGH :
bits : 21 - 21 (1 bit)
access : read-write

GPIO_QSPI_SD3_EDGE_LOW :
bits : 22 - 22 (1 bit)
access : read-write

GPIO_QSPI_SD3_EDGE_HIGH :
bits : 23 - 23 (1 bit)
access : read-write


PROC1_INTS

Interrupt status after masking & forcing for proc1
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PROC1_INTS PROC1_INTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIO_QSPI_SCLK_LEVEL_LOW GPIO_QSPI_SCLK_LEVEL_HIGH GPIO_QSPI_SCLK_EDGE_LOW GPIO_QSPI_SCLK_EDGE_HIGH GPIO_QSPI_SS_LEVEL_LOW GPIO_QSPI_SS_LEVEL_HIGH GPIO_QSPI_SS_EDGE_LOW GPIO_QSPI_SS_EDGE_HIGH GPIO_QSPI_SD0_LEVEL_LOW GPIO_QSPI_SD0_LEVEL_HIGH GPIO_QSPI_SD0_EDGE_LOW GPIO_QSPI_SD0_EDGE_HIGH GPIO_QSPI_SD1_LEVEL_LOW GPIO_QSPI_SD1_LEVEL_HIGH GPIO_QSPI_SD1_EDGE_LOW GPIO_QSPI_SD1_EDGE_HIGH GPIO_QSPI_SD2_LEVEL_LOW GPIO_QSPI_SD2_LEVEL_HIGH GPIO_QSPI_SD2_EDGE_LOW GPIO_QSPI_SD2_EDGE_HIGH GPIO_QSPI_SD3_LEVEL_LOW GPIO_QSPI_SD3_LEVEL_HIGH GPIO_QSPI_SD3_EDGE_LOW GPIO_QSPI_SD3_EDGE_HIGH

GPIO_QSPI_SCLK_LEVEL_LOW :
bits : 0 - 0 (1 bit)
access : read-only

GPIO_QSPI_SCLK_LEVEL_HIGH :
bits : 1 - 1 (1 bit)
access : read-only

GPIO_QSPI_SCLK_EDGE_LOW :
bits : 2 - 2 (1 bit)
access : read-only

GPIO_QSPI_SCLK_EDGE_HIGH :
bits : 3 - 3 (1 bit)
access : read-only

GPIO_QSPI_SS_LEVEL_LOW :
bits : 4 - 4 (1 bit)
access : read-only

GPIO_QSPI_SS_LEVEL_HIGH :
bits : 5 - 5 (1 bit)
access : read-only

GPIO_QSPI_SS_EDGE_LOW :
bits : 6 - 6 (1 bit)
access : read-only

GPIO_QSPI_SS_EDGE_HIGH :
bits : 7 - 7 (1 bit)
access : read-only

GPIO_QSPI_SD0_LEVEL_LOW :
bits : 8 - 8 (1 bit)
access : read-only

GPIO_QSPI_SD0_LEVEL_HIGH :
bits : 9 - 9 (1 bit)
access : read-only

GPIO_QSPI_SD0_EDGE_LOW :
bits : 10 - 10 (1 bit)
access : read-only

GPIO_QSPI_SD0_EDGE_HIGH :
bits : 11 - 11 (1 bit)
access : read-only

GPIO_QSPI_SD1_LEVEL_LOW :
bits : 12 - 12 (1 bit)
access : read-only

GPIO_QSPI_SD1_LEVEL_HIGH :
bits : 13 - 13 (1 bit)
access : read-only

GPIO_QSPI_SD1_EDGE_LOW :
bits : 14 - 14 (1 bit)
access : read-only

GPIO_QSPI_SD1_EDGE_HIGH :
bits : 15 - 15 (1 bit)
access : read-only

GPIO_QSPI_SD2_LEVEL_LOW :
bits : 16 - 16 (1 bit)
access : read-only

GPIO_QSPI_SD2_LEVEL_HIGH :
bits : 17 - 17 (1 bit)
access : read-only

GPIO_QSPI_SD2_EDGE_LOW :
bits : 18 - 18 (1 bit)
access : read-only

GPIO_QSPI_SD2_EDGE_HIGH :
bits : 19 - 19 (1 bit)
access : read-only

GPIO_QSPI_SD3_LEVEL_LOW :
bits : 20 - 20 (1 bit)
access : read-only

GPIO_QSPI_SD3_LEVEL_HIGH :
bits : 21 - 21 (1 bit)
access : read-only

GPIO_QSPI_SD3_EDGE_LOW :
bits : 22 - 22 (1 bit)
access : read-only

GPIO_QSPI_SD3_EDGE_HIGH :
bits : 23 - 23 (1 bit)
access : read-only


DORMANT_WAKE_INTE

Interrupt Enable for dormant_wake
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DORMANT_WAKE_INTE DORMANT_WAKE_INTE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIO_QSPI_SCLK_LEVEL_LOW GPIO_QSPI_SCLK_LEVEL_HIGH GPIO_QSPI_SCLK_EDGE_LOW GPIO_QSPI_SCLK_EDGE_HIGH GPIO_QSPI_SS_LEVEL_LOW GPIO_QSPI_SS_LEVEL_HIGH GPIO_QSPI_SS_EDGE_LOW GPIO_QSPI_SS_EDGE_HIGH GPIO_QSPI_SD0_LEVEL_LOW GPIO_QSPI_SD0_LEVEL_HIGH GPIO_QSPI_SD0_EDGE_LOW GPIO_QSPI_SD0_EDGE_HIGH GPIO_QSPI_SD1_LEVEL_LOW GPIO_QSPI_SD1_LEVEL_HIGH GPIO_QSPI_SD1_EDGE_LOW GPIO_QSPI_SD1_EDGE_HIGH GPIO_QSPI_SD2_LEVEL_LOW GPIO_QSPI_SD2_LEVEL_HIGH GPIO_QSPI_SD2_EDGE_LOW GPIO_QSPI_SD2_EDGE_HIGH GPIO_QSPI_SD3_LEVEL_LOW GPIO_QSPI_SD3_LEVEL_HIGH GPIO_QSPI_SD3_EDGE_LOW GPIO_QSPI_SD3_EDGE_HIGH

GPIO_QSPI_SCLK_LEVEL_LOW :
bits : 0 - 0 (1 bit)
access : read-write

GPIO_QSPI_SCLK_LEVEL_HIGH :
bits : 1 - 1 (1 bit)
access : read-write

GPIO_QSPI_SCLK_EDGE_LOW :
bits : 2 - 2 (1 bit)
access : read-write

GPIO_QSPI_SCLK_EDGE_HIGH :
bits : 3 - 3 (1 bit)
access : read-write

GPIO_QSPI_SS_LEVEL_LOW :
bits : 4 - 4 (1 bit)
access : read-write

GPIO_QSPI_SS_LEVEL_HIGH :
bits : 5 - 5 (1 bit)
access : read-write

GPIO_QSPI_SS_EDGE_LOW :
bits : 6 - 6 (1 bit)
access : read-write

GPIO_QSPI_SS_EDGE_HIGH :
bits : 7 - 7 (1 bit)
access : read-write

GPIO_QSPI_SD0_LEVEL_LOW :
bits : 8 - 8 (1 bit)
access : read-write

GPIO_QSPI_SD0_LEVEL_HIGH :
bits : 9 - 9 (1 bit)
access : read-write

GPIO_QSPI_SD0_EDGE_LOW :
bits : 10 - 10 (1 bit)
access : read-write

GPIO_QSPI_SD0_EDGE_HIGH :
bits : 11 - 11 (1 bit)
access : read-write

GPIO_QSPI_SD1_LEVEL_LOW :
bits : 12 - 12 (1 bit)
access : read-write

GPIO_QSPI_SD1_LEVEL_HIGH :
bits : 13 - 13 (1 bit)
access : read-write

GPIO_QSPI_SD1_EDGE_LOW :
bits : 14 - 14 (1 bit)
access : read-write

GPIO_QSPI_SD1_EDGE_HIGH :
bits : 15 - 15 (1 bit)
access : read-write

GPIO_QSPI_SD2_LEVEL_LOW :
bits : 16 - 16 (1 bit)
access : read-write

GPIO_QSPI_SD2_LEVEL_HIGH :
bits : 17 - 17 (1 bit)
access : read-write

GPIO_QSPI_SD2_EDGE_LOW :
bits : 18 - 18 (1 bit)
access : read-write

GPIO_QSPI_SD2_EDGE_HIGH :
bits : 19 - 19 (1 bit)
access : read-write

GPIO_QSPI_SD3_LEVEL_LOW :
bits : 20 - 20 (1 bit)
access : read-write

GPIO_QSPI_SD3_LEVEL_HIGH :
bits : 21 - 21 (1 bit)
access : read-write

GPIO_QSPI_SD3_EDGE_LOW :
bits : 22 - 22 (1 bit)
access : read-write

GPIO_QSPI_SD3_EDGE_HIGH :
bits : 23 - 23 (1 bit)
access : read-write


DORMANT_WAKE_INTF

Interrupt Force for dormant_wake
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DORMANT_WAKE_INTF DORMANT_WAKE_INTF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIO_QSPI_SCLK_LEVEL_LOW GPIO_QSPI_SCLK_LEVEL_HIGH GPIO_QSPI_SCLK_EDGE_LOW GPIO_QSPI_SCLK_EDGE_HIGH GPIO_QSPI_SS_LEVEL_LOW GPIO_QSPI_SS_LEVEL_HIGH GPIO_QSPI_SS_EDGE_LOW GPIO_QSPI_SS_EDGE_HIGH GPIO_QSPI_SD0_LEVEL_LOW GPIO_QSPI_SD0_LEVEL_HIGH GPIO_QSPI_SD0_EDGE_LOW GPIO_QSPI_SD0_EDGE_HIGH GPIO_QSPI_SD1_LEVEL_LOW GPIO_QSPI_SD1_LEVEL_HIGH GPIO_QSPI_SD1_EDGE_LOW GPIO_QSPI_SD1_EDGE_HIGH GPIO_QSPI_SD2_LEVEL_LOW GPIO_QSPI_SD2_LEVEL_HIGH GPIO_QSPI_SD2_EDGE_LOW GPIO_QSPI_SD2_EDGE_HIGH GPIO_QSPI_SD3_LEVEL_LOW GPIO_QSPI_SD3_LEVEL_HIGH GPIO_QSPI_SD3_EDGE_LOW GPIO_QSPI_SD3_EDGE_HIGH

GPIO_QSPI_SCLK_LEVEL_LOW :
bits : 0 - 0 (1 bit)
access : read-write

GPIO_QSPI_SCLK_LEVEL_HIGH :
bits : 1 - 1 (1 bit)
access : read-write

GPIO_QSPI_SCLK_EDGE_LOW :
bits : 2 - 2 (1 bit)
access : read-write

GPIO_QSPI_SCLK_EDGE_HIGH :
bits : 3 - 3 (1 bit)
access : read-write

GPIO_QSPI_SS_LEVEL_LOW :
bits : 4 - 4 (1 bit)
access : read-write

GPIO_QSPI_SS_LEVEL_HIGH :
bits : 5 - 5 (1 bit)
access : read-write

GPIO_QSPI_SS_EDGE_LOW :
bits : 6 - 6 (1 bit)
access : read-write

GPIO_QSPI_SS_EDGE_HIGH :
bits : 7 - 7 (1 bit)
access : read-write

GPIO_QSPI_SD0_LEVEL_LOW :
bits : 8 - 8 (1 bit)
access : read-write

GPIO_QSPI_SD0_LEVEL_HIGH :
bits : 9 - 9 (1 bit)
access : read-write

GPIO_QSPI_SD0_EDGE_LOW :
bits : 10 - 10 (1 bit)
access : read-write

GPIO_QSPI_SD0_EDGE_HIGH :
bits : 11 - 11 (1 bit)
access : read-write

GPIO_QSPI_SD1_LEVEL_LOW :
bits : 12 - 12 (1 bit)
access : read-write

GPIO_QSPI_SD1_LEVEL_HIGH :
bits : 13 - 13 (1 bit)
access : read-write

GPIO_QSPI_SD1_EDGE_LOW :
bits : 14 - 14 (1 bit)
access : read-write

GPIO_QSPI_SD1_EDGE_HIGH :
bits : 15 - 15 (1 bit)
access : read-write

GPIO_QSPI_SD2_LEVEL_LOW :
bits : 16 - 16 (1 bit)
access : read-write

GPIO_QSPI_SD2_LEVEL_HIGH :
bits : 17 - 17 (1 bit)
access : read-write

GPIO_QSPI_SD2_EDGE_LOW :
bits : 18 - 18 (1 bit)
access : read-write

GPIO_QSPI_SD2_EDGE_HIGH :
bits : 19 - 19 (1 bit)
access : read-write

GPIO_QSPI_SD3_LEVEL_LOW :
bits : 20 - 20 (1 bit)
access : read-write

GPIO_QSPI_SD3_LEVEL_HIGH :
bits : 21 - 21 (1 bit)
access : read-write

GPIO_QSPI_SD3_EDGE_LOW :
bits : 22 - 22 (1 bit)
access : read-write

GPIO_QSPI_SD3_EDGE_HIGH :
bits : 23 - 23 (1 bit)
access : read-write


DORMANT_WAKE_INTS

Interrupt status after masking & forcing for dormant_wake
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DORMANT_WAKE_INTS DORMANT_WAKE_INTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIO_QSPI_SCLK_LEVEL_LOW GPIO_QSPI_SCLK_LEVEL_HIGH GPIO_QSPI_SCLK_EDGE_LOW GPIO_QSPI_SCLK_EDGE_HIGH GPIO_QSPI_SS_LEVEL_LOW GPIO_QSPI_SS_LEVEL_HIGH GPIO_QSPI_SS_EDGE_LOW GPIO_QSPI_SS_EDGE_HIGH GPIO_QSPI_SD0_LEVEL_LOW GPIO_QSPI_SD0_LEVEL_HIGH GPIO_QSPI_SD0_EDGE_LOW GPIO_QSPI_SD0_EDGE_HIGH GPIO_QSPI_SD1_LEVEL_LOW GPIO_QSPI_SD1_LEVEL_HIGH GPIO_QSPI_SD1_EDGE_LOW GPIO_QSPI_SD1_EDGE_HIGH GPIO_QSPI_SD2_LEVEL_LOW GPIO_QSPI_SD2_LEVEL_HIGH GPIO_QSPI_SD2_EDGE_LOW GPIO_QSPI_SD2_EDGE_HIGH GPIO_QSPI_SD3_LEVEL_LOW GPIO_QSPI_SD3_LEVEL_HIGH GPIO_QSPI_SD3_EDGE_LOW GPIO_QSPI_SD3_EDGE_HIGH

GPIO_QSPI_SCLK_LEVEL_LOW :
bits : 0 - 0 (1 bit)
access : read-only

GPIO_QSPI_SCLK_LEVEL_HIGH :
bits : 1 - 1 (1 bit)
access : read-only

GPIO_QSPI_SCLK_EDGE_LOW :
bits : 2 - 2 (1 bit)
access : read-only

GPIO_QSPI_SCLK_EDGE_HIGH :
bits : 3 - 3 (1 bit)
access : read-only

GPIO_QSPI_SS_LEVEL_LOW :
bits : 4 - 4 (1 bit)
access : read-only

GPIO_QSPI_SS_LEVEL_HIGH :
bits : 5 - 5 (1 bit)
access : read-only

GPIO_QSPI_SS_EDGE_LOW :
bits : 6 - 6 (1 bit)
access : read-only

GPIO_QSPI_SS_EDGE_HIGH :
bits : 7 - 7 (1 bit)
access : read-only

GPIO_QSPI_SD0_LEVEL_LOW :
bits : 8 - 8 (1 bit)
access : read-only

GPIO_QSPI_SD0_LEVEL_HIGH :
bits : 9 - 9 (1 bit)
access : read-only

GPIO_QSPI_SD0_EDGE_LOW :
bits : 10 - 10 (1 bit)
access : read-only

GPIO_QSPI_SD0_EDGE_HIGH :
bits : 11 - 11 (1 bit)
access : read-only

GPIO_QSPI_SD1_LEVEL_LOW :
bits : 12 - 12 (1 bit)
access : read-only

GPIO_QSPI_SD1_LEVEL_HIGH :
bits : 13 - 13 (1 bit)
access : read-only

GPIO_QSPI_SD1_EDGE_LOW :
bits : 14 - 14 (1 bit)
access : read-only

GPIO_QSPI_SD1_EDGE_HIGH :
bits : 15 - 15 (1 bit)
access : read-only

GPIO_QSPI_SD2_LEVEL_LOW :
bits : 16 - 16 (1 bit)
access : read-only

GPIO_QSPI_SD2_LEVEL_HIGH :
bits : 17 - 17 (1 bit)
access : read-only

GPIO_QSPI_SD2_EDGE_LOW :
bits : 18 - 18 (1 bit)
access : read-only

GPIO_QSPI_SD2_EDGE_HIGH :
bits : 19 - 19 (1 bit)
access : read-only

GPIO_QSPI_SD3_LEVEL_LOW :
bits : 20 - 20 (1 bit)
access : read-only

GPIO_QSPI_SD3_LEVEL_HIGH :
bits : 21 - 21 (1 bit)
access : read-only

GPIO_QSPI_SD3_EDGE_LOW :
bits : 22 - 22 (1 bit)
access : read-only

GPIO_QSPI_SD3_EDGE_HIGH :
bits : 23 - 23 (1 bit)
access : read-only


GPIO_QSPI_SS_STATUS

GPIO status
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO_QSPI_SS_STATUS GPIO_QSPI_SS_STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUTFROMPERI OUTTOPAD OEFROMPERI OETOPAD INFROMPAD INTOPERI IRQFROMPAD IRQTOPROC

OUTFROMPERI : output signal from selected peripheral, before register override is applied
bits : 8 - 8 (1 bit)
access : read-only

OUTTOPAD : output signal to pad after register override is applied
bits : 9 - 9 (1 bit)
access : read-only

OEFROMPERI : output enable from selected peripheral, before register override is applied
bits : 12 - 12 (1 bit)
access : read-only

OETOPAD : output enable to pad after register override is applied
bits : 13 - 13 (1 bit)
access : read-only

INFROMPAD : input signal from pad, before override is applied
bits : 17 - 17 (1 bit)
access : read-only

INTOPERI : input signal to peripheral, after override is applied
bits : 19 - 19 (1 bit)
access : read-only

IRQFROMPAD : interrupt from pad before override is applied
bits : 24 - 24 (1 bit)
access : read-only

IRQTOPROC : interrupt to processors, after override is applied
bits : 26 - 26 (1 bit)
access : read-only


GPIO_QSPI_SS_CTRL

GPIO control including function select and overrides.
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO_QSPI_SS_CTRL GPIO_QSPI_SS_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FUNCSEL OUTOVER OEOVER INOVER IRQOVER

FUNCSEL : 0-31 -> selects pin function according to the gpio table 31 == NULL
bits : 0 - 4 (5 bit)
access : read-write

Enumeration:

0 : xip_ss_n

None

5 : sio_31

None

31 : null

None

End of enumeration elements list.

OUTOVER :
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : NORMAL

drive output from peripheral signal selected by funcsel

1 : INVERT

drive output from inverse of peripheral signal selected by funcsel

2 : LOW

drive output low

3 : HIGH

drive output high

End of enumeration elements list.

OEOVER :
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : NORMAL

drive output enable from peripheral signal selected by funcsel

1 : INVERT

drive output enable from inverse of peripheral signal selected by funcsel

2 : DISABLE

disable output

3 : ENABLE

enable output

End of enumeration elements list.

INOVER :
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0 : NORMAL

don't invert the peri input

1 : INVERT

invert the peri input

2 : LOW

drive peri input low

3 : HIGH

drive peri input high

End of enumeration elements list.

IRQOVER :
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

0 : NORMAL

don't invert the interrupt

1 : INVERT

invert the interrupt

2 : LOW

drive interrupt low

3 : HIGH

drive interrupt high

End of enumeration elements list.



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