\n
address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
Crystal Oscillator Control
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FREQ_RANGE : Frequency range. This resets to 0xAA0 and cannot be changed.
bits : 0 - 11 (12 bit)
access : read-write
Enumeration:
2720 : 1_15MHZ
None
2721 : RESERVED_1
None
2722 : RESERVED_2
None
2723 : RESERVED_3
None
End of enumeration elements list.
ENABLE : On power-up this field is initialised to DISABLE and the chip runs from the ROSC.
If the chip has subsequently been programmed to run from the XOSC then setting this field to DISABLE may lock-up the chip. If this is a concern then run the clk_ref from the ROSC and enable the clk_sys RESUS feature.
The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator.
bits : 12 - 23 (12 bit)
access : read-write
Enumeration:
3358 : DISABLE
None
4011 : ENABLE
None
End of enumeration elements list.
A down counter running at the xosc frequency which counts to zero and stops.
To start the counter write a non-zero value.
Can be used for short software pauses when setting up time sensitive hardware.
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT :
bits : 0 - 7 (8 bit)
access : read-write
Crystal Oscillator Status
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FREQ_RANGE : The current frequency range setting, always reads 0
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0 : 1_15MHZ
None
1 : RESERVED_1
None
2 : RESERVED_2
None
3 : RESERVED_3
None
End of enumeration elements list.
ENABLED : Oscillator is enabled but not necessarily running and stable, resets to 0
bits : 12 - 12 (1 bit)
access : read-only
BADWRITE : An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or DORMANT
bits : 24 - 24 (1 bit)
access : read-write
STABLE : Oscillator is running and stable
bits : 31 - 31 (1 bit)
access : read-only
Crystal Oscillator pause control
This is used to save power by pausing the XOSC
On power-up this field is initialised to WAKE
An invalid write will also select WAKE
WARNING: stop the PLLs before selecting dormant mode
WARNING: setup the irq before selecting dormant mode
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Controls the startup delay
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DELAY : in multiples of 256*xtal_period. The reset value of 0xc4 corresponds to approx 50 000 cycles.
bits : 0 - 13 (14 bit)
access : read-write
X4 : Multiplies the startup_delay by 4. This is of little value to the user given that the delay can be programmed directly.
bits : 20 - 20 (1 bit)
access : read-write
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