Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
Control and Status
GENERAL CONSTRAINTS:
Reference clock frequency min=5MHz, max=800MHz
Feedback divider min=16, max=320
VCO frequency min=750MHz, max=1600MHz
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REFDIV : Divides the PLL input reference clock.
Behaviour is undefined for div=0.
PLL output will be unpredictable during refdiv changes, wait for lock=1 before using it.
bits : 0 - 5 (6 bit)
access : read-write
BYPASS : Passes the reference clock to the output instead of the divided VCO. The VCO continues to run so the user can switch between the reference clock and the divided VCO but the output will glitch when doing so.
bits : 8 - 8 (1 bit)
access : read-write
LOCK : PLL is locked
bits : 31 - 31 (1 bit)
access : read-only
Controls the PLL power modes.
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PD : PLL powerdown
To save power set high when PLL output not required.
bits : 0 - 0 (1 bit)
access : read-write
DSMPD : PLL DSM powerdown
Nothing is achieved by setting this low.
bits : 2 - 2 (1 bit)
access : read-write
POSTDIVPD : PLL post divider powerdown
To save power set high when PLL output not required or bypass=1.
bits : 3 - 3 (1 bit)
access : read-write
VCOPD : PLL VCO powerdown
To save power set high when PLL output not required or bypass=1.
bits : 5 - 5 (1 bit)
access : read-write
Feedback divisor
(note: this PLL does not support fractional division)
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FBDIV_INT : see ctrl reg description for constraints
bits : 0 - 11 (12 bit)
access : read-write
Controls the PLL post dividers for the primary output
(note: this PLL does not have a secondary output)
the primary output is driven from VCO divided by postdiv1*postdiv2
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POSTDIV2 : divide by 1-7
bits : 12 - 14 (3 bit)
access : read-write
POSTDIV1 : divide by 1-7
bits : 16 - 18 (3 bit)
access : read-write
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.