UARTDR

UARTFR

UARTILPR

UARTIBRD

UARTFBRD

UARTLCR_H

UARTCR

UARTIFLS

UARTIMSC

UARTRIS

UARTRSR

UARTMIS

UARTICR

UARTDMACR

UARTPERIPHID0

UARTPERIPHID1

UARTPERIPHID2

UARTPERIPHID3

UARTPCELLID0

UARTPCELLID1

UARTPCELLID2

UARTPCELLID3

DATA : Receive (read) data character. Transmit (write) data character.
bits : 0 - 7 (8 bit)
access : read-write

FE : Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). In FIFO mode, this error is associated with the character at the top of the FIFO.
bits : 8 - 8 (1 bit)
access : read-only

PE : Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. In FIFO mode, this error is associated with the character at the top of the FIFO.
bits : 9 - 9 (1 bit)
access : read-only

BE : Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity and stop bits). In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state), and the next valid start bit is received.
bits : 10 - 10 (1 bit)
access : read-only

OE : Overrun error. This bit is set to 1 if data is received and the receive FIFO is already full. This is cleared to 0 once there is an empty space in the FIFO and a new character can be written to it.
bits : 11 - 11 (1 bit)
access : read-only

CTS : Clear to send. This bit is the complement of the UART clear to send, nUARTCTS, modem status input. That is, the bit is 1 when nUARTCTS is LOW.
bits : 0 - 0 (1 bit)
access : read-only

DSR : Data set ready. This bit is the complement of the UART data set ready, nUARTDSR, modem status input. That is, the bit is 1 when nUARTDSR is LOW.
bits : 1 - 1 (1 bit)
access : read-only

DCD : Data carrier detect. This bit is the complement of the UART data carrier detect, nUARTDCD, modem status input. That is, the bit is 1 when nUARTDCD is LOW.
bits : 2 - 2 (1 bit)
access : read-only

BUSY : UART busy. If this bit is set to 1, the UART is busy transmitting data. This bit remains set until the complete byte, including all the stop bits, has been sent from the shift register. This bit is set as soon as the transmit FIFO becomes non-empty, regardless of whether the UART is enabled or not.
bits : 3 - 3 (1 bit)
access : read-only

RXFE : Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is empty. If the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty.
bits : 4 - 4 (1 bit)
access : read-only

TXFF : Transmit FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the transmit holding register is full. If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full.
bits : 5 - 5 (1 bit)
access : read-only

RXFF : Receive FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is full. If the FIFO is enabled, the RXFF bit is set when the receive FIFO is full.
bits : 6 - 6 (1 bit)
access : read-only

TXFE : Transmit FIFO empty. The meaning of this bit depends on the state of the FEN bit in the Line Control Register, UARTLCR_H. If the FIFO is disabled, this bit is set when the transmit holding register is empty. If the FIFO is enabled, the TXFE bit is set when the transmit FIFO is empty. This bit does not indicate if there is data in the transmit shift register.
bits : 7 - 7 (1 bit)
access : read-only

RI : Ring indicator. This bit is the complement of the UART ring indicator, nUARTRI, modem status input. That is, the bit is 1 when nUARTRI is LOW.
bits : 8 - 8 (1 bit)
access : read-only

ILPDVSR : 8-bit low-power divisor value. These bits are cleared to 0 at reset.
bits : 0 - 7 (8 bit)
access : read-write

BAUD_DIVINT : The integer baud rate divisor. These bits are cleared to 0 on reset.
bits : 0 - 15 (16 bit)
access : read-write

BAUD_DIVFRAC : The fractional baud rate divisor. These bits are cleared to 0 on reset.
bits : 0 - 5 (6 bit)
access : read-write

BRK : Send break. If this bit is set to 1, a low-level is continually output on the UARTTXD output, after completing transmission of the current character. For the proper execution of the break command, the software must set this bit for at least two complete frames. For normal use, this bit must be cleared to 0.
bits : 0 - 0 (1 bit)
access : read-write

PEN : Parity enable: 0 = parity is disabled and no parity bit added to the data frame 1 = parity checking and generation is enabled.
bits : 1 - 1 (1 bit)
access : read-write

EPS : Even parity select. Controls the type of parity the UART uses during transmission and reception: 0 = odd parity. The UART generates or checks for an odd number of 1s in the data and parity bits. 1 = even parity. The UART generates or checks for an even number of 1s in the data and parity bits. This bit has no effect when the PEN bit disables parity checking and generation.
bits : 2 - 2 (1 bit)
access : read-write

STP2 : Two stop bits select. If this bit is set to 1, two stop bits are transmitted at the end of the frame. The receive logic does not check for two stop bits being received.
bits : 3 - 3 (1 bit)
access : read-write

FEN : Enable FIFOs: 0 = FIFOs are disabled (character mode) that is, the FIFOs become 1-byte-deep holding registers 1 = transmit and receive FIFO buffers are enabled (FIFO mode).
bits : 4 - 4 (1 bit)
access : read-write

WLEN : Word length. These bits indicate the number of data bits transmitted or received in a frame as follows: b11 = 8 bits b10 = 7 bits b01 = 6 bits b00 = 5 bits.
bits : 5 - 6 (2 bit)
access : read-write

SPS : Stick parity select. 0 = stick parity is disabled 1 = either: * if the EPS bit is 0 then the parity bit is transmitted and checked as a 1 * if the EPS bit is 1 then the parity bit is transmitted and checked as a 0. This bit has no effect when the PEN bit disables parity checking and generation.
bits : 7 - 7 (1 bit)
access : read-write

UARTEN : UART enable: 0 = UART is disabled. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. 1 = the UART is enabled. Data transmission and reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit.
bits : 0 - 0 (1 bit)
access : read-write

SIREN : SIR enable: 0 = IrDA SIR ENDEC is disabled. nSIROUT remains LOW (no light pulse generated), and signal transitions on SIRIN have no effect. 1 = IrDA SIR ENDEC is enabled. Data is transmitted and received on nSIROUT and SIRIN. UARTTXD remains HIGH, in the marking state. Signal transitions on UARTRXD or modem status inputs have no effect. This bit has no effect if the UARTEN bit disables the UART.
bits : 1 - 1 (1 bit)
access : read-write

SIRLP : SIR low-power IrDA mode. This bit selects the IrDA encoding mode. If this bit is cleared to 0, low-level bits are transmitted as an active high pulse with a width of 3 / 16th of the bit period. If this bit is set to 1, low-level bits are transmitted with a pulse width that is 3 times the period of the IrLPBaud16 input signal, regardless of the selected bit rate. Setting this bit uses less power, but might reduce transmission distances.
bits : 2 - 2 (1 bit)
access : read-write

LBE : Loopback enable. If this bit is set to 1 and the SIREN bit is set to 1 and the SIRTEST bit in the Test Control Register, UARTTCR is set to 1, then the nSIROUT path is inverted, and fed through to the SIRIN path. The SIRTEST bit in the test register must be set to 1 to override the normal half-duplex SIR operation. This must be the requirement for accessing the test registers during normal operation, and SIRTEST must be cleared to 0 when loopback testing is finished. This feature reduces the amount of external coupling required during system test. If this bit is set to 1, and the SIRTEST bit is set to 0, the UARTTXD path is fed through to the UARTRXD path. In either SIR mode or UART mode, when this bit is set, the modem outputs are also fed through to the modem inputs. This bit is cleared to 0 on reset, to disable loopback.
bits : 7 - 7 (1 bit)
access : read-write

TXE : Transmit enable. If this bit is set to 1, the transmit section of the UART is enabled. Data transmission occurs for either UART signals, or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of transmission, it completes the current character before stopping.
bits : 8 - 8 (1 bit)
access : read-write

RXE : Receive enable. If this bit is set to 1, the receive section of the UART is enabled. Data reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of reception, it completes the current character before stopping.
bits : 9 - 9 (1 bit)
access : read-write

DTR : Data transmit ready. This bit is the complement of the UART data transmit ready, nUARTDTR, modem status output. That is, when the bit is programmed to a 1 then nUARTDTR is LOW.
bits : 10 - 10 (1 bit)
access : read-write

RTS : Request to send. This bit is the complement of the UART request to send, nUARTRTS, modem status output. That is, when the bit is programmed to a 1 then nUARTRTS is LOW.
bits : 11 - 11 (1 bit)
access : read-write

OUT1 : This bit is the complement of the UART Out1 (nUARTOut1) modem status output. That is, when the bit is programmed to a 1 the output is 0. For DTE this can be used as Data Carrier Detect (DCD).
bits : 12 - 12 (1 bit)
access : read-write

OUT2 : This bit is the complement of the UART Out2 (nUARTOut2) modem status output. That is, when the bit is programmed to a 1, the output is 0. For DTE this can be used as Ring Indicator (RI).
bits : 13 - 13 (1 bit)
access : read-write

RTSEN : RTS hardware flow control enable. If this bit is set to 1, RTS hardware flow control is enabled. Data is only requested when there is space in the receive FIFO for it to be received.
bits : 14 - 14 (1 bit)
access : read-write

CTSEN : CTS hardware flow control enable. If this bit is set to 1, CTS hardware flow control is enabled. Data is only transmitted when the nUARTCTS signal is asserted.
bits : 15 - 15 (1 bit)
access : read-write

TXIFLSEL : Transmit interrupt FIFO level select. The trigger points for the transmit interrupt are as follows: b000 = Transmit FIFO becomes <= 1 / 8 full b001 = Transmit FIFO becomes <= 1 / 4 full b010 = Transmit FIFO becomes <= 1 / 2 full b011 = Transmit FIFO becomes <= 3 / 4 full b100 = Transmit FIFO becomes <= 7 / 8 full b101-b111 = reserved.
bits : 0 - 2 (3 bit)
access : read-write

RXIFLSEL : Receive interrupt FIFO level select. The trigger points for the receive interrupt are as follows: b000 = Receive FIFO becomes >= 1 / 8 full b001 = Receive FIFO becomes >= 1 / 4 full b010 = Receive FIFO becomes >= 1 / 2 full b011 = Receive FIFO becomes >= 3 / 4 full b100 = Receive FIFO becomes >= 7 / 8 full b101-b111 = reserved.
bits : 3 - 5 (3 bit)
access : read-write

RIMIM : nUARTRI modem interrupt mask. A read returns the current mask for the UARTRIINTR interrupt. On a write of 1, the mask of the UARTRIINTR interrupt is set. A write of 0 clears the mask.
bits : 0 - 0 (1 bit)
access : read-write

CTSMIM : nUARTCTS modem interrupt mask. A read returns the current mask for the UARTCTSINTR interrupt. On a write of 1, the mask of the UARTCTSINTR interrupt is set. A write of 0 clears the mask.
bits : 1 - 1 (1 bit)
access : read-write

DCDMIM : nUARTDCD modem interrupt mask. A read returns the current mask for the UARTDCDINTR interrupt. On a write of 1, the mask of the UARTDCDINTR interrupt is set. A write of 0 clears the mask.
bits : 2 - 2 (1 bit)
access : read-write

DSRMIM : nUARTDSR modem interrupt mask. A read returns the current mask for the UARTDSRINTR interrupt. On a write of 1, the mask of the UARTDSRINTR interrupt is set. A write of 0 clears the mask.
bits : 3 - 3 (1 bit)
access : read-write

RXIM : Receive interrupt mask. A read returns the current mask for the UARTRXINTR interrupt. On a write of 1, the mask of the UARTRXINTR interrupt is set. A write of 0 clears the mask.
bits : 4 - 4 (1 bit)
access : read-write

TXIM : Transmit interrupt mask. A read returns the current mask for the UARTTXINTR interrupt. On a write of 1, the mask of the UARTTXINTR interrupt is set. A write of 0 clears the mask.
bits : 5 - 5 (1 bit)
access : read-write

RTIM : Receive timeout interrupt mask. A read returns the current mask for the UARTRTINTR interrupt. On a write of 1, the mask of the UARTRTINTR interrupt is set. A write of 0 clears the mask.
bits : 6 - 6 (1 bit)
access : read-write

FEIM : Framing error interrupt mask. A read returns the current mask for the UARTFEINTR interrupt. On a write of 1, the mask of the UARTFEINTR interrupt is set. A write of 0 clears the mask.
bits : 7 - 7 (1 bit)
access : read-write

PEIM : Parity error interrupt mask. A read returns the current mask for the UARTPEINTR interrupt. On a write of 1, the mask of the UARTPEINTR interrupt is set. A write of 0 clears the mask.
bits : 8 - 8 (1 bit)
access : read-write

BEIM : Break error interrupt mask. A read returns the current mask for the UARTBEINTR interrupt. On a write of 1, the mask of the UARTBEINTR interrupt is set. A write of 0 clears the mask.
bits : 9 - 9 (1 bit)
access : read-write

OEIM : Overrun error interrupt mask. A read returns the current mask for the UARTOEINTR interrupt. On a write of 1, the mask of the UARTOEINTR interrupt is set. A write of 0 clears the mask.
bits : 10 - 10 (1 bit)
access : read-write

RIRMIS : nUARTRI modem interrupt status. Returns the raw interrupt state of the UARTRIINTR interrupt.
bits : 0 - 0 (1 bit)
access : read-only

CTSRMIS : nUARTCTS modem interrupt status. Returns the raw interrupt state of the UARTCTSINTR interrupt.
bits : 1 - 1 (1 bit)
access : read-only

DCDRMIS : nUARTDCD modem interrupt status. Returns the raw interrupt state of the UARTDCDINTR interrupt.
bits : 2 - 2 (1 bit)
access : read-only

DSRRMIS : nUARTDSR modem interrupt status. Returns the raw interrupt state of the UARTDSRINTR interrupt.
bits : 3 - 3 (1 bit)
access : read-only

RXRIS : Receive interrupt status. Returns the raw interrupt state of the UARTRXINTR interrupt.
bits : 4 - 4 (1 bit)
access : read-only

TXRIS : Transmit interrupt status. Returns the raw interrupt state of the UARTTXINTR interrupt.
bits : 5 - 5 (1 bit)
access : read-only

RTRIS : Receive timeout interrupt status. Returns the raw interrupt state of the UARTRTINTR interrupt. a
bits : 6 - 6 (1 bit)
access : read-only

FERIS : Framing error interrupt status. Returns the raw interrupt state of the UARTFEINTR interrupt.
bits : 7 - 7 (1 bit)
access : read-only

PERIS : Parity error interrupt status. Returns the raw interrupt state of the UARTPEINTR interrupt.
bits : 8 - 8 (1 bit)
access : read-only

BERIS : Break error interrupt status. Returns the raw interrupt state of the UARTBEINTR interrupt.
bits : 9 - 9 (1 bit)
access : read-only

OERIS : Overrun error interrupt status. Returns the raw interrupt state of the UARTOEINTR interrupt.
bits : 10 - 10 (1 bit)
access : read-only

FE : Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO.
bits : 0 - 0 (1 bit)
access : read-write

PE : Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO.
bits : 1 - 1 (1 bit)
access : read-write

BE : Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity, and stop bits). This bit is cleared to 0 after a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received.
bits : 2 - 2 (1 bit)
access : read-write

OE : Overrun error. This bit is set to 1 if data is received and the FIFO is already full. This bit is cleared to 0 by a write to UARTECR. The FIFO contents remain valid because no more data is written when the FIFO is full, only the contents of the shift register are overwritten. The CPU must now read the data, to empty the FIFO.
bits : 3 - 3 (1 bit)
access : read-write

RIMMIS : nUARTRI modem masked interrupt status. Returns the masked interrupt state of the UARTRIINTR interrupt.
bits : 0 - 0 (1 bit)
access : read-only

CTSMMIS : nUARTCTS modem masked interrupt status. Returns the masked interrupt state of the UARTCTSINTR interrupt.
bits : 1 - 1 (1 bit)
access : read-only

DCDMMIS : nUARTDCD modem masked interrupt status. Returns the masked interrupt state of the UARTDCDINTR interrupt.
bits : 2 - 2 (1 bit)
access : read-only

DSRMMIS : nUARTDSR modem masked interrupt status. Returns the masked interrupt state of the UARTDSRINTR interrupt.
bits : 3 - 3 (1 bit)
access : read-only

RXMIS : Receive masked interrupt status. Returns the masked interrupt state of the UARTRXINTR interrupt.
bits : 4 - 4 (1 bit)
access : read-only

TXMIS : Transmit masked interrupt status. Returns the masked interrupt state of the UARTTXINTR interrupt.
bits : 5 - 5 (1 bit)
access : read-only

RTMIS : Receive timeout masked interrupt status. Returns the masked interrupt state of the UARTRTINTR interrupt.
bits : 6 - 6 (1 bit)
access : read-only

FEMIS : Framing error masked interrupt status. Returns the masked interrupt state of the UARTFEINTR interrupt.
bits : 7 - 7 (1 bit)
access : read-only

PEMIS : Parity error masked interrupt status. Returns the masked interrupt state of the UARTPEINTR interrupt.
bits : 8 - 8 (1 bit)
access : read-only

BEMIS : Break error masked interrupt status. Returns the masked interrupt state of the UARTBEINTR interrupt.
bits : 9 - 9 (1 bit)
access : read-only

OEMIS : Overrun error masked interrupt status. Returns the masked interrupt state of the UARTOEINTR interrupt.
bits : 10 - 10 (1 bit)
access : read-only

RIMIC : nUARTRI modem interrupt clear. Clears the UARTRIINTR interrupt.
bits : 0 - 0 (1 bit)
access : read-write

CTSMIC : nUARTCTS modem interrupt clear. Clears the UARTCTSINTR interrupt.
bits : 1 - 1 (1 bit)
access : read-write

DCDMIC : nUARTDCD modem interrupt clear. Clears the UARTDCDINTR interrupt.
bits : 2 - 2 (1 bit)
access : read-write

DSRMIC : nUARTDSR modem interrupt clear. Clears the UARTDSRINTR interrupt.
bits : 3 - 3 (1 bit)
access : read-write

RXIC : Receive interrupt clear. Clears the UARTRXINTR interrupt.
bits : 4 - 4 (1 bit)
access : read-write

TXIC : Transmit interrupt clear. Clears the UARTTXINTR interrupt.
bits : 5 - 5 (1 bit)
access : read-write

RTIC : Receive timeout interrupt clear. Clears the UARTRTINTR interrupt.
bits : 6 - 6 (1 bit)
access : read-write

FEIC : Framing error interrupt clear. Clears the UARTFEINTR interrupt.
bits : 7 - 7 (1 bit)
access : read-write

PEIC : Parity error interrupt clear. Clears the UARTPEINTR interrupt.
bits : 8 - 8 (1 bit)
access : read-write

BEIC : Break error interrupt clear. Clears the UARTBEINTR interrupt.
bits : 9 - 9 (1 bit)
access : read-write

OEIC : Overrun error interrupt clear. Clears the UARTOEINTR interrupt.
bits : 10 - 10 (1 bit)
access : read-write

RXDMAE : Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is enabled.
bits : 0 - 0 (1 bit)
access : read-write

TXDMAE : Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is enabled.
bits : 1 - 1 (1 bit)
access : read-write

DMAONERR : DMA on error. If this bit is set to 1, the DMA receive request outputs, UARTRXDMASREQ or UARTRXDMABREQ, are disabled when the UART error interrupt is asserted.
bits : 2 - 2 (1 bit)
access : read-write

PARTNUMBER0 : These bits read back as 0x11
bits : 0 - 7 (8 bit)
access : read-only

PARTNUMBER1 : These bits read back as 0x0
bits : 0 - 3 (4 bit)
access : read-only

DESIGNER0 : These bits read back as 0x1
bits : 4 - 7 (4 bit)
access : read-only

DESIGNER1 : These bits read back as 0x4
bits : 0 - 3 (4 bit)
access : read-only

REVISION : This field depends on the revision of the UART: r1p0 0x0 r1p1 0x1 r1p3 0x2 r1p4 0x2 r1p5 0x3
bits : 4 - 7 (4 bit)
access : read-only

CONFIGURATION : These bits read back as 0x00
bits : 0 - 7 (8 bit)
access : read-only

UARTPCELLID0 : These bits read back as 0x0D
bits : 0 - 7 (8 bit)
access : read-only

UARTPCELLID1 : These bits read back as 0xF0
bits : 0 - 7 (8 bit)
access : read-only

UARTPCELLID2 : These bits read back as 0x05
bits : 0 - 7 (8 bit)
access : read-only

UARTPCELLID3 : These bits read back as 0xB1
bits : 0 - 7 (8 bit)
access : read-only