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SPI0

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

SSPCR0

SSPCPSR

SSPIMSC

SSPRIS

SSPMIS

SSPICR

SSPDMACR

SSPCR1

SSPDR

SSPSR

SSPPERIPHID0

SSPPERIPHID1

SSPPERIPHID2

SSPPERIPHID3

SSPPCELLID0

SSPPCELLID1

SSPPCELLID2

SSPPCELLID3


SSPCR0

Control register 0, SSPCR0 on page 3-4
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSPCR0 SSPCR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSS FRF SPO SPH SCR

DSS : Data Size Select: 0000 Reserved, undefined operation. 0001 Reserved, undefined operation. 0010 Reserved, undefined operation. 0011 4-bit data. 0100 5-bit data. 0101 6-bit data. 0110 7-bit data. 0111 8-bit data. 1000 9-bit data. 1001 10-bit data. 1010 11-bit data. 1011 12-bit data. 1100 13-bit data. 1101 14-bit data. 1110 15-bit data. 1111 16-bit data.
bits : 0 - 3 (4 bit)
access : read-write

FRF : Frame format: 00 Motorola SPI frame format. 01 TI synchronous serial frame format. 10 National Microwire frame format. 11 Reserved, undefined operation.
bits : 4 - 5 (2 bit)
access : read-write

SPO : SSPCLKOUT polarity, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10.
bits : 6 - 6 (1 bit)
access : read-write

SPH : SSPCLKOUT phase, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10.
bits : 7 - 7 (1 bit)
access : read-write

SCR : Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: F SSPCLK CPSDVSR x (1+SCR) where CPSDVSR is an even value from 2-254, programmed through the SSPCPSR register and SCR is a value from 0-255.
bits : 8 - 15 (8 bit)
access : read-write


SSPCPSR

Clock prescale register, SSPCPSR on page 3-8
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSPCPSR SSPCPSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPSDVSR

CPSDVSR : Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads.
bits : 0 - 7 (8 bit)
access : read-write


SSPIMSC

Interrupt mask set or clear register, SSPIMSC on page 3-9
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSPIMSC SSPIMSC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RORIM RTIM RXIM TXIM

RORIM : Receive overrun interrupt mask: 0 Receive FIFO written to while full condition interrupt is masked. 1 Receive FIFO written to while full condition interrupt is not masked.
bits : 0 - 0 (1 bit)
access : read-write

RTIM : Receive timeout interrupt mask: 0 Receive FIFO not empty and no read prior to timeout period interrupt is masked. 1 Receive FIFO not empty and no read prior to timeout period interrupt is not masked.
bits : 1 - 1 (1 bit)
access : read-write

RXIM : Receive FIFO interrupt mask: 0 Receive FIFO half full or less condition interrupt is masked. 1 Receive FIFO half full or less condition interrupt is not masked.
bits : 2 - 2 (1 bit)
access : read-write

TXIM : Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or less condition interrupt is masked. 1 Transmit FIFO half empty or less condition interrupt is not masked.
bits : 3 - 3 (1 bit)
access : read-write


SSPRIS

Raw interrupt status register, SSPRIS on page 3-10
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSPRIS SSPRIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RORRIS RTRIS RXRIS TXRIS

RORRIS : Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt
bits : 0 - 0 (1 bit)
access : read-only

RTRIS : Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt
bits : 1 - 1 (1 bit)
access : read-only

RXRIS : Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt
bits : 2 - 2 (1 bit)
access : read-only

TXRIS : Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt
bits : 3 - 3 (1 bit)
access : read-only


SSPMIS

Masked interrupt status register, SSPMIS on page 3-11
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSPMIS SSPMIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RORMIS RTMIS RXMIS TXMIS

RORMIS : Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt
bits : 0 - 0 (1 bit)
access : read-only

RTMIS : Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt
bits : 1 - 1 (1 bit)
access : read-only

RXMIS : Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt
bits : 2 - 2 (1 bit)
access : read-only

TXMIS : Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt
bits : 3 - 3 (1 bit)
access : read-only


SSPICR

Interrupt clear register, SSPICR on page 3-11
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSPICR SSPICR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RORIC RTIC

RORIC : Clears the SSPRORINTR interrupt
bits : 0 - 0 (1 bit)
access : read-write

RTIC : Clears the SSPRTINTR interrupt
bits : 1 - 1 (1 bit)
access : read-write


SSPDMACR

DMA control register, SSPDMACR on page 3-12
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSPDMACR SSPDMACR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXDMAE TXDMAE

RXDMAE : Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled.
bits : 0 - 0 (1 bit)
access : read-write

TXDMAE : Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled.
bits : 1 - 1 (1 bit)
access : read-write


SSPCR1

Control register 1, SSPCR1 on page 3-5
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSPCR1 SSPCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LBM SSE MS SOD

LBM : Loop back mode: 0 Normal serial port operation enabled. 1 Output of transmit serial shifter is connected to input of receive serial shifter internally.
bits : 0 - 0 (1 bit)
access : read-write

SSE : Synchronous serial port enable: 0 SSP operation disabled. 1 SSP operation enabled.
bits : 1 - 1 (1 bit)
access : read-write

MS : Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0: 0 Device configured as master, default. 1 Device configured as slave.
bits : 2 - 2 (1 bit)
access : read-write

SOD : Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line: 0 SSP can drive the SSPTXD output in slave mode. 1 SSP must not drive the SSPTXD output in slave mode.
bits : 3 - 3 (1 bit)
access : read-write


SSPDR

Data register, SSPDR on page 3-6
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSPDR SSPDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Transmit/Receive FIFO: Read Receive FIFO. Write Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies.
bits : 0 - 15 (16 bit)
access : read-write


SSPSR

Status register, SSPSR on page 3-7
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSPSR SSPSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TFE TNF RNE RFF BSY

TFE : Transmit FIFO empty, RO: 0 Transmit FIFO is not empty. 1 Transmit FIFO is empty.
bits : 0 - 0 (1 bit)
access : read-only

TNF : Transmit FIFO not full, RO: 0 Transmit FIFO is full. 1 Transmit FIFO is not full.
bits : 1 - 1 (1 bit)
access : read-only

RNE : Receive FIFO not empty, RO: 0 Receive FIFO is empty. 1 Receive FIFO is not empty.
bits : 2 - 2 (1 bit)
access : read-only

RFF : Receive FIFO full, RO: 0 Receive FIFO is not full. 1 Receive FIFO is full.
bits : 3 - 3 (1 bit)
access : read-only

BSY : PrimeCell SSP busy flag, RO: 0 SSP is idle. 1 SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty.
bits : 4 - 4 (1 bit)
access : read-only


SSPPERIPHID0

Peripheral identification registers, SSPPeriphID0-3 on page 3-13
address_offset : 0xFE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSPPERIPHID0 SSPPERIPHID0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PARTNUMBER0

PARTNUMBER0 : These bits read back as 0x22
bits : 0 - 7 (8 bit)
access : read-only


SSPPERIPHID1

Peripheral identification registers, SSPPeriphID0-3 on page 3-13
address_offset : 0xFE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSPPERIPHID1 SSPPERIPHID1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PARTNUMBER1 DESIGNER0

PARTNUMBER1 : These bits read back as 0x0
bits : 0 - 3 (4 bit)
access : read-only

DESIGNER0 : These bits read back as 0x1
bits : 4 - 7 (4 bit)
access : read-only


SSPPERIPHID2

Peripheral identification registers, SSPPeriphID0-3 on page 3-13
address_offset : 0xFE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSPPERIPHID2 SSPPERIPHID2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DESIGNER1 REVISION

DESIGNER1 : These bits read back as 0x4
bits : 0 - 3 (4 bit)
access : read-only

REVISION : These bits return the peripheral revision
bits : 4 - 7 (4 bit)
access : read-only


SSPPERIPHID3

Peripheral identification registers, SSPPeriphID0-3 on page 3-13
address_offset : 0xFEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSPPERIPHID3 SSPPERIPHID3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CONFIGURATION

CONFIGURATION : These bits read back as 0x00
bits : 0 - 7 (8 bit)
access : read-only


SSPPCELLID0

PrimeCell identification registers, SSPPCellID0-3 on page 3-16
address_offset : 0xFF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSPPCELLID0 SSPPCELLID0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SSPPCELLID0

SSPPCELLID0 : These bits read back as 0x0D
bits : 0 - 7 (8 bit)
access : read-only


SSPPCELLID1

PrimeCell identification registers, SSPPCellID0-3 on page 3-16
address_offset : 0xFF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSPPCELLID1 SSPPCELLID1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SSPPCELLID1

SSPPCELLID1 : These bits read back as 0xF0
bits : 0 - 7 (8 bit)
access : read-only


SSPPCELLID2

PrimeCell identification registers, SSPPCellID0-3 on page 3-16
address_offset : 0xFF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSPPCELLID2 SSPPCELLID2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SSPPCELLID2

SSPPCELLID2 : These bits read back as 0x05
bits : 0 - 7 (8 bit)
access : read-only


SSPPCELLID3

PrimeCell identification registers, SSPPCellID0-3 on page 3-16
address_offset : 0xFFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSPPCELLID3 SSPPCELLID3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SSPPCELLID3

SSPPCELLID3 : These bits read back as 0xB1
bits : 0 - 7 (8 bit)
access : read-only



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