IC_CON

IC_DATA_CMD

IC_SS_SCL_HCNT

IC_SS_SCL_LCNT

IC_FS_SCL_HCNT

IC_FS_SCL_LCNT

IC_INTR_STAT

IC_INTR_MASK

IC_RAW_INTR_STAT

IC_RX_TL

IC_TX_TL

IC_TAR

IC_CLR_INTR

IC_CLR_RX_UNDER

IC_CLR_RX_OVER

IC_CLR_TX_OVER

IC_CLR_RD_REQ

IC_CLR_TX_ABRT

IC_CLR_RX_DONE

IC_CLR_ACTIVITY

IC_CLR_STOP_DET

IC_CLR_START_DET

IC_CLR_GEN_CALL

IC_ENABLE

IC_STATUS

IC_TXFLR

IC_RXFLR

IC_SDA_HOLD

IC_SAR

IC_TX_ABRT_SOURCE

IC_SLV_DATA_NACK_ONLY

IC_DMA_CR

IC_DMA_TDLR

IC_DMA_RDLR

IC_SDA_SETUP

IC_ACK_GENERAL_CALL

IC_ENABLE_STATUS

IC_FS_SPKLEN

IC_CLR_RESTART_DET

IC_COMP_PARAM_1

IC_COMP_VERSION

IC_COMP_TYPE

MASTER_MODE : This bit controls whether the DW_apb_i2c master is enabled. NOTE: Software should ensure that if this bit is written with '1' then bit 6 should also be written with a '1'.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPEED : These bits control at which speed the DW_apb_i2c operates its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode. This register should be programmed only with a value in the range of 1 to IC_MAX_SPEED_MODE otherwise, hardware updates this register with the value of IC_MAX_SPEED_MODE. 1: standard mode (100 kbit/s) 2: fast mode (<=400 kbit/s) or fast mode plus (<=1000Kbit/s) 3: high speed mode (3.4 Mbit/s) Note: This field is not applicable when IC_ULTRA_FAST_MODE=1
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IC_10BITADDR_SLAVE : When acting as a slave, this bit controls whether the DW_apb_i2c responds to 7- or 10-bit addresses. - 0: 7-bit addressing. The DW_apb_i2c ignores transactions that involve 10-bit addressing for 7-bit addressing, only the lower 7 bits of the IC_SAR register are compared. - 1: 10-bit addressing. The DW_apb_i2c responds to only 10-bit addressing transfers that match the full 10 bits of the IC_SAR register.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IC_10BITADDR_MASTER : Controls whether the DW_apb_i2c starts its transfers in 7- or 10-bit addressing mode when acting as a master. - 0: 7-bit addressing - 1: 10-bit addressing
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IC_RESTART_EN : Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions however, RESTART conditions are used in several DW_apb_i2c operations. When RESTART is disabled, the master is prohibited from performing the following functions: - Sending a START BYTE - Performing any high-speed mode operation - High-speed mode operation - Performing direction changes in combined format mode - Performing a read operation with a 10-bit address By replacing RESTART condition followed by a STOP and a subsequent START condition, split operations are broken down into multiple DW_apb_i2c transfers. If the above operations are performed, it will result in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. Reset value: ENABLED
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IC_SLAVE_DISABLE : This bit controls whether I2C has its slave disabled, which means once the presetn signal is applied, then this bit is set and the slave is disabled. If this bit is set (slave is disabled), DW_apb_i2c functions only as a master and does not perform any action that requires a slave. NOTE: Software should ensure that if this bit is written with 0, then bit 0 should also be written with a 0.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

STOP_DET_IFADDRESSED : In slave mode: - 1'b1: issues the STOP_DET interrupt only when it is addressed. - 1'b0: issues the STOP_DET irrespective of whether it's addressed or not. Reset value: 0x0 NOTE: During a general call address, this slave does not issue the STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR).
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TX_EMPTY_CTRL : This bit controls the generation of the TX_EMPTY interrupt, as described in the IC_RAW_INTR_STAT register. Reset value: 0x0.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RX_FIFO_FULL_HLD_CTRL : This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH, as described in the IC_RX_FULL_HLD_BUS_EN parameter. Reset value: 0x0.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

STOP_DET_IF_MASTER_ACTIVE : Master issues the STOP_DET interrupt irrespective of whether master is active or not
bits : 10 - 10 (1 bit)
access : read-only

DAT : This register contains the data to be transmitted or received on the I2C bus. If you are writing to this register and want to perform a read, bits 7:0 (DAT) are ignored by the DW_apb_i2c. However, when you read this register, these bits return the value of data received on the DW_apb_i2c interface. Reset value: 0x0
bits : 0 - 7 (8 bit)
access : read-write

CMD : This bit controls whether a read or a write is performed. This bit does not control the direction when the DW_apb_i2con acts as a slave. It controls only the direction when it acts as a master. When a command is entered in the TX FIFO, this bit distinguishes the write and read commands. In slave-receiver mode, this bit is a 'don't care' because writes to this register are not required. In slave-transmitter mode, a '0' indicates that the data in IC_DATA_CMD is to be transmitted. When programming this bit, you should remember the following: attempting to perform a read operation after a General Call command has been sent results in a TX_ABRT interrupt (bit 6 of the IC_RAW_INTR_STAT register), unless bit 11 (SPECIAL) in the IC_TAR register has been cleared. If a '1' is written to this bit after receiving a RD_REQ interrupt, then a TX_ABRT interrupt occurs. Reset value: 0x0
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

STOP : This bit controls whether a STOP is issued after the byte is sent or received. - 1 - STOP is issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master immediately tries to start a new transfer by issuing a START and arbitrating for the bus. - 0 - STOP is not issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master continues the current transfer by sending/receiving data bytes according to the value of the CMD bit. If the Tx FIFO is empty, the master holds the SCL line low and stalls the bus until a new command is available in the Tx FIFO. Reset value: 0x0
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RESTART : This bit controls whether a RESTART is issued before the byte is sent or received. 1 - If IC_RESTART_EN is 1, a RESTART is issued before the data is sent/received (according to the value of CMD), regardless of whether or not the transfer direction is changing from the previous command if IC_RESTART_EN is 0, a STOP followed by a START is issued instead. 0 - If IC_RESTART_EN is 1, a RESTART is issued only if the transfer direction is changing from the previous command if IC_RESTART_EN is 0, a STOP followed by a START is issued instead. Reset value: 0x0
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FIRST_DATA_BYTE : Indicates the first data byte received after the address phase for receive transfer in Master receiver or Slave receiver mode. Reset value : 0x0 NOTE: In case of APB_DATA_WIDTH=8, 1. The user has to perform two APB Reads to IC_DATA_CMD in order to get status on 11 bit. 2. In order to read the 11 bit, the user has to perform the first data byte read [7:0] (offset 0x10) and then perform the second read [15:8] (offset 0x11) in order to know the status of 11 bit (whether the data received in previous read is a first data byte or not). 3. The 11th bit is an optional read field, user can ignore 2nd byte read [15:8] (offset 0x11) if not interested in FIRST_DATA_BYTE status.
bits : 11 - 11 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

IC_SS_SCL_HCNT : This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration'. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. The minimum valid value is 6 hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. NOTE: This register must not be programmed to a value higher than 65525, because DW_apb_i2c uses a 16-bit counter to flag an I2C bus idle condition when this counter reaches a value of IC_SS_SCL_HCNT + 10.
bits : 0 - 15 (16 bit)
access : read-write

IC_SS_SCL_LCNT : This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration' This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. The minimum valid value is 8 hardware prevents values less than this being written, and if attempted, results in 8 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of DW_apb_i2c. The lower byte must be programmed first, and then the upper byte is programmed.
bits : 0 - 15 (16 bit)
access : read-write

IC_FS_SCL_HCNT : This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for fast mode or fast mode plus. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'. This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. The minimum valid value is 6 hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH == 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed.
bits : 0 - 15 (16 bit)
access : read-write

IC_FS_SCL_LCNT : This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for fast speed. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'. This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. The minimum valid value is 8 hardware prevents values less than this being written, and if attempted results in 8 being set. For designs with APB_DATA_WIDTH = 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. If the value is less than 8 then the count value gets changed to 8.
bits : 0 - 15 (16 bit)
access : read-write

R_RX_UNDER : See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER bit. Reset value: 0x0
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

R_RX_OVER : See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER bit. Reset value: 0x0
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

R_RX_FULL : See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL bit. Reset value: 0x0
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

R_TX_OVER : See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER bit. Reset value: 0x0
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

R_TX_EMPTY : See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY bit. Reset value: 0x0
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

R_RD_REQ : See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ bit. Reset value: 0x0
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

R_TX_ABRT : See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT bit. Reset value: 0x0
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

R_RX_DONE : See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE bit. Reset value: 0x0
bits : 7 - 7 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

R_ACTIVITY : See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY bit. Reset value: 0x0
bits : 8 - 8 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

R_STOP_DET : See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET bit. Reset value: 0x0
bits : 9 - 9 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

R_START_DET : See IC_RAW_INTR_STAT for a detailed description of R_START_DET bit. Reset value: 0x0
bits : 10 - 10 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

R_GEN_CALL : See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL bit. Reset value: 0x0
bits : 11 - 11 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

R_RESTART_DET : See IC_RAW_INTR_STAT for a detailed description of R_RESTART_DET bit. Reset value: 0x0
bits : 12 - 12 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

R_MASTER_ON_HOLD : See IC_RAW_INTR_STAT for a detailed description of R_MASTER_ON_HOLD bit.\n\n Reset value: 0x0
bits : 13 - 26 (14 bit)
access : read-only

Enumeration:

End of enumeration elements list.

M_RX_UNDER : This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register. Reset value: 0x1
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

M_RX_OVER : This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register. Reset value: 0x1
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

M_RX_FULL : This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register. Reset value: 0x1
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

M_TX_OVER : This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register. Reset value: 0x1
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

M_TX_EMPTY : This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register. Reset value: 0x1
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

M_RD_REQ : This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register. Reset value: 0x1
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

M_TX_ABRT : This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register. Reset value: 0x1
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

M_RX_DONE : This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register. Reset value: 0x1
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

M_ACTIVITY : This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register. Reset value: 0x0
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

M_STOP_DET : This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register. Reset value: 0x0
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

M_START_DET : This bit masks the R_START_DET interrupt in IC_INTR_STAT register. Reset value: 0x0
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

M_GEN_CALL : This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register. Reset value: 0x1
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

M_RESTART_DET : This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register. Reset value: 0x0
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

M_MASTER_ON_HOLD_READ_ONLY : This M_MASTER_ON_HOLD_read_only bit masks the R_MASTER_ON_HOLD interrupt in IC_INTR_STAT register.\n\n Reset value: 0x0
bits : 13 - 26 (14 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RX_UNDER : Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register. If the module is disabled (IC_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. Reset value: 0x0
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RX_OVER : Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device. The DW_apb_i2c acknowledges this, but any data bytes received after the FIFO is full are lost. If the module is disabled (IC_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. Note: If bit 9 of the IC_CON register (RX_FIFO_FULL_HLD_CTRL) is programmed to HIGH, then the RX_OVER interrupt never occurs, because the Rx FIFO never overflows. Reset value: 0x0
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RX_FULL : Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register. It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled (IC_ENABLE[0]=0), the RX FIFO is flushed and held in reset therefore the RX FIFO is not full. So this bit is cleared once the IC_ENABLE bit 0 is programmed with a 0, regardless of the activity that continues. Reset value: 0x0
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TX_OVER : Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. When the module is disabled, this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. Reset value: 0x0
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TX_EMPTY : The behavior of the TX_EMPTY interrupt status differs based on the TX_EMPTY_CTRL selection in the IC_CON register. - When TX_EMPTY_CTRL = 0: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register. - When TX_EMPTY_CTRL = 1: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register and the transmission of the address/data from the internal shift register for the most recently popped command is completed. It is automatically cleared by hardware when the buffer level goes above the threshold. When IC_ENABLE[0] is set to 0, the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no data within it, so this bit is set to 1, provided there is activity in the master or slave state machines. When there is no longer any activity, then with ic_en=0, this bit is set to 0. Reset value: 0x0.
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RD_REQ : This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is attempting to read data from DW_apb_i2c. The DW_apb_i2c holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which means that the slave has been addressed by a remote master that is asking for data to be transferred. The processor must respond to this interrupt and then write the requested data to the IC_DATA_CMD register. This bit is set to 0 just after the processor reads the IC_CLR_RD_REQ register. Reset value: 0x0
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TX_ABRT : This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave, and is referred to as a 'transmit abort'. When this bit is set to 1, the IC_TX_ABRT_SOURCE register indicates the reason why the transmit abort takes places. Note: The DW_apb_i2c flushes/resets/empties the TX_FIFO and RX_FIFO whenever there is a transmit abort caused by any of the events tracked by the IC_TX_ABRT_SOURCE register. The FIFOs remains in this flushed state until the register IC_CLR_TX_ABRT is read. Once this read is performed, the Tx FIFO is then ready to accept more data bytes from the APB interface. Reset value: 0x0
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RX_DONE : When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating that the transmission is done. Reset value: 0x0
bits : 7 - 7 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ACTIVITY : This bit captures DW_apb_i2c activity and stays set until it is cleared. There are four ways to clear it: - Disabling the DW_apb_i2c - Reading the IC_CLR_ACTIVITY register - Reading the IC_CLR_INTR register - System reset Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the DW_apb_i2c module is idle, this bit remains set until cleared, indicating that there was activity on the bus. Reset value: 0x0
bits : 8 - 8 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

STOP_DET : Indicates whether a STOP condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. In Slave Mode: - If IC_CON[7]=1'b1 (STOP_DET_IFADDRESSED), the STOP_DET interrupt will be issued only if slave is addressed. Note: During a general call address, this slave does not issue a STOP_DET interrupt if STOP_DET_IF_ADDRESSED=1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR). - If IC_CON[7]=1'b0 (STOP_DET_IFADDRESSED), the STOP_DET interrupt is issued irrespective of whether it is being addressed. In Master Mode: - If IC_CON[10]=1'b1 (STOP_DET_IF_MASTER_ACTIVE),the STOP_DET interrupt will be issued only if Master is active. - If IC_CON[10]=1'b0 (STOP_DET_IFADDRESSED),the STOP_DET interrupt will be issued irrespective of whether master is active or not. Reset value: 0x0
bits : 9 - 9 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

START_DET : Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. Reset value: 0x0
bits : 10 - 10 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

GEN_CALL : Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling DW_apb_i2c or when the CPU reads bit 0 of the IC_CLR_GEN_CALL register. DW_apb_i2c stores the received data in the Rx buffer. Reset value: 0x0
bits : 11 - 11 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RESTART_DET : Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in Slave mode and the slave is being addressed. Enabled only when IC_SLV_RESTART_DET_EN=1. Note: However, in high-speed mode or during a START BYTE transfer, the RESTART comes before the address field as per the I2C protocol. In this case, the slave is not the addressed slave when the RESTART is issued, therefore DW_apb_i2c does not generate the RESTART_DET interrupt. Reset value: 0x0
bits : 12 - 12 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

MASTER_ON_HOLD : Indicates whether master is holding the bus and TX FIFO is empty. Enabled only when I2C_DYNAMIC_TAR_UPDATE=1 and IC_EMPTYFIFO_HOLD_MASTER_EN=1.\n\n Reset value: 0x0
bits : 13 - 26 (14 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RX_TL : Receive FIFO Threshold Level. Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that hardware does not allow this value to be set to a value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 1 entry, and a value of 255 sets the threshold for 256 entries.
bits : 0 - 7 (8 bit)
access : read-write

TX_TL : Transmit FIFO Threshold Level. Controls the level of entries (or below) that trigger the TX_EMPTY interrupt (bit 4 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that it may not be set to value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 0 entries, and a value of 255 sets the threshold for 255 entries.
bits : 0 - 7 (8 bit)
access : read-write

IC_TAR : This is the target address for any master transaction. When transmitting a General Call, these bits are ignored. To generate a START BYTE, the CPU needs to write only once into these bits. If the IC_TAR and IC_SAR are the same, loopback exists but the FIFOs are shared between master and slave, so full loopback is not feasible. Only one direction loopback mode is supported (simplex), not duplex. A master cannot transmit to itself it can transmit to only a slave.
bits : 0 - 9 (10 bit)
access : read-write

GC_OR_START : If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0, then this bit indicates whether a General Call or START byte command is to be performed by the DW_apb_i2c. - 0: General Call Address - after issuing a General Call, only writes may be performed. Attempting to issue a read command results in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. The DW_apb_i2c remains in General Call mode until the SPECIAL bit value (bit 11) is cleared. - 1: START BYTE Reset value: 0x0
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPECIAL : This bit indicates whether software performs a Device-ID or General Call or START BYTE command. - 0: ignore bit 10 GC_OR_START and use IC_TAR normally - 1: perform special I2C command as specified in Device_ID or GC_OR_START bit Reset value: 0x0
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLR_INTR : Read this register to clear the combined interrupt, all individual interrupts, and the IC_TX_ABRT_SOURCE register. This bit does not clear hardware clearable interrupts but software clearable interrupts. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE. Reset value: 0x0
bits : 0 - 0 (1 bit)
access : read-only

CLR_RX_UNDER : Read this register to clear the RX_UNDER interrupt (bit 0) of the IC_RAW_INTR_STAT register. Reset value: 0x0
bits : 0 - 0 (1 bit)
access : read-only

CLR_RX_OVER : Read this register to clear the RX_OVER interrupt (bit 1) of the IC_RAW_INTR_STAT register. Reset value: 0x0
bits : 0 - 0 (1 bit)
access : read-only

CLR_TX_OVER : Read this register to clear the TX_OVER interrupt (bit 3) of the IC_RAW_INTR_STAT register. Reset value: 0x0
bits : 0 - 0 (1 bit)
access : read-only

CLR_RD_REQ : Read this register to clear the RD_REQ interrupt (bit 5) of the IC_RAW_INTR_STAT register. Reset value: 0x0
bits : 0 - 0 (1 bit)
access : read-only

CLR_TX_ABRT : Read this register to clear the TX_ABRT interrupt (bit 6) of the IC_RAW_INTR_STAT register, and the IC_TX_ABRT_SOURCE register. This also releases the TX FIFO from the flushed/reset state, allowing more writes to the TX FIFO. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE. Reset value: 0x0
bits : 0 - 0 (1 bit)
access : read-only

CLR_RX_DONE : Read this register to clear the RX_DONE interrupt (bit 7) of the IC_RAW_INTR_STAT register. Reset value: 0x0
bits : 0 - 0 (1 bit)
access : read-only

CLR_ACTIVITY : Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore. If the I2C module is still active on the bus, the ACTIVITY interrupt bit continues to be set. It is automatically cleared by hardware if the module is disabled and if there is no further activity on the bus. The value read from this register to get status of the ACTIVITY interrupt (bit 8) of the IC_RAW_INTR_STAT register. Reset value: 0x0
bits : 0 - 0 (1 bit)
access : read-only

CLR_STOP_DET : Read this register to clear the STOP_DET interrupt (bit 9) of the IC_RAW_INTR_STAT register. Reset value: 0x0
bits : 0 - 0 (1 bit)
access : read-only

CLR_START_DET : Read this register to clear the START_DET interrupt (bit 10) of the IC_RAW_INTR_STAT register. Reset value: 0x0
bits : 0 - 0 (1 bit)
access : read-only

CLR_GEN_CALL : Read this register to clear the GEN_CALL interrupt (bit 11) of IC_RAW_INTR_STAT register. Reset value: 0x0
bits : 0 - 0 (1 bit)
access : read-only

ENABLE : Controls whether the DW_apb_i2c is enabled. - 0: Disables DW_apb_i2c (TX and RX FIFOs are held in an erased state) - 1: Enables DW_apb_i2c Software can disable DW_apb_i2c while it is active. However, it is important that care be taken to ensure that DW_apb_i2c is disabled properly. A recommended procedure is described in 'Disabling DW_apb_i2c'. When DW_apb_i2c is disabled, the following occurs: - The TX FIFO and RX FIFO get flushed. - Status bits in the IC_INTR_STAT register are still active until DW_apb_i2c goes into IDLE state. If the module is transmitting, it stops as well as deletes the contents of the transmit buffer after the current transfer is complete. If the module is receiving, the DW_apb_i2c stops the current transfer at the end of the current byte and does not acknowledge the transfer. In systems with asynchronous pclk and ic_clk when IC_CLK_TYPE parameter set to asynchronous (1), there is a two ic_clk delay when enabling or disabling the DW_apb_i2c. For a detailed description on how to disable DW_apb_i2c, refer to 'Disabling DW_apb_i2c' Reset value: 0x0
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ABORT : When set, the controller initiates the transfer abort. - 0: ABORT not initiated or ABORT done - 1: ABORT operation in progress The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when ENABLE is already set otherwise, the controller ignores any write to ABORT bit. The software cannot clear the ABORT bit once set. In response to an ABORT, the controller issues a STOP and flushes the Tx FIFO after completing the current transfer, then sets the TX_ABORT interrupt after the abort operation. The ABORT bit is cleared automatically after the abort operation. For a detailed description on how to abort I2C transfers, refer to 'Aborting I2C Transfers'. Reset value: 0x0
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TX_CMD_BLOCK : In Master mode: - 1'b1: Blocks the transmission of data on I2C bus even if Tx FIFO has data to transmit. - 1'b0: The transmission of data starts on I2C bus automatically, as soon as the first data is available in the Tx FIFO. Note: To block the execution of Master commands, set the TX_CMD_BLOCK bit only when Tx FIFO is empty (IC_STATUS[2]==1) and Master is in Idle state (IC_STATUS[5] == 0). Any further commands put in the Tx FIFO are not executed until TX_CMD_BLOCK bit is unset. Reset value: IC_TX_CMD_BLOCK_DEFAULT
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ACTIVITY : I2C Activity Status. Reset value: 0x0
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TFNF : Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty locations, and is cleared when the FIFO is full. - 0: Transmit FIFO is full - 1: Transmit FIFO is not full Reset value: 0x1
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TFE : Transmit FIFO Completely Empty. When the transmit FIFO is completely empty, this bit is set. When it contains one or more valid entries, this bit is cleared. This bit field does not request an interrupt. - 0: Transmit FIFO is not empty - 1: Transmit FIFO is empty Reset value: 0x1
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RFNE : Receive FIFO Not Empty. This bit is set when the receive FIFO contains one or more entries it is cleared when the receive FIFO is empty. - 0: Receive FIFO is empty - 1: Receive FIFO is not empty Reset value: 0x0
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RFF : Receive FIFO Completely Full. When the receive FIFO is completely full, this bit is set. When the receive FIFO contains one or more empty location, this bit is cleared. - 0: Receive FIFO is not full - 1: Receive FIFO is full Reset value: 0x0
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

MST_ACTIVITY : Master FSM Activity Status. When the Master Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Master FSM is in IDLE state so the Master part of DW_apb_i2c is not Active - 1: Master FSM is not in IDLE state so the Master part of DW_apb_i2c is Active Note: IC_STATUS[0]-that is, ACTIVITY bit-is the OR of SLV_ACTIVITY and MST_ACTIVITY bits. Reset value: 0x0
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

SLV_ACTIVITY : Slave FSM Activity Status. When the Slave Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Slave FSM is in IDLE state so the Slave part of DW_apb_i2c is not Active - 1: Slave FSM is not in IDLE state so the Slave part of DW_apb_i2c is Active Reset value: 0x0
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TXFLR : Transmit FIFO Level. Contains the number of valid data entries in the transmit FIFO. Reset value: 0x0
bits : 0 - 4 (5 bit)
access : read-only

RXFLR : Receive FIFO Level. Contains the number of valid data entries in the receive FIFO. Reset value: 0x0
bits : 0 - 4 (5 bit)
access : read-only

IC_SDA_TX_HOLD : Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a transmitter. Reset value: IC_DEFAULT_SDA_HOLD[15:0].
bits : 0 - 15 (16 bit)
access : read-write

IC_SDA_RX_HOLD : Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a receiver. Reset value: IC_DEFAULT_SDA_HOLD[23:16].
bits : 16 - 23 (8 bit)
access : read-write

IC_SAR : The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit addressing, only IC_SAR[6:0] is used. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. Note: The default values cannot be any of the reserved address locations: that is, 0x00 to 0x07, or 0x78 to 0x7f. The correct operation of the device is not guaranteed if you program the IC_SAR or IC_TAR to a reserved value. Refer to <<table_I2C_firstbyte_bit_defs>> for a complete list of these reserved values.
bits : 0 - 9 (10 bit)
access : read-write

ABRT_7B_ADDR_NOACK : This field indicates that the Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Master-Receiver
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ABRT_10ADDR1_NOACK : This field indicates that the Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Master-Receiver
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ABRT_10ADDR2_NOACK : This field indicates that the Master is in 10-bit address mode and that the second address byte of the 10-bit address was not acknowledged by any slave. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Master-Receiver
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ABRT_TXDATA_NOACK : This field indicates the master-mode only bit. When the master receives an acknowledgement for the address, but when it sends data byte(s) following the address, it did not receive an acknowledge from the remote slave(s). Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ABRT_GCALL_NOACK : This field indicates that DW_apb_i2c in master mode has sent a General Call and no slave on the bus acknowledged the General Call. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ABRT_GCALL_READ : This field indicates that DW_apb_i2c in the master mode has sent a General Call but the user programmed the byte following the General Call to be a read from the bus (IC_DATA_CMD[9] is set to 1). Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ABRT_HS_ACKDET : This field indicates that the Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior). Reset value: 0x0 Role of DW_apb_i2c: Master
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ABRT_SBYTE_ACKDET : This field indicates that the Master has sent a START Byte and the START Byte was acknowledged (wrong behavior). Reset value: 0x0 Role of DW_apb_i2c: Master
bits : 7 - 7 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ABRT_HS_NORSTRT : This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to use the master to transfer data in High Speed mode. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Master-Receiver
bits : 8 - 8 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ABRT_SBYTE_NORSTRT : To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first restart must be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]). Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, bit 9 clears for one cycle and then gets reasserted. When this field is set to 1, the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to send a START Byte. Reset value: 0x0 Role of DW_apb_i2c: Master
bits : 9 - 9 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ABRT_10B_RD_NORSTRT : This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the master sends a read command in 10-bit addressing mode. Reset value: 0x0 Role of DW_apb_i2c: Master-Receiver
bits : 10 - 10 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ABRT_MASTER_DIS : This field indicates that the User tries to initiate a Master operation with the Master mode disabled. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Master-Receiver
bits : 11 - 11 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ARB_LOST : This field specifies that the Master has lost arbitration, or if IC_TX_ABRT_SOURCE[14] is also set, then the slave transmitter has lost arbitration. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter
bits : 12 - 12 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ABRT_SLVFLUSH_TXFIFO : This field specifies that the Slave has received a read command and some data exists in the TX FIFO, so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO. Reset value: 0x0 Role of DW_apb_i2c: Slave-Transmitter
bits : 13 - 13 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ABRT_SLV_ARBLOST : This field indicates that a Slave has lost the bus while transmitting data to a remote master. IC_TX_ABRT_SOURCE[12] is set at the same time. Note: Even though the slave never 'owns' the bus, something could go wrong on the bus. This is a fail safe check. For instance, during a data transmission at the low-to-high transition of SCL, if what is on the data bus is not what is supposed to be transmitted, then DW_apb_i2c no longer own the bus. Reset value: 0x0 Role of DW_apb_i2c: Slave-Transmitter
bits : 14 - 14 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ABRT_SLVRD_INTX : 1: When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of IC_DATA_CMD register. Reset value: 0x0 Role of DW_apb_i2c: Slave-Transmitter
bits : 15 - 15 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ABRT_USER_ABRT : This is a master-mode-only bit. Master has detected the transfer abort (IC_ENABLE[1]) Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter
bits : 16 - 16 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TX_FLUSH_CNT : This field indicates the number of Tx FIFO Data Commands which are flushed due to TX_ABRT interrupt. It is cleared whenever I2C is disabled. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter
bits : 23 - 31 (9 bit)
access : read-only

NACK : Generate NACK. This NACK generation only occurs when DW_apb_i2c is a slave-receiver. If this register is set to a value of 1, it can only generate a NACK after a data byte is received hence, the data transfer is aborted and the data received is not pushed to the receive buffer. When the register is set to a value of 0, it generates NACK/ACK, depending on normal criteria. - 1: generate NACK after data byte received - 0: generate NACK/ACK normally Reset value: 0x0
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RDMAE : Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel. Reset value: 0x0
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TDMAE : Transmit DMA Enable. This bit enables/disables the transmit FIFO DMA channel. Reset value: 0x0
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DMATDL : Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level that is, the dma_tx_req signal is generated when the number of valid data entries in the transmit FIFO is equal to or below this field value, and TDMAE = 1. Reset value: 0x0
bits : 0 - 3 (4 bit)
access : read-write

DMARDL : Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level = DMARDL+1 that is, dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or more than this field value + 1, and RDMAE =1. For instance, when DMARDL is 0, then dma_rx_req is asserted when 1 or more data entries are present in the receive FIFO. Reset value: 0x0
bits : 0 - 3 (4 bit)
access : read-write

SDA_SETUP : SDA Setup. It is recommended that if the required delay is 1000ns, then for an ic_clk frequency of 10 MHz, IC_SDA_SETUP should be programmed to a value of 11. IC_SDA_SETUP must be programmed with a minimum value of 2.
bits : 0 - 7 (8 bit)
access : read-write

ACK_GEN_CALL : ACK General Call. When set to 1, DW_apb_i2c responds with a ACK (by asserting ic_data_oe) when it receives a General Call. Otherwise, DW_apb_i2c responds with a NACK (by negating ic_data_oe).
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IC_EN : ic_en Status. This bit always reflects the value driven on the output port ic_en. - When read as 1, DW_apb_i2c is deemed to be in an enabled state. - When read as 0, DW_apb_i2c is deemed completely inactive. Note: The CPU can safely read this bit anytime. When this bit is read as 0, the CPU can safely read SLV_RX_DATA_LOST (bit 2) and SLV_DISABLED_WHILE_BUSY (bit 1). Reset value: 0x0
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

SLV_DISABLED_WHILE_BUSY : Slave Disabled While Busy (Transmit, Receive). This bit indicates if a potential or active Slave operation has been aborted due to the setting bit 0 of the IC_ENABLE register from 1 to 0. This bit is set when the CPU writes a 0 to the IC_ENABLE register while: (a) DW_apb_i2c is receiving the address byte of the Slave-Transmitter operation from a remote master OR, (b) address and data bytes of the Slave-Receiver operation from a remote master. When read as 1, DW_apb_i2c is deemed to have forced a NACK during any part of an I2C transfer, irrespective of whether the I2C address matches the slave address set in DW_apb_i2c (IC_SAR register) OR if the transfer is completed before IC_ENABLE is set to 0 but has not taken effect. Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE[0] has been set to 0, then this bit will also be set to 1. When read as 0, DW_apb_i2c is deemed to have been disabled when there is master activity, or when the I2C bus is idle. Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0. Reset value: 0x0
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

SLV_RX_DATA_LOST : Slave Received Data Lost. This bit indicates if a Slave-Receiver operation has been aborted with at least one data byte received from an I2C transfer due to the setting bit 0 of IC_ENABLE from 1 to 0. When read as 1, DW_apb_i2c is deemed to have been actively engaged in an aborted I2C transfer (with matching address) and the data phase of the I2C transfer has been entered, even though a data byte has been responded with a NACK. Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE[0] has been set to 0, then this bit is also set to 1. When read as 0, DW_apb_i2c is deemed to have been disabled without being actively involved in the data phase of a Slave-Receiver transfer. Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0. Reset value: 0x0
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

IC_FS_SPKLEN : This register must be set before any I2C bus transaction can take place to ensure stable operation. This register sets the duration, measured in ic_clk cycles, of the longest spike in the SCL or SDA lines that will be filtered out by the spike suppression logic. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. The minimum valid value is 1 hardware prevents values less than this being written, and if attempted results in 1 being set. or more information, refer to 'Spike Suppression'.
bits : 0 - 7 (8 bit)
access : read-write