CS

DIV

INTR

INTE

INTF

INTS

RESULT

FCS

FIFO

EN : Power on ADC and enable its clock. 1 - enabled. 0 - disabled.
bits : 0 - 0 (1 bit)
access : read-write

TS_EN : Power on temperature sensor. 1 - enabled. 0 - disabled.
bits : 1 - 1 (1 bit)
access : read-write

START_ONCE : Start a single conversion. Self-clearing. Ignored if start_many is asserted.
bits : 2 - 2 (1 bit)
access : read-write

START_MANY : Continuously perform conversions whilst this bit is 1. A new conversion will start immediately after the previous finishes.
bits : 3 - 3 (1 bit)
access : read-write

READY : 1 if the ADC is ready to start a new conversion. Implies any previous conversion has completed. 0 whilst conversion in progress.
bits : 8 - 8 (1 bit)
access : read-only

ERR : The most recent ADC conversion encountered an error result is undefined or noisy.
bits : 9 - 9 (1 bit)
access : read-only

ERR_STICKY : Some past ADC conversion encountered an error. Write 1 to clear.
bits : 10 - 10 (1 bit)
access : read-write

AINSEL : Select analog mux input. Updated automatically in round-robin mode.
bits : 12 - 14 (3 bit)
access : read-write

RROBIN : Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable. Otherwise, the ADC will cycle through each enabled channel in a round-robin fashion. The first channel to be sampled will be the one currently indicated by AINSEL. AINSEL will be updated after each conversion with the newly-selected channel.
bits : 16 - 20 (5 bit)
access : read-write

FRAC : Fractional part of clock divisor. First-order delta-sigma.
bits : 0 - 7 (8 bit)
access : read-write

INT : Integer part of clock divisor.
bits : 8 - 23 (16 bit)
access : read-write

FIFO : Triggered when the sample FIFO reaches a certain level. This level can be programmed via the FCS_THRESH field.
bits : 0 - 0 (1 bit)
access : read-only

FIFO : Triggered when the sample FIFO reaches a certain level. This level can be programmed via the FCS_THRESH field.
bits : 0 - 0 (1 bit)
access : read-write

FIFO : Triggered when the sample FIFO reaches a certain level. This level can be programmed via the FCS_THRESH field.
bits : 0 - 0 (1 bit)
access : read-write

FIFO : Triggered when the sample FIFO reaches a certain level. This level can be programmed via the FCS_THRESH field.
bits : 0 - 0 (1 bit)
access : read-only

RESULT :
bits : 0 - 11 (12 bit)
access : read-only

EN : If 1: write result to the FIFO after each conversion.
bits : 0 - 0 (1 bit)
access : read-write

SHIFT : If 1: FIFO results are right-shifted to be one byte in size. Enables DMA to byte buffers.
bits : 1 - 1 (1 bit)
access : read-write

ERR : If 1: conversion error bit appears in the FIFO alongside the result
bits : 2 - 2 (1 bit)
access : read-write

DREQ_EN : If 1: assert DMA requests when FIFO contains data
bits : 3 - 3 (1 bit)
access : read-write

EMPTY :
bits : 8 - 8 (1 bit)
access : read-only

FULL :
bits : 9 - 9 (1 bit)
access : read-only

UNDER : 1 if the FIFO has been underflowed. Write 1 to clear.
bits : 10 - 10 (1 bit)
access : read-write

OVER : 1 if the FIFO has been overflowed. Write 1 to clear.
bits : 11 - 11 (1 bit)
access : read-write

LEVEL : The number of conversion results currently waiting in the FIFO
bits : 16 - 19 (4 bit)
access : read-only

THRESH : DREQ/IRQ asserted when level >= threshold
bits : 24 - 27 (4 bit)
access : read-write

VAL :
bits : 0 - 11 (12 bit)
access : read-only

ERR : 1 if this particular sample experienced a conversion error. Remains in the same location if the sample is shifted.
bits : 15 - 15 (1 bit)
access : read-only