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ROSC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CTRL

DIV

PHASE

STATUS

RANDOMBIT

COUNT

FREQA

FREQB

DORMANT


CTRL

Ring Oscillator control
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FREQ_RANGE ENABLE

FREQ_RANGE : Controls the number of delay stages in the ROSC ring LOW uses stages 0 to 7 MEDIUM uses stages 0 to 5 HIGH uses stages 0 to 3 TOOHIGH uses stages 0 to 1 and should not be used because its frequency exceeds design specifications The clock output will not glitch when changing the range up one step at a time The clock output will glitch when changing the range down Note: the values here are gray coded which is why HIGH comes before TOOHIGH
bits : 0 - 11 (12 bit)
access : read-write

Enumeration:

4004 : LOW

None

4005 : MEDIUM

None

4007 : HIGH

None

4006 : TOOHIGH

None

End of enumeration elements list.

ENABLE : On power-up this field is initialised to ENABLE The system clock must be switched to another source before setting this field to DISABLE otherwise the chip will lock up The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator.
bits : 12 - 23 (12 bit)
access : read-write

Enumeration:

3358 : DISABLE

None

4011 : ENABLE

None

End of enumeration elements list.


DIV

Controls the output divider
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIV DIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIV

DIV : set to 0xaa0 + div where div = 0 divides by 32 div = 1-31 divides by div any other value sets div=31 this register resets to div=16
bits : 0 - 11 (12 bit)
access : read-write

Enumeration:

2720 : PASS

None

End of enumeration elements list.


PHASE

Controls the phase shifted output
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PHASE PHASE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SHIFT FLIP ENABLE PASSWD

SHIFT : phase shift the phase-shifted output by SHIFT input clocks this can be changed on-the-fly must be set to 0 before setting div=1
bits : 0 - 1 (2 bit)
access : read-write

FLIP : invert the phase-shifted output this is ignored when div=1
bits : 2 - 2 (1 bit)
access : read-write

ENABLE : enable the phase-shifted output this can be changed on-the-fly
bits : 3 - 3 (1 bit)
access : read-write

PASSWD : set to 0xaa any other value enables the output with shift=0
bits : 4 - 11 (8 bit)
access : read-write


STATUS

Ring Oscillator Status
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLED DIV_RUNNING BADWRITE STABLE

ENABLED : Oscillator is enabled but not necessarily running and stable this resets to 0 but transitions to 1 during chip startup
bits : 12 - 12 (1 bit)
access : read-only

DIV_RUNNING : post-divider is running this resets to 0 but transitions to 1 during chip startup
bits : 16 - 16 (1 bit)
access : read-only

BADWRITE : An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or FREQA or FREQB or DIV or PHASE or DORMANT
bits : 24 - 24 (1 bit)
access : read-write

STABLE : Oscillator is running and stable
bits : 31 - 31 (1 bit)
access : read-only


RANDOMBIT

This just reads the state of the oscillator output so randomness is compromised if the ring oscillator is stopped or run at a harmonic of the bus frequency
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RANDOMBIT RANDOMBIT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RANDOMBIT

RANDOMBIT :
bits : 0 - 0 (1 bit)
access : read-only


COUNT

A down counter running at the ROSC frequency which counts to zero and stops. To start the counter write a non-zero value. Can be used for short software pauses when setting up time sensitive hardware.
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COUNT COUNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT

COUNT :
bits : 0 - 7 (8 bit)
access : read-write


FREQA

The FREQA & FREQB registers control the frequency by controlling the drive strength of each stage The drive strength has 4 levels determined by the number of bits set Increasing the number of bits set increases the drive strength and increases the oscillation frequency 0 bits set is the default drive strength 1 bit set doubles the drive strength 2 bits set triples drive strength 3 bits set quadruples drive strength
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FREQA FREQA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DS0 DS1 DS2 DS3 PASSWD

DS0 : Stage 0 drive strength
bits : 0 - 2 (3 bit)
access : read-write

DS1 : Stage 1 drive strength
bits : 4 - 6 (3 bit)
access : read-write

DS2 : Stage 2 drive strength
bits : 8 - 10 (3 bit)
access : read-write

DS3 : Stage 3 drive strength
bits : 12 - 14 (3 bit)
access : read-write

PASSWD : Set to 0x9696 to apply the settings Any other value in this field will set all drive strengths to 0
bits : 16 - 31 (16 bit)
access : read-write

Enumeration:

38550 : PASS

None

End of enumeration elements list.


FREQB

For a detailed description see freqa register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FREQB FREQB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DS4 DS5 DS6 DS7 PASSWD

DS4 : Stage 4 drive strength
bits : 0 - 2 (3 bit)
access : read-write

DS5 : Stage 5 drive strength
bits : 4 - 6 (3 bit)
access : read-write

DS6 : Stage 6 drive strength
bits : 8 - 10 (3 bit)
access : read-write

DS7 : Stage 7 drive strength
bits : 12 - 14 (3 bit)
access : read-write

PASSWD : Set to 0x9696 to apply the settings Any other value in this field will set all drive strengths to 0
bits : 16 - 31 (16 bit)
access : read-write

Enumeration:

38550 : PASS

None

End of enumeration elements list.


DORMANT

Ring Oscillator pause control This is used to save power by pausing the ROSC On power-up this field is initialised to WAKE An invalid write will also select WAKE Warning: setup the irq before selecting dormant mode
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DORMANT DORMANT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


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