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VREG_AND_CHIP_RESET

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

VREG

BOD

CHIP_RESET


VREG

Voltage regulator control and status
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VREG VREG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN HIZ VSEL ROK

EN : enable 0=not enabled, 1=enabled
bits : 0 - 0 (1 bit)
access : read-write

HIZ : high impedance mode select 0=not in high impedance mode, 1=in high impedance mode
bits : 1 - 1 (1 bit)
access : read-write

VSEL : output voltage select 0000 to 0101 - 0.80V 0110 - 0.85V 0111 - 0.90V 1000 - 0.95V 1001 - 1.00V 1010 - 1.05V 1011 - 1.10V (default) 1100 - 1.15V 1101 - 1.20V 1110 - 1.25V 1111 - 1.30V
bits : 4 - 7 (4 bit)
access : read-write

ROK : regulation status 0=not in regulation, 1=in regulation
bits : 12 - 12 (1 bit)
access : read-only


BOD

brown-out detection control
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BOD BOD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN VSEL

EN : enable 0=not enabled, 1=enabled
bits : 0 - 0 (1 bit)
access : read-write

VSEL : threshold select 0000 - 0.473V 0001 - 0.516V 0010 - 0.559V 0011 - 0.602V 0100 - 0.645V 0101 - 0.688V 0110 - 0.731V 0111 - 0.774V 1000 - 0.817V 1001 - 0.860V (default) 1010 - 0.903V 1011 - 0.946V 1100 - 0.989V 1101 - 1.032V 1110 - 1.075V 1111 - 1.118V
bits : 4 - 7 (4 bit)
access : read-write


CHIP_RESET

Chip reset control and status
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHIP_RESET CHIP_RESET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HAD_POR HAD_RUN HAD_PSM_RESTART PSM_RESTART_FLAG

HAD_POR : Last reset was from the power-on reset or brown-out detection blocks
bits : 8 - 8 (1 bit)
access : read-only

HAD_RUN : Last reset was from the RUN pin
bits : 16 - 16 (1 bit)
access : read-only

HAD_PSM_RESTART : Last reset was from the debug port
bits : 20 - 20 (1 bit)
access : read-only

PSM_RESTART_FLAG : This is set by psm_restart from the debugger. Its purpose is to branch bootcode to a safe mode when the debugger has issued a psm_restart in order to recover from a boot lock-up. In the safe mode the debugger can repair the boot code, clear this flag then reboot the processor.
bits : 24 - 24 (1 bit)
access : read-write



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